Lecture 11 – Flip-Flops Borivoje...

inst.eecs.berkeley.edu/~ee241b

Borivoje Nikolić

EE241B : Advanced Digital Circuits

Lecture 11 – Flip-Flops

February 25, 2020, NY Times: Should robots

have a face?

As automation comes to retail industries, companies are giving machines more humanlike features in order to make them liked, not feared.

1EECS241B L11 FLIP-FLOPS

Announcements

• Response to project abstracts sent• Please let me know if you didn’t receive it

• Team web pages

• Be careful not to leak proprietary info (interface tools via Hammer)

• Assignment 2 posted

2EECS241B L11 FLIP-FLOPS

Outline

• Module 3• Design of latches and flip-flops

3EECS241B L11 FLIP-FLOPS

3. Design for Performance

3.D Latch Design

4EECS241B L11 FLIP-FLOPS

MUX

• 2-input MUX

A

Sel

YSel

B

Sel

Sel

SelA

Sel

Sel

B

Y

A

B

Sel

1

0

Y

EECS241B L11 FLIP-FLOPS 5

Transmission Gates

EECS241B L11 FLIP-FLOPS 6

S

A

S

Y

Latch vs. Flip-Flop

Courtesy of IEEE Press, New York. 2000EECS241B L11 FLIP-FLOPS 7

Latches

D

Clk

Clk

Q

Clk

D

Clk

Q

Transmission-Gate Latch C2MOS Latch

EECS241B L11 FLIP-FLOPS 8

Usually without contention

Latches

Courtesy of IEEE Press, New York. 2000EECS241B L11 FLIP-FLOPS 9

Clk-Q Delay

TSetup-1

TClk-Q

Time

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1

EECS241B L11 FLIP-FLOPS 10

Clk-Q Delay

TSetup-1

TClk-Q

Time

Timet=0

ClockDataTSetup-1

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

EECS241B L11 FLIP-FLOPS 11

Clk-Q Delay

TSetup-1

TClk-Q

Time

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)

EECS241B L11 FLIP-FLOPS 12

Clk-Q Delay

TSetup-1

TClk-Q

Time

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)

EECS241B L11 FLIP-FLOPS 13

Timet=0

ClockDataTSetup-1

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Setup-Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)

Clk-Q Delay

TSetup-1

TClk-Q

Time

EECS241B L11 FLIP-FLOPS 14

Setup-Hold Time Illustrations

Hold-1 case

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Timet=0

0

Clk-Q Delay

THold-1

TClk-Q

Time

EECS241B L11 FLIP-FLOPS 15

Clk-Q Delay

THold-1

TClk-Q

Time

Setup-Hold Time Illustrations

Hold-1 case

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

0

EECS241B L11 FLIP-FLOPS 16

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Setup-Hold Time Illustrations

Hold-1 case

0

EECS241B L11 FLIP-FLOPS 17

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Setup-Hold Time Illustrations

Hold-1 case

0

EECS241B L11 FLIP-FLOPS 18

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1 SM

Inv1

Inv2TG1

Timet=0

ClockTHold-1

Data

Setup-Hold Time Illustrations

Hold-1 case

0

EECS241B L11 FLIP-FLOPS 19

More Precise Setup Time

tD 2 C

t

t

t

tC 2 Q1.05tC 2 Q

tSu

tH

Clk

D

Q

(a)

Td-clk

1.05(tclk-q)

tclk-q

EECS241B L11 FLIP-FLOPS 20

Generating Complementary Clocks

EECS241B L11 FLIP-FLOPS 21

Latch tD-Q and tClk-Q

EECS241B L11 FLIP-FLOPS 22

tsetup

EECS241B L11 FLIP-FLOPS 23

Key Point

• Two ways to design a flip-flop• Latch pair

• Pulsed latch

EECS241B L11 FLIP-FLOPS 24

3. Design for Performance

3.E Flip-Flop Design

25EECS241B L11 FLIP-FLOPS

Latch vs. Flip-Flop

Courtesy of IEEE Press, New York. 2000EECS241B L11 FLIP-FLOPS 26

Flip-Flops

• Performance metrics

• Delay metrics• Insertion delay

• Inherent race immunity

• ‘Softness’ (Clock skew absorption)

• Inclusion of logic

• Small (+constant) clock load

• Power/Energy Metrics• Power/energy

• Design robustness• Noise immunity

EECS241B L11 FLIP-FLOPS 27

Scan Test

EECS241B L11 FLIP-FLOPS 28