Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic · PDF file · 2015-08-11Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic December 20, ... M bits Storage cell M bits S 0 S

© Digital Integrated Circuits2nd Memories

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

SemiconductorSemiconductorMemoriesMemories

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic

December 20, 2002


Chapter OverviewChapter Overview

Memory ClassificationMemory ArchitecturesThe Memory CorePeripheryReliabilityCase Studies


Semiconductor Memory ClassificationSemiconductor Memory Classification

Read-Write MemoryNon-VolatileRead-Write

MemoryRead-Only Memory

EPROM

E2PROM

FLASH

RandomAccess

Non-RandomAccess

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

CAM

LIFO


Memory Timing: DefinitionsMemory Timing: Definitions

Write cycleRead access Read access

Read cycle

Write access

Data written

Data valid

DATA

WRITE

READ


Memory Architecture: DecodersMemory Architecture: Decoders

Word 0

Word 1

Word 2

Word N2 2

Word N2 1

M bits

Storagecell

M bits

S0

S1

S2

SN2 2

SN2 1

A 0

A 1

A K2 1

K 5 log2N

Word 0

Word 1

Word 2

Word N2 2

Word N2 1

Storagecell

S0

Input-Output(M bits)

Intuitive architecture for N x M memoryToo many select signals:

N words == N select signals K = log2NDecoder reduces the number of select signals



ArrayArray--Structured Memory ArchitectureStructured Memory Architecture

Row

Dec

oder

Bit line2L 2 K

Word line

AK

AK1 1

AL 2 1

A0

M.2K

AK2 1

Sense amplifiers / Drivers

Column decoder


Storage cell

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing torail-to-rail amplitude

Selects appropriateword


Hierarchical Memory ArchitectureHierarchical Memory Architecture

Advantages:Advantages:1. Shorter wires within blocks1. Shorter wires within blocks2. Block address activates only 1 block => power savings2. Block address activates only 1 block => power savings

Globalamplifier/driver

Controlcircuitry

Global data busBlock selector

Block 0

Rowaddress

Columnaddress

Blockaddress

Block i Block P 2 1

I/O


Block Diagram of 4 Block Diagram of 4 MbitMbit SRAMSRAMClock

generator

CS, WEbuffer

I/Obuffer

Y-addressbuffer

X -addressbuffer

x1/x4controller

Z -addressbuffer

X -addressbuffer

Predecoder and block selectorBit line load

Transfer gateColumn decoder

Sense amplifier and write driver

[Hirose90]


ContentsContents--Addressable MemoryAddressable Memory

Add

ress

Dec

oder

Data (64 bits)

I/O B

uffe

rs

Comparand

CAM Array29 words 3 64 bits

Mask

Control Logic R/W Address (9 bits)

Com

man

ds

29 Val

idity

Bits

Prio

rity

Enc

oder


Memory Timing: ApproachesMemory Timing: Approaches

DRAM TimingMultiplexed Adressing

SRAM TimingSelf-timed

Addressbus

RAS

RAS-CAS timing

Row Address

AddressBus

Address transitioninitiates memory operation

Address

Column Address

CAS


ReadRead--Only Memory CellsOnly Memory Cells

WL

BL

WL

BL

1WL

BL

WL

BL

WL

BL

0

VDD

WL

BL

GND

Diode ROM MOS ROM 1 MOS ROM 2


MOS OR ROMMOS OR ROM

WL[0]

VDD

BL[0]

WL[1]

WL[2]

WL[3]

Vbias

BL[1]

Pull-down loads

BL[2] BL[3]

VDD


MOS NOR ROMMOS NOR ROM

WL[0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Pull-up devices

BL [2] BL [3]

GND


MOS NOR ROM LayoutMOS NOR ROM Layout

Programmming using theActive Layer Only

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (9.5λ x 7λ)


MOS NOR ROM LayoutMOS NOR ROM Layout

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (11λ x 7λ)

Programmming usingthe Contact Layer Only


MOS NAND ROMMOS NAND ROM

All word lines high by default with exception of selected row

WL [0]

WL [1]

WL [2]

WL [3]

VDD

Pull-up devices

BL[3]BL[2]BL[1]BL [0]


MOS NAND ROM LayoutMOS NAND ROM Layout

No contact to VDD or GND necessary;

Loss in performance compared to NOR ROMdrastically reduced cell size

Polysilicon

Diffusion

Metal1 on Diffusion

Cell (8λ x 7λ)

Programmming usingthe Metal-1 Layer Only


NAND ROM LayoutNAND ROM LayoutCell (5λ x 6λ)

Polysilicon

Threshold-alteringimplant

Metal1 on Diffusion

Programmming usingImplants Only


Equivalent Transient Model for MOS NOR ROMEquivalent Transient Model for MOS NOR ROM

Word line parasiticsWire capacitance and gate capacitanceWire resistance (polysilicon)

Bit line parasiticsResistance not dominant (metal)Drain and Gate-Drain capacitance

Model for NOR ROM VDD

Cbit

rword

cword

WL

BL


Equivalent Transient Model for MOS NAND ROMEquivalent Transient Model for MOS NAND ROM

Word line parasiticsSimilar to NOR ROM

Bit line parasiticsResistance of cascaded transistors dominatesDrain/Source and complete gate capacitance

Model for NAND ROMVDD

CL

rword

cword

cbit

rbit

WL

BL


Decreasing Word Line DelayDecreasing Word Line Delay

Metal bypass

Polysilicon word lineK cells

Polysilicon word lineWLDriver

(b) Using a metal bypass

(a) Driving the word line from both sides

Metal word line

WL

(c) Use silicides


PrechargedPrecharged MOS NOR ROMMOS NOR ROM

PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.

WL [0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Precharge devices

BL [2] BL [3]

GND

pref


NonNon--Volatile MemoriesVolatile MemoriesThe FloatingThe Floating--gate transistor (FAMOS)gate transistor (FAMOS)

Floating gate

Source

Substrate

Gate

Drain

n+ n+_p

tox

tox

Device cross-section Schematic symbol

G

S

D


FloatingFloating--Gate Transistor ProgrammingGate Transistor Programming

0 V

2 5 V 0 V

DS

Removing programming voltage leaves charge trapped

5 V

2 2.5 V 5 V

DS

Programming results inhigher VT.

20 V

10 V 5 V 20 V

DS

Avalanche injection


A A ““ProgrammableProgrammable--ThresholdThreshold”” TransistorTransistor

“ 0” -state “ 1” -state

DVT

VWL VGS

“ ON ”

“ OFF”

ID


FLOTOX EEPROMFLOTOX EEPROMFloating gate

Source

Substratep

Gate

Drain

n1 n1

FLOTOX transistor Fowler-NordheimI-V characteristic

20–30 nm

10 nm

-10 V10 V

I

VGD


EEPROM CellEEPROM Cell

WL

BL

VDD

Absolute threshold controlis hardUnprogrammed transistor might be depletion

2 transistor cell


Flash EEPROMFlash EEPROM

Control gate

erasure

p-substrate

Floating gate

Thin tunneling oxide

n1 source n1 drainprogramming

Many other options …


CrossCross--sections of NVM cellssections of NVM cells

EPROMFlashCourtesy Intel


Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――EraseErase

S D

12 VG

cell arrayBL 0 BL 1

open open

WL 0

WL 1

0 V

0 V

12 V


Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――WriteWrite

S D

12 V

6 VG

BL 0 BL 1

6 V 0 V

WL 0

WL 1

12 V

0 V

0 V


Basic Operations in a NOR Flash MemoryBasic Operations in a NOR Flash Memory――ReadRead

5 V

1 VG

S D

BL 0 BL 1

1 V 0 V

WL 0

WL 1

5 V

0 V

0 V


NAND Flash MemoryNAND Flash Memory

Unit Cell

Word line(poly)

Source line(Diff. Layer)

Courtesy Toshiba

GateONO

FGGateOxide


NAND Flash MemoryNAND Flash Memory

Word linesSelect transistor

Bit line contact Source line contact

Active area

STI

Courtesy Toshiba


Characteristics of StateCharacteristics of State--ofof--thethe--art NVMart NVM


ReadRead--Write Memories (RAM)Write Memories (RAM)STATIC (SRAM)

DYNAMIC (DRAM)

Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential

Periodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle Ended


66--transistor CMOS SRAM Cell transistor CMOS SRAM Cell

WL

BL

VDD

M5M6

M4

M1

M2

M3

BL

QQ


CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)WL

BL

VDD

M 5M 6

M 4

M1 VDDVDD VDD

BL

Q = 1Q = 0

Cbit Cbit


CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)

00

0.2

0.4

0.6

0.8

1

1.2

0.5 1 1.2 1.5 2Cell Ratio (CR)

2.5 3

V o l t a g e r i s e [ V ]

Vol

tage

Ris

e (V

)


CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write)

BL = 1 BL = 0

Q = 0Q = 1

M1

M4

M5

M6

VDD

VDD

WL


CMOS SRAM Analysis (Write)CMOS SRAM Analysis (Write)


6T6T--SRAM SRAM —— Layout Layout VDD

GND

QQ

WL

BLBL

M1 M3

M4M2

M5 M6


ResistanceResistance--load SRAM Cellload SRAM Cell

Static power dissipation -- Want RL largeBit lines precharged to VDD to address tp problem

M3

RL RL

VDD

WL

Q Q

M1 M2

M4

BL BL


SRAM CharacteristicsSRAM Characteristics


33--Transistor DRAM CellTransistor DRAM Cell

No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTn

WWL

BL1

M1 X

M3

M2

CS

BL2

RWL

V DD

VDD 2 VT

DVV DD 2 VTBL 2

BL 1

X

RWL

WWL


3T3T--DRAM DRAM —— LayoutLayout

BL2 BL1 GND

RWL

WWL

M3

M2

M1


11--Transistor DRAM CellTransistor DRAM Cell

Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

M1

CS

WL

BL

CBL

VDD 2 VT

WL

X

sensing

BL

GND

Write 1 Read 1

VDD

VDD /2 VDD /2

ΔV BL VPRE– VBIT VPRE–CS

CS CBL+------------= =V


DRAM Cell ObservationsDRAM Cell Observations1T DRAM requires a sense amplifier for each bit line, due

to charge redistribution read-out.DRAM memory cells are single ended in contrast to

SRAM cells.The read-out of the 1T DRAM cell is destructive; read

and refresh operations are necessary for correct operation.

Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.

When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD


Sense Amp OperationSense Amp Operation

DV(1)

V(1)

V(0)t

VPRE

VBL

Sense amp activatedWord line activated


11--T DRAM CellT DRAM Cell

Uses Polysilicon-Diffusion CapacitanceExpensive in Area

M1 wordline

Diffusedbit line

Polysilicongate

Polysiliconplate

Capacitor

Cross-section Layout

Metal word line

Poly

SiO2

Field Oxiden+ n+

Inversion layerinduced byplate bias

Poly


SEM of polySEM of poly--diffusion capacitor 1Tdiffusion capacitor 1T--DRAMDRAM


Advanced 1T DRAM CellsAdvanced 1T DRAM Cells

Cell Plate Si

Capacitor Insulator

Storage Node Poly

2nd Field Oxide

Refilling Poly

Si Substrate

Trench Cell Stacked-capacitor Cell

Capacitor dielectric layerCell plateWord line

Insulating Layer

IsolationTransfer gateStorage electrode


Static CAM Memory CellStatic CAM Memory Cell

• • • • • •

CAM

BitWord

Bit

••• CAM

Bit Bit

CAM

Word

Wired-NOR Match Line

Match M1

M2

M7M6

M4 M5M8 M9

M3int

SWord

••• CAM

Bit Bit

S


CAM in Cache MemoryCAM in Cache Memory

A d d r e s s D e c o d e r

H i t L o g i c

CAM

ARRAY

Input Drivers

Tag HitAddress

SRAM

ARRAY

Sense Amps / Input Drivers

DataR/W


PeripheryPeriphery

DecodersSense AmplifiersInput/Output BuffersControl / Timing Circuitry


Row DecodersRow DecodersCollection of 2M complex logic gatesOrganized in regular and dense fashion

(N)AND Decoder

NOR Decoder


Hierarchical DecodersHierarchical Decoders

• • •

• • •

A2A2

A2A3

WL 0

A2A3A2A3A2A3

A3 A3A0A0

A0A1A0A1A0A1A0A1

A1 A1

WL 1

Multi-stage implementation improves performance

NAND decoder usingNAND decoder using22--input preinput pre--decodersdecoders


Dynamic DecodersDynamic Decoders

Precharge devices

VDD φ

GND

WL3

WL2

WL1

WL0

A0A0

GND

A1A1φ

WL3

A0A0 A1A1

WL 2

WL 1

WL 0

VDD

VDD

VDD

VDD

2-input NOR decoder 2-input NAND decoder


44--input passinput pass--transistor based column transistor based column decoderdecoder

2 - i n p u t N O R d e c o d e r

Advantages: speed (tpd does not add to overall memory access time)Only one extra transistor in signal path

Disadvantage: Large transistor count

A0S0

BL 0 BL 1 BL 2 BL 3

A1

S1

S2

S3

D


44--toto--1 tree based column decoder1 tree based column decoder

Number of devices drastically reducedDelay increases quadratically with # of sections; prohibitive for large decoders

buffersprogressive sizingcombination of tree and pass transistor approaches

Solutions:

BL 0 BL 1 BL 2 BL 3

D

A 0

A 0

A1

A 1


Decoder for circular shiftDecoder for circular shift--registerregister

V DD

V DD

R

WL 0

V DD

f

ff

f

V DD

R

WL 1

V DD

f

ff

f

V DD

R

WL 2

V DD

f

ff

f• • •


Sense AmplifiersSense Amplifiers

tpC ΔV⋅

Iav----------------=

make ΔV as smallas possible

smalllarge

Idea: Use Sense Amplifer

outputinput

s.a.smalltransition


Differential Sense AmplifierDifferential Sense Amplifier

Directly applicable toSRAMs

M 4

M 1

M 5

M 3

M 2

VDD

bitbit

SE

Outy


Differential Sensing Differential Sensing ―― SRAMSRAMVDD

VDD

VDD

VDD

BLEQ

Diff.SenseAmp

(a) SRAM sensing scheme (b) two stage differential amplifier

SRAM cell i

WL i

2xx

VDD

Output

BL

PC

M3

M1

M5

M2

M4

x

SE

SE

SE

Output

SE

x2x 2x

y

y

2y


LatchLatch--Based Sense Amplifier (DRAM)Based Sense Amplifier (DRAM)

Initialized in its meta-stable point with EQOnce adequate voltage gap created, sense amp enabled with SEPositive feedback quickly forces output to a stable operating point.

EQ

VDD

BL BL

SE

SE


ChargeCharge--Redistribution AmplifierRedistribution Amplifier

0.5

1.0

1.5

2.0

2.5

0.00.0 1.00 2.00

time (nsec)

V

Vin

Vref 5 3V

VL

VS

3.00

Concept

M 2 M 3

M 1VL VS

Vref

CsmallClarge

Transient Response


ChargeCharge--Redistribution AmplifierRedistribution Amplifier――EPROMEPROM

SE

VDD

BL

Out

Cout

Ccol

CBLM1

M2

M3

M4

WLC

Load

Cascodedevice

Columndecoder

EPROMarrayWL

Vcasc


SingleSingle--toto--Differential ConversionDifferential Conversion

How to make a good Vref?

Diff.S.A.Cell

2xx

Output

WL

Vref

BL

12


Open Open bitlinebitline architecture with architecture with dummy cellsdummy cells

CS CS CS CS

BLL

L L 1 L 0 R0

CS

R1

CS

L

… …

BLR

V DD

SE

SE

EQ

Dummy cell Dummy cell


DRAM Read Process with Dummy CellDRAM Read Process with Dummy Cell3

2

1

00 1 2 3

V

BL

BL

t (ns)

reading 03

2

1

00 1 2 3

V

SE

EQ WL

t (ns)

control signals

3

2

1

00 1 2 3

V

BL

BL

t (ns)

reading 1


Voltage RegulatorVoltage Regulator

-

+

VDD

VREF

Vbias

Mdrive

VDL

Mdrive

VDL

VREF

Equivalent Model


Charge PumpCharge Pump

CLK

VDD

A BM1

M2Vload

Cload

Cpump

2VDD 2 VT

VDD 2 VT

0 V

VB

Vload

0 V


DRAM TimingDRAM Timing


RDRAM ArchitectureRDRAM Architecture

memoryarray

m u x / d e m u x

n e t w o r k

Databus

Clocks

Column

Rowdemux packet dec.

packet dec.

Bus

k k3 l

demux


Address Transition DetectionAddress Transition Detection

DELAYtdA0

DELAYtdA1

DELAYtdAN2 1

VDD

ATD ATD

…


Reliability and YieldReliability and Yield


Sensing Parameters in DRAMSensing Parameters in DRAM

From [Itoh01]

4K

10

100

1000

64K 1M 16M 256M 4G 64GMemory Capacity (bits /chip)

C

D

,

Q

S

,

C

S

,

V

D D

,

V

s m a x

CD(1F)

CS(1F)

Q S(1C)

V smax (mv)

VDD (V)Q S 5 CS V DD /2V smax 5 Q S / (CS 1 CD)


Noise Sources in 1T Noise Sources in 1T DRamDRam

Ccross

electrode

a-particles

leakage CS

WL

BL substrate Adjacent BLCWBL


Open BitOpen Bit--line Architecture line Architecture ——Cross CouplingCross Coupling

SenseAmplifierC

WL 1

BL

CBL

CWBL CWBL

CC

WL 0

CCBL

C C

WL D WL D WL 0 WL 1

BL

EQ


FoldedFolded--BitlineBitline ArchitectureArchitecture

SenseAmplifier

C

WL 1

CWBL

CWBL

C

WL 0 WL 0 WL D

CC

WL 1

CC

WL D

BL CBL

BL CBL

EQ

x

x

y

y

…


TransposedTransposed--BitlineBitline ArchitectureArchitecture

SA

Ccross

(a) Straightforward bit-line routing

(b) Transposed bit-line architecture

BL 9

BLBL

BL 99

SA

CcrossBL 9

BLBL

BL 99


AlphaAlpha--particles (or Neutrons)particles (or Neutrons)

1 Particle ~ 1 Million Carriers

WL

BL

V DD

n1

a-particle

SiO 21

11

11

12

22

22

2


YieldYield

Yield curves at different stages of process maturity(from [Veendrick92])


RedundancyRedundancy

MemoryArray

R o w D e c o d e r

Redundantrows

Redundantcolumns

RowAddress

Column Decoder ColumnAddress

FuseBank:


ErrorError--Correcting CodesCorrecting CodesExample: Hamming Codes

with

e.g. B3 Wrong

1

1

0

= 3


Redundancy and Error CorrectionRedundancy and Error Correction


Sources of Power Dissipation in Sources of Power Dissipation in MemoriesMemories

PERIPHERY

ROWDEC

selected

non-selected

CHIP

COLUMN DEC

nC DE VINT f

mC DE VINT f

CPTVINT f

IDCP

ARRAY

m

n

m(n 2 1)ihld

miact

VDD

VSS

IDD 5 SCiDVif1S IDCP

From [Itoh00]


Data Retention in SRAMData Retention in SRAM

( A )

1.30u

1.10u

900n

700n

500n

300n

100n

0.00 .600 1.20 1.80

Factor 7

0.13 m CMOSm

0.18 m CMOSm

VDD

I leak

age

SRAM leakage increases with technology scaling


Suppressing Leakage in SRAMSuppressing Leakage in SRAM

SRAMcell

SRAMcell

SRAMcell

VDD,int

VSS,int

VDDVDD VDDL

sleep

sleep

SRAMcell

SRAMcell

SRAMcell

VDD,int

sleep

low-threshold transistor

Reducing the supply voltageReducing the supply voltageInserting Extra ResistanceInserting Extra Resistance


Data Retention in DRAMData Retention in DRAM101

100

102 1

102 2

102 3

102 4

102 5

102 6

15M 64M 255M 1G 4G 15G 64G

Capacity (bit)

Cur

rent

(A)

3.3 2.5 2.0 1.5 1.2 1.0 0.8Operating voltage (V)

0.53 0.40 0.32 0.24 0.19 0.16 0.13

Extrapolated threshold voltage at 25 C (V)

I ACT

IAC

IDC

Cycle time : 150 nsT 5 75 C,S5 97 mV/dec.

From [Itoh00]


Case StudiesCase Studies

Programmable Logic ArraySRAM Flash Memory


PLA versus ROMPLA versus ROMProgrammable Logic Arraystructured approach to random logic“two level logic implementation”

NOR-NOR (product of sums)NAND-NAND (sum of products)

IDENTICAL TO ROM!

Main differenceROM: fully populatedPLA: one element per minterm

Note: Importance of PLA’s has drastically reduced1. slow2. better software techniques (mutli-level logic

synthesis)But …


Programmable Logic ArrayProgrammable Logic Array

GND GND GND GND

GND

GND

GND

V DD

V DD

X 0X 0 X 1 f0 f1X 1 X 2X 2

AND-plane OR-plane

Pseudo-NMOS PLA


Dynamic PLADynamic PLAGND

GNDVDD

VDD

X 0X 0 X 1 f0 f1X 1 X 2X 2

ANDf

ANDf

ORf

ORf

AND-plane OR-plane


Clock Signal Generation Clock Signal Generation for selffor self--timed dynamic PLAtimed dynamic PLA

f

tpre teval

f AND

f

f AND

f AND

f OR

f OR

(a) Clock signals (b) Timing generation circuitry

Dummy AND row

Dummy AND row


PLA LayoutPLA LayoutVDD GNDφ

And-Plane Or-Plane

f0 f1x0 x0 x1 x1 x2 x2Pull-up devices Pull-up devices


4 4 MbitMbit SRAMSRAMHierarchical WordHierarchical Word--line Architectureline Architecture

Global word line

Sub-global word line

Block groupselect

Blockselect

Blockselect

Memory cell

Localword line

Block 0

•••

Localword line

Block 1

•••

Block 2...

•••


BitBit--line Circuitryline CircuitryBit-lineload

Blockselect ATD

BEQ

Local WL

Memory cell

I/O lineI/O

B /T

CD

Sense amplifier

CD CD

I/O

B /T


Sense Amplifier (and Waveforms)Sense Amplifier (and Waveforms)

BS

I /O I /O

DATA

Blockselect ATD

BSSA SA

BS

SEQ

SEQ

SEQ

SEQSEQ

Dei

I/O Lines

Address

Data-cut

ATD

BEQ

SEQ

DATA

Vdd

GND

SA, SAVdd

GND


1 1 GbitGbit Flash MemoryFlash Memory

Sense Latches(10241 32) 3 8

Data Caches(10241 32) 3 8

Sense Latches(10241 32) 3 8

Data Caches(10241 32) 3 8

Wor

d Li

ne D

river

Wor

d Li

ne D

river

Wor

d Li

ne D

river

Wor

d Li

ne D

river

512Mb Memory Array 512Mb Memory ArrayBL0 BL1 ····· BL16895 BL16996 BL16897··· BL33791

SGDWL31

WL0SGS

Block0

BLT0Block1023

Block0

Block1023

Bit Line Control CircuitBLT1

I/O I/O

From [Nakamura02]


Writing Flash MemoryWriting Flash MemoryN

umbe

r of m

emor

y ce

lls

0V 1V 2VVt of memory cells

Verify level 5 0.8 V Word-line level 5 4.5 V

3V 4V

Result of 4 timesprogram

R e a d l e v e l ( 4 . 5 V )

N u m b e r o f c e l l s

1000V 1V 2V

Vt of memory cells

3V 4V

102

104

106

108

Evolution of thresholds Final Distribution

From [Nakamura02]


125125mmmm22 1Gbit NAND Flash Memory1Gbit NAND Flash Memory

10.7

mm

11.7mm

2kB

Pag

e bu

ffer &

cac

heC

harg

e pu

mp

16896 bit lines

32 word lines x 1024 blocks

From [Nakamura02]


125125mmmm22 1Gbit NAND Flash Memory1Gbit NAND Flash MemoryTechnology 0.13μm p-sub CMOS triple-well

1poly, 1polycide, 1W, 2AlCell size 0.077μm2Chip size 125.2mm2Organization 2112 x 8b x 64 page x 1k blockPower supply 2.7V-3.6VCycle time 50nsRead time 25μsProgram time 200μs / pageErase time 2ms / block

Technology 0.13μm p-sub CMOS triple-well1poly, 1polycide, 1W, 2Al

Cell size 0.077μm2Chip size 125.2mm2Organization 2112 x 8b x 64 page x 1k blockPower supply 2.7V-3.6VCycle time 50nsRead time 25μsProgram time 200μs / pageErase time 2ms / block

From [Nakamura02]


Semiconductor Memory TrendsSemiconductor Memory Trends(up to the 90(up to the 90’’s)s)

Memory Size as a function of time: x 4 every three years


Semiconductor Memory TrendsSemiconductor Memory Trends(updated)(updated)

From [Itoh01]


Trends in Memory Cell AreaTrends in Memory Cell Area

From [Itoh01]


Semiconductor Memory TrendsSemiconductor Memory Trends

Technology feature size for different SRAM generations

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Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic · PDF file · 2015-08-11Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic December 20, ... M bits Storage cell M bits S 0 S