inst.eecs.berkeley.edu/~ee241b

Borivoje Nikoli

EE241B : Advanced Digital Circuits

Lecture 10 – Latch Timing

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1EECS241B L10 LATCH TIMING

Announcements

• Response to project abstracts today, by e-mail• Team web pages

• Be careful not to leak proprietary info (interface tools via Hammer)

• Quiz 1 today

• Reading

• Chapter 11 (Partovi) in Chandrakasan, Fox, Bowhill

2EECS241B L10 LATCH TIMING

Outline

• Module 3• Flip-flop timing

• Latch-based timing

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3. Design for Performance

3.A Flip-Flop Timing

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Clock Uncertainties

2

43

Power Supply

Interconnect

5 Temperature

6 Capacitive Load

7 Coupling to Adjacent Lines

1 Clock Generation

Devices

Sources of clock uncertainty

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Clock Constraints in Edge-Triggered Systems

Courtesy of IEEE Press, New York. 2000EECS241B L10 LATCH TIMING 6

3.B Timing with Uncertainty/Variations

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Pictorial View of Setup and Hold Tests

0 or moreswitching(s)allowed

Latest clock arrival time Earliest clock arrival time(next cycle)

Data must be stable

Hold time

Early RAT

Data must be stable

Setup time

Late RAT

Actual early AT Actual late AT

Earlyslack

Lateslack

ICCAD '07 Tutorial Chandu VisweswariahEECS241B L10 LATCH TIMING 8

LF CF

Hold test

Handling of Across-Chip Variation

• Each gate has a range of delay: [lb, ub]• The lower bound is used for early timing• The upper bound is used for late timing

• This is called an early/late split

• Static timing obtains bounds on timing slacks• Timing is performed as one forward pass and one backward pass

LF CF

Setup test

Capturing early path

Launching late path

Capturing late path

Launching early path

ICCAD '07 Tutorial Chandu VisweswariahEECS241B L10 LATCH TIMING 9

How is the Early/Late Split Computed?

• The best way is to take known effects into account during characterization of library cells• History effect, simultaneous switching, pre-charging of internal nodes, etc.• This drives separate characterization for early and late; this is the most accurate method

• Failing that, the most common method is derating factors• Example: Late delay = library delay * 1.05

Early delay = library delay * 0.95• The IBM way of achieving derating is LCD factors (Linear Combination of Delay) (FC=fast

chip, SC=slow chip, see next page)• Late delay = L * FC_delay + L * NOM_delay + L * SC_delay

Early delay = E * FC_delay + E * NOM_delay + E * SC_delay• Across-chip variation is therefore assumed to be a fixed proportion of chip-to-chip

variation for each cell type

ICCAD '07 Tutorial Chandu VisweswariahEECS241B L10 LATCH TIMING 10

IBM Delay Modeling*

Intrinsic:Chip means

SystematicACV

RandomACV

Early Late Early Late

*P. S. Zuchowski, ICCAD’04

At a given cornerlate delay = intrinsic + systematic + randomearly delay = intrinsic – systematic – random

ICCAD '07 Tutorial Chandu VisweswariahEECS241B L10 LATCH TIMING 11

Traditional Timing Corners

Fast

chi

p ea

rly

Fast

chi

p la

te

Intra-chip variation

Slow

chi

p ea

rly

Slow

chi

p la

te

Intra-chip variation

Chip-to-chip variation

Fast chip Slow chip

ICCAD '07 Tutorial Chandu VisweswariahEECS241B L10 LATCH TIMING 12

The Problem with an Early/Late Split

• The early/late split is very useful• Allows bounds during delay modeling• Any unknown or hard-to-model effect can be swept under the rug of an

early/late split• But, it has problems

• Additional pessimism (which may be desirable)• Unnecessary pessimism (which is never desirable)

LF CF

Setup test

Capturing early path

Launching late path

This physically commonportion can’t be both fastand slow at the same time

ICCAD '07 Tutorial Chandu VisweswariahEECS241B L10 LATCH TIMING 13

How to Have Less Pessimism?

• Common path pessimism removal

• Account for correlations

• Credit for statistical averaging of random

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Statistical Timing

• Deterministic

• Statistical

a

b

c++ MAX

b

a

c++ MAX

ICCAD '07 Tutorial Chandu VisweswariahEECS241B L10 LATCH TIMING 15

Statistical Max Operation

*C. E. Clark, “The greatest of a finite set of random variables,” OR Journal, March-April 1961, pp. 145—162**M. Cain, “The moment-generating function of the minimum of bivariate normal random variables,” American Statistician, May ’94, 48(2)

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Unified View of Correlations

Independentlyrandom part

Spatially correlated part:within-chip distance-related correlation

Globally correlated part: chip-to-chip, wafer-to-wafer, batch-to-batch variation

1

0 Distance

Correlation Coefficient

Rrii XaXaaD 0

ICCAD '07 Tutorial Chandu VisweswariahEECS241B L10 LATCH TIMING 17

Spatial Correlation vs. Early/Late Split

LF1 LF2 CFLF3

early clock

0

1

2

3

4 6

7

8

9

10

5 11

12

13

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15

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17 19

20

21

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18 24

25

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30 32

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44 50

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56 58

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70 76

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7879

8081

82 84

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90

Dependence on common virtual variables cancels out at the timing testICCAD '07 Tutorial Chandu VisweswariahEECS241B L10 LATCH TIMING 18

3.C Latch Timing

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Key Point

• Latch-based sequencing can improve performance, but is more complicated

• Timing analysis not limited to a consecutive pair of latches

EECS241B L10 LATCH TIMING 20

Latch Timing

D

Clk

Q

tDQ

tCQ

When data arrives to transparent latch

When data arrives to non-transparent latch

Data has to be ‘re-launched’

Latch is a ‘soft’ barrier

EECS241B L10 LATCH TIMING 21

Latch Sequencing

D

Clk

Q D

Clk

Q

D

Clk

Q

Clk1 Clk2

D

Clk

Q D

Clk

Q

Logic

Logic Logic

Clk1

Clk Clk

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Preventing Late Arrivals

EECS241B L10 LATCH TIMING 23

D

Clk

Q D

Clk

QLogic

Clk Clk

Clk

tCY PW

TSU Late RAT

Clk

TCQ TLM

TSU

Clk

TDQ TLM

TSUPW

TSU

Early RAT

Data can launch during transparency

Preventing Premature Arrivals

• Data should not be able to race through during transparency

ClkTHPW

TCQ TLm

EECS241B L10 LATCH TIMING 24

Two-Phase Latch-Based Design

• Two-phase non-overlapping is safer, but adds margin

L1Latch Logic

Logic

L2Latch

Clk

L1 latch is transparentwhen Clk = 1

L2 latch is transparent when Clk = 0

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Latch-Based Timing

• Single-phase, two-latch

As long as transitions are within the assertion period of the latch,no impact of position of clock edges

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Latch Design and Hold Times

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Soft-Edge Properties of Latches• Slack passing – logical partition uses left over time (slack) from the

previous partition• Time borrowing – logical partition utilizes a portion of time allotted to

the next partition• Makes most impact in unbalanced pipelines

Bernstein et al, Chapter 8, Chandrakasan, Chap 11 (by Partovi)

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Slack Passing and Time Borrowing

EECS241B L10 LATCH TIMING 29

D

Clk

Q D

Clk

QLogic

Clk Clk

ClktCY/2

tlogic

D

Clk

Q

Clk

Logic

tCY/2

tDQtlogictDQ

Slack Passing and Time Borrowing

• Slack passed

EECS241B L10 LATCH TIMING 30

D

Clk

Q D

Clk

QLogic

Clk Clk

ClktCY/2

tlogic

D

Clk

Q

Clk

Logic

tCY/2

tDQtlogictDQ

slack

Slack Passing and Time Borrowing

EECS241B L10 LATCH TIMING 31

D

Clk

Q D

Clk

QLogic

Clk Clk

ClktCY/2

tlogic

D

Clk

Q

Clk

Logic

tCY/2

tDQtlogictDQ

• Time borrowed

Slack-Passing and Cycle Borrowing

For N stage pipeline, overall logic delay should be < N TclEECS241B L10 LATCH TIMING 32

Next Lecture

• Flip-flops

EECS241B L10 LATCH TIMING 33