Intellectual Property Key...

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Intellectual PropertyKey Ingredients…..

W. Tonti IEEE Sr. DirectorIEEE Future Directionsw.r.tonti@ieee.org

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Issue Date: 8/25/1998

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The Process of Inventing: New Space, Base Tech – Think Tank

Write Specification, Independent and Dependent claims, FILE

Literature and Patent Expert Search, Prior Art Review

Simulate, Fabricate, Measure and Test

Develop Prime EmbodimentDescribe Best Mode: Structure and or Method

ResearchFormulate potential solution space

Greenfield Form a team of like minded researchers

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The Process of Inventing: Solving a Problem, Cross Functional Team

Write Specification, Independent and Dependent claims, FILE

Literature and Patent Expert Search, Prior Art Review

Simulate, Fabricate, Measure and Test

Develop Prime EmbodimentDescribe Best Mode: Structure and or Method

Define the “Real” Problem: The CruxFormulate solution space

Problem StatementForm a Cross Functional Solutions Team

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The Patent Process

v Solution of an existing problem

vIdentifying elements for a future roadmap

v Leverage your strengths

v Form a team

v Everyone is a contributor, no idea is bad

v Write it down…… • For me ideas come at night. Have a pad nearby.• A picture really is worth 1000 words

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Where do you search for Prior Art ?

vTwo main sources of IP

§ IEEE Xplore

§ US patent database

vWhy bother searching?§ It is required.

§ Your claims will be modified based on what you uncover.

§ More often than not prior art will sharpen your own submission.

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Transistor

Four Terminal Switch, A Field Effect DeviceMinority Carrier Current flows from (Source to Drain) Requires a potential to invert the surface (Gate)Common Substrate Connection

Fundamental design criterion: Built in potential fB=[kT/q] Ln(N/Ns)

A Transistor switches from the off to on state at ~2 fB

S D

G

Sx

Bias ConfigurationS= GndSx= GndD=High(+)G= Swept, Gnd to D

Layout

log(Ids)

Vgs

Off

On

2 fB

VDS=HVGS=H

VDS=HVGS=Gnd

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INSIGHT:

v Designer starts with a simple library element, ie a MOSFET:

v This is translated into shapes using a layout tool

v Cross section of what process is trying to deliver

A A’

B’

S D

B S

D

SS

GD

A A’ B B’

vThe Problem: B-B’

G

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Physical Evidence: Measured Data - Same Wafer

vMOS Characteristic of devicespecifically designed without a corner

vMOS Characteristic standard device design

(Note, this is NOT a solution!)This design is an annular device ring. Large, leaky, not optimized…

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Ids

Vgs

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Can you Publish ?

File Date: 9/16/1997Issue Date: 8/25/1998

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Acknowledgements

v I would like to acknowledge my co inventor and long time friend Dr. Jack Mandelman who has prepared many of the visuals contained in this package.

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IP_Tut1

Questions ?? Ask The….

William Tontiw.r.tonti@ieee.org‘802 238 5401