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Copyright © Altera Corporation
Designing with Nios II and SOPC BuilderDesigning with Nios II and SOPC Builder
2Copyright © 2005 Altera Corporation
� Intellectual Property (IP)− Signal Processing
− Communications− Embedded Processors
� Nios®, Nios II
� Devices (continued)− Mercury™ Devices
− ACEX® Devices
− FLEX® Devices− MAX® Devices
� Tools− Quartus® II Software− Quartus II Web Edition
− SOPC Builder
− DSP Builder− Nios II IDE
� Devices− Stratix II™
− Stratix
− Stratix GX
− Cyclone II™
− Cyclone
− MAX® II
The Programmable Solutions Company ®The Programmable Solutions Company ®
Copyright © Altera Corporation
Nios II Hardware DevelopmentNios II Hardware Development
4Copyright © 2005 Altera Corporation
What is Nios II ?What is Nios II ?
� Altera’s Second Generation Soft-Core 32 Bit RISC Microprocessor− Developed Internally By Altera− Harvard Architecture− Royalty-Free
FPGA
- Nios II Plus All Peripherals Written In HDL- Can Be Targeted For All Altera FPGAs- Synthesis Using Quartus II Integrated Synthesis
Ava
lon
Sw
itch
Fab
ric
UART
GPIO
Timer
SPI
SDRAMController
On-ChipROM
On-ChipRAM
Nios IICPUDebug C
ache
5Copyright © 2005 Altera Corporation
Problem : Reduce Cost, Complexity & PowerProblem : Reduce Cost, Complexity & Power
Flash
SDRAM
CPU
DSP
I/O
I/O
I/O FPGA
I/O I/O I/O
CPU DSP
Solution: Replace External Devices with Programmable Logic
FPGA
6Copyright © 2005 Altera Corporation
Problem : Reduce Cost, Complexity & PowerProblem : Reduce Cost, Complexity & Power
Flash
SDRAM
Solution: Replace External Devices with Programmable Logic
CPU is a Critical Control Function Required for System-Level Integration
System On A Programmable Chip (SOPC)System On A Programmable Chip (SOPC)
FPGA
7Copyright © 2005 Altera Corporation
Synthesis- Translate Design into Device Specific Primitives- Optimization to Meet Required Area & Performance Constraints- Spectrum, Synplify, Quartus II
Design Specification
Place & Route- Map Primitives to Specific Locations Inside
Target Technology with Reference to Area &Performance Constraints
- Specify Routing Resources to Be Used
Design Entry/RTL Coding- Behavioral or Structural Description of Design
RTL Simulation- Functional Simulation (Modelsim,
Quartus II)- Verify Logic Model & Data Flow
(No Timing Delays)
LE M512
M4K I/O
FPGA Hardware Design FlowFPGA Hardware Design Flow
SOPC BuilderSOPC Builder
Functional Simulation (Modelsim, Quartus II)Verify Logic Model & Data Flow (No Timing Delays)
8Copyright © 2005 Altera Corporation
Timing Analysis- Verify Performance Specifications Were Met- Static Timing Analysis
Gate Level Simulation- Timing Simulation- Verify Design Will Work in Target Technology
tclk
FPGA Hardware Design FlowFPGA Hardware Design Flow
Test FPGA on PC Board- Program & Test Device on Board- Use SignalTap II for Debugging
9Copyright © 2005 Altera Corporation
Development Kits, Stratix & Cyclone EditionDevelopment Kits, Stratix & Cyclone Edition
8 MB Flash
Configuration Controller (MAX 7128AE)
10/100 Ethernet MAC/PHY & RJ-45 Connector
Compact Flash(Connector Mounted on Back)
16 MB SDRAM
Power Connector
Download /JTAG Debug Connector
Serial RS-232 Connectors
1MB SRAM
Buttons LEDs 7 Segment
Expansion Prototype Connectors(40 I/O pins each)
Configuration Control
CPU Reset
10Copyright © 2005 Altera Corporation
32-BitNios II
ProcessorROM
(with Monitor)
On-Chip Off-Chip
Address (32)
Read
Write
Data In (32)
Data Out (32)
IRQ
IRQ #(6)
Avalon S
witch F
abric
Nios II Processor
Standard Design Block DiagramStandard Design Block Diagram
Tri-StateBridge
Leve
l Shi
fter
16MB Compact FLASH
SDRAMController
8MB FLASH
1MB SRAM
Ethernet MAC/PHY
32MB SDRAM
Tri-StateBridge
Compact Flash PIOs
Button PIO7-SegmentLED PIO
LCD PIOLED PIO
General Purpose
Timer
Periodic Timer
UART
8 LEDsExpansion
Header J12
2 Digit Display
4 Momentary
buttons
ReconfigPIO
11Copyright © 2005 Altera Corporation
User-DefinedInterface
MemoryInterface
On-ChipDebug Core
Off-ChipSoftware Trace
Memory
UART n
Timer n
SPI n
GPIO n
DMA n
Avalon Switch Fabric
Instr.
Data
AddressDecoder
InterruptController
Wait StateGeneration
Data inMultiplexer
DynamicBus Sizing
AvalonMaster/SlavePort
Interfaces
MasterArbitration
Nios II System ArchitectureNios II System ArchitectureUART 0
Timer 0
SPI 0
GPIO 0
DMA 0
MemoryInterface
User-DefinedInterface
Nios IICPU
12Copyright © 2005 Altera Corporation
Nios II Block DiagramNios II Block Diagram
ProgramController
&Address
Generation Instruction
Cache
clock
reset
irq[31..0]
ControlRegistersctl0 to ctl4
ArithmeticLogic Unit
Hardware-Assisted
Debug Module
InterruptController
JTAG interfaceto Software
Debugger
Custom Instruction
Logic
ExceptionController
InstructionMasterPort
DataCache
DataMasterPort
GeneralPurpose
Registersr0 to r31
CustomI/O Signals
Nios II Processor Core
13Copyright © 2005 Altera Corporation
Nios II Processor ArchitectureNios II Processor Architecture
�Classic Pipelined RISC Machine− 32 General Purpose Registers− 3 Instruction Formats − 32-Bit Instructions− 32-Bit Data Path− Flat Register File− Separate Instruction and Data Cache (configurable sizes)− Branch Prediction− 32 Prioritized Interrupts− Custom Instructions− JTAG-Based Hardware Debug Unit
14Copyright © 2005 Altera Corporation
Nios II VersionsNios II Versions
�Nios II Processor Comes In Three ISA Compatible Versions
�Software− Code is Binary Compatible
� No Changes Required When CPU is Changed
− FAST: Optimized for Speed
− STANDARD : Balanced for Speed and Size
− ECONOMY: Optimized for Size
15Copyright © 2005 Altera Corporation
Binary Compatibility / Flexible PerformanceBinary Compatibility / Flexible Performance
600 – 7001200 – 14001400 - 1800Logic Usage (Logic Elements)
NoneNoneConfigurableData Cache
CustomInstructions
Instruction Cache
Branch Prediction
H/W Multiplier & Barrel Shifter
Pipeline
NoneConfigurableConfigurable
Up to 256
Dynamic
1 Cycle
6 Stage
Nios II /fFast
NoneStatic
EmulatedIn Software3 Cycle
None5 Stage
Nios II /eEconomy
Nios II /sStandard
16Copyright © 2005 Altera Corporation
Hardware Multiplier AccelerationHardware Multiplier Acceleration� Nios II Economy version - No Multiply Hardware
− Uses GNUPro Math Library to Implement Multiplier
� Nios II Standard - Full Hardware Multiplier− 32 x 32 � 32 in 3 Clock Cycles if DSP block present, else uses software
only multiplier
� Nios II Fast - Full Hardware Multiplier− 32 x 32 � 32 in 1 Clock Cycles if DSP block present, else uses software
only multiplier
3StandardMUL in Stratix
1FastMUL in Stratix
250None
Clock Cycles(32 x 32 � 32)
AccelerationHardware
17Copyright © 2005 Altera Corporation
Variation with FPGA DeviceVariation with FPGA Device
0
50
100
150
200
250
0 500 1000 1500 2000Logic Elements
DM
IPS
Stratix II Stratix Cyclone HC-Stratix
Fast
Economy
Standard
18Copyright © 2005 Altera Corporation
Nios II: Hard NumbersNios II: Hard Numbers
Nios II/f Nios II/s Nios II/e
Stratix II 200 DMIPS @ 175MHz1180 LEs1 of 8 DSP4K Icache, 2K DcacheStratix 2S10-C5
90 DMIPS @ 175MHz800 LEs
4K Icache, No DcacheStratix 2S10-C5
28 DMIPS @ 190MHz400 LEs
No Icache, No DcacheStratix 2S10-C5
Stratix 150 DMIPS @ 135MHz1800 LEs1 of 8 DSP4K Icache, 2K DcacheStratix 1S10-C5
67 DMIPS @ 135MHz1200 LEs
4K Icache, No DcacheStratix 1S10-C5
22 DMIPS @ 150MHz550 LEs
No Icache, No DcacheStratix 1S10-C5
Cyclone 100 DMIPS @ 125MHz1800 LEs
4K Icache, 1K DcacheCyclone 1C4-C6
62 DMIPS @ 125MHz1200 LEs
2K Icache, No DcacheCyclone 1C4-C6
20 DMIPS @ 140MHz550 LEs
No Icache, No DcacheCyclone 1C4-C6
* FMax Numbers Based Reference Design Running From On-Chip Memory (Nios II/f ≅1.15 DMIPS / MHz)
19Copyright © 2005 Altera Corporation
SOPC BuilderSOPC Builder
� Altera, Partner & User Cores
− Processors− Memory Interfaces− Peripherals− Bridges− Hardware Accelerators− Import User Logic
(ie. custom peripherals)
� Web-Based IP Deployment
Over 60 Cores Available
Today
– System Contents Page
20Copyright © 2005 Altera Corporation
� Hardware designer selects which Nios II version to use when creating system
Nios II CPU Configured in SOPC BuilderNios II CPU Configured in SOPC Builder
21Copyright © 2005 Altera Corporation
Selecting JTAG Debug CoreSelecting JTAG Debug Core
� Configuration is chosen when hardware designer selects appropriate Nios II processor core
22Copyright © 2005 Altera Corporation
SOPC BuilderSOPC Builder – More “cpu” Settings Page
23Copyright © 2005 Altera Corporation
SOPC Builder – System Generation PageSOPC Builder – System Generation Page
24Copyright © 2005 Altera Corporation
SOPC Builder Produces a .PTF FileSOPC Builder Produces a .PTF File
� Text file that records SOPC Builder edits� Describes Nios II System
� Used by software development tools
25Copyright © 2005 Altera Corporation
Integrate SOPC Builder O/P in Quartus IIIntegrate SOPC Builder O/P in Quartus II
� Integrate SOPC Builder block symbol to Quartus II schematic (as shown below) and compile design
� Or, instantiate top module into your HDL design and compile
26Copyright © 2005 Altera Corporation
� Memory Interfaces− EPCS Serial Flash
Controller− On-Chip
� RAM, ROM
− Off-Chip� SRAM
� CFI Flash
� LCD Display
New Peripherals for Nios II New Peripherals for Nios II
� System ID Peripheral− Used to Ensure Hardware/
Software Version Synchronization− Simple 2 read-only register
peripheral containing hardware ID tags.� Register 1 contains random
number
� Register 2 contains time and date when system was generated in SOPC Builder
− Can be checked at runtime to ensure that the software to be downloaded matches the hardware image
27Copyright © 2005 Altera Corporation
� JTAG UART− Single JTAG
Connection For:� Device Configuration
� Flash Programming
� Code Download � Debug
� Target STDIO (printing)
New Peripherals for Nios II New Peripherals for Nios II
� Compact Flash Interface− Mass Storage Support
� True IDE Mode
� Compact Flash Mode
− Software Supports� Low-Level API
� MicroC/OS-II File System Support
� µCLinux File System Support
Supported through www.niosforum.com
28Copyright © 2005 Altera Corporation
Project DirectoriesProject Directories
� Hardware− HDL Source & Netlist− db - Quartus project
database
� Software− Application source code− Library files
� Simulation− Testbench− Automatically generated
test memory and vectors
Copyright © Altera Corporation
Nios II Software DevelopmentNios II Software Development
30Copyright © 2005 Altera Corporation
SOPC Builder FlowSOPC Builder FlowSOPC Builder GUI
Connect Blocks
Processor Library Custom Instructions
Peripheral Library Select & Configure Peripherals, IP
IP Modules
Configure Processor
� C Header files
� Custom Library
� Peripheral Drivers
Compiler, Linker, Debugger
Software Development
� User Code
� Libraries
� RTOS
GNU Tools
Generate
� HDL Source Files
� Testbench
Synthesis &Fitter
� User Design
� Other IP Blocks
Hardware Development
Quartus II
On-ChipDebug
Software TraceHard Breakpoints
SignalTap ® II
AlteraPLD
JTAG,Serial, orEthernet
ExecutableCode
HardwareConfiguration
File Verification& Debug
NiosNios II IDEII IDE
31Copyright © 2005 Altera Corporation
Nios II IDE (Integrated Development Environment)*Nios II IDE (Integrated Development Environment)*
� Leading Edge Software Development Tool
� Target Connections− Hardware (JTAG)− Instruction Set Simulator− ModelSim®-Altera Software
� Advanced Hardware Debug Features− Software and Hardware
Break Points, Data Triggers, Trace
� Flash Memory Programming Support
* Based on Eclipse Project
32Copyright © 2005 Altera Corporation
Opening the Nios II IDEOpening the Nios II IDE
Launch the Launch the NiosNios II IDE from II IDE from the SOPC Builder or from the SOPC Builder or from the Windows Start menuthe Windows Start menu
33Copyright © 2005 Altera Corporation
Nios II IDENios II IDE
List of Open Projects
Terminal window
File Viewer Window
(for C code, C++, and assembly*)
•Note: C++ files must have extension .cppIn-line assembly code offset by asm();
34Copyright © 2005 Altera Corporation
Nios II IDE C/C++ Projects/NavigatorNios II IDE C/C++ Projects/Navigator
� Lists all open projects
� Displays source files associated with project
� List all open and closed projects
� Allows you to drag and drop new files into existing projects
35Copyright © 2005 Altera Corporation
Creating a C/C++ ApplicationCreating a C/C++ ApplicationFile > New > Project
36Copyright © 2005 Altera Corporation
Creating a C/C++ ApplicationCreating a C/C++ Application
Link to a System Library- Select a pre-existing library- Or create a new library
37Copyright © 2005 Altera Corporation
This Creates Two Software Projects- Application and System Library ProjectThis Creates Two Software Projects- Application and System Library Project
System Library Project- contains system
header file, etc.
Application Project- contains application source code
Drivers Directory- contains all device drivers – DO NOT DELETE !
38Copyright © 2005 Altera Corporation
Application and System Library ProjectsApplication and System Library Projects
� Application Projects build executables
� System Library Projects contain interface to the hardware− Nios II device drivers (Hardware Abstraction
Layer)− Optional RTOS (MicroC/OS-II)− Optional software components (Lightweight
TCP/IP stack, Read Only Zip File System)
39Copyright © 2005 Altera Corporation
System Library OptionsSystem Library OptionsSelect RTOSSpecify stdio devicesPartition the memory map
40Copyright © 2005 Altera Corporation
Software CompilationSoftware Compilation
� To compile a software application, highlight your project and select Build Project from the Projects menu
41Copyright © 2005 Altera Corporation
Directory Structure After CompilationDirectory Structure After Compilation
� Application Project � System Library Project
42Copyright © 2005 Altera Corporation
Hardware Abstraction LayerHardware Abstraction Layer
� A lightweight runtime environment for Nios II software− Provides a level of abstraction between application code and
low level hardware
� HAL libraries are generated by Nios II IDE� A HAL contains:
− device drivers− initialization software− file system− stdio, stderr
43Copyright © 2005 Altera Corporation
Hardware Abstraction LayerHardware Abstraction Layer
� Provides generic device models for classes of peripherals common in embedded systems− eg. timers, I/O peripherals, etc.
� Gives a consistent POSIX-like API, regardless of underlying hardware
� Make programming as familiar as possible to software engineers who may not be familiar with the specific peripheral architectures
� ANSI C (through the Newlib library)� UNIX style interface (i.e. POSIX like)� Altera extensions where standards don’t exist or were
inappropriate (watch for the alt_* extension)
44Copyright © 2005 Altera Corporation
Nios II Processor System Hardware
DeviceDriver
DeviceDriver
DeviceDriver…
Nios II HAL: Runtime LibraryNios II HAL: Runtime Library
_exit()close()closedir()fstat()getpid()gettimeofday()ioctl()isatty()kill()lseek()
open()opendirread()readdir()rewinddir()sbrk()settimeofday()stat()usleep()wait()write()
HAL API
HAL API
C Standard LibraryC Standard Library
User Program
The HAL ‘UNIX Style’ Functions are the glue between the C library and the device drivers
45Copyright © 2005 Altera Corporation
HAL File SystemHAL File System
/
/dev /mnt
/dev/jtag_uart0 /dev/lcd0 /mnt/rozipfs
/mnt/rozipfs/myfile1
/mnt/rozips/myfile21• Device names match those set in SOPC builder.• Can only access nodes, not directories.• All paths must be absolute (no current directory)
46Copyright © 2005 Altera Corporation
Familiar File/Device AccessFamiliar File/Device Access
� ANSI C:fp = fopen (“/dev/lcd0”, “w”); fprintf (fp, “%s”, m sg);
� UNIX Style:fd = open (“/dev/lcd0”, O_WRONLY); write (fd, msg, strlen(msg));
� Newlib also supports C++ streams:ofstream ofp(“/dev/lcd0”, ios::out); ofp << msg;
� Existing code (outside the Nios world) uses these interfaces. Porting is now much easier.
� Use of existing standards means there’s nothing new to learn.
47Copyright © 2005 Altera Corporation
HAL System Header FileHAL System Header File
system.hsystem.h
SOPCSOPC Builder System ContentsBuilder System Contents
System Library SettingsSystem Library Settings
48Copyright © 2005 Altera Corporation
system.hsystem.h
� Contains macro definitions for system parameters, including peripheral configuration, for instance: − Hardware configuration of the peripheral− Base address− IRQ priority (if any)− Symbolic name for peripheral
� Does not include: static information, function prototypes, or device structures (unlike the old excalibur.h)
� Located in the syslib project directory� Rarely necessary to include it explicitly in your
application code, which improves rebuild time
49Copyright © 2005 Altera Corporation
system.h - examplesystem.h - example
.
.
./** button_pio configuration**/
#define BUTTON_PIO_NAME "/dev/button_pio"#define BUTTON_PIO_TYPE "altera_avalon_pio"#define BUTTON_PIO_BASE 0x00920830#define BUTTON_PIO_IRQ 2#define BUTTON_PIO_HAS_TRI 0#define BUTTON_PIO_HAS_OUT 0#define BUTTON_PIO_HAS_IN 1#define BUTTON_PIO_CAPTURE 1#define BUTTON_PIO_EDGE_TYPE "ANY"#define BUTTON_PIO_IRQ_TYPE "EDGE"#define BUTTON_PIO_FREQ 50000000
/** system configuration**/
#define ALT_SYSTEM_NAME "std_1s10ES"#define ALT_CPU_NAME "cpu"#define ALT_CPU_ARCHITECTURE "altera_nios2"#define ALT_DEVICE_FAMILY "STRATIX"#define ALTERA_NIOS_DEV_BOARD_STRATIX_1S10_ES#define ALT_STDIN "/dev/jtag_uart"#define ALT_STDOUT "/dev/jtag_uart"#define ALT_STDERR "/dev/jtag_uart"#define ALT_CPU_FREQ 50000000#define ALT_CPP_CONSTRUCTORS#define ALT_IRQ_BASE NULL
.
.
.
� Defines system settings and peripheral configurations:− Replaces excalibur.h (from Nios)
50Copyright © 2005 Altera Corporation
HAL ReferencesHAL References
� Each HAL project references library routines and drivers for thecomponents included in your Nios II system
51Copyright © 2005 Altera Corporation
Reading/Writing Hardware in Nios IIReading/Writing Hardware in Nios II
� Instead use I/O macros to access hardware− I/O macros bypass the cache for hardware accesses− They set bit 31 of address bus high (ie. control bit)
− IORD(BASE, REGNUM)� Reads value at register
REGNUM offset from base address BASE
− IOWR(BASE,REGNUM,DATA)� Writes DATA to register
REGNUM offset from base address BASE
REGNUM = 0REGNUM = 0
REGNUM = 1REGNUM = 1
REGNUM = 2REGNUM = 2
REGNUM = 3REGNUM = 3
REGNUM = 4REGNUM = 4
BASE+2BASE+2
BASEBASE
BASE+4BASE+4
52Copyright © 2005 Altera Corporation
Header Files for Nios II PeripheralsHeader Files for Nios II Peripherals
� Each Nios II peripheral has specific read/write macros for each register− Example: UART (altera_avalon_uart_regs.h)
#define IORD_ALTERA_AVALON_UART_RXDATA(base) IORD(base, 0)
#define IOWR_ALTERA_AVALON_UART_RXDATA(base, data) IOWR(base, 0, data)
#define IORD_ALTERA_AVALON_UART_TXDATA(base) IORD(base, 1)
#define IOWR_ALTERA_AVALON_UART_TXDATA(base, data) IOWR(base, 1, data)
#define IORD_ALTERA_AVALON_UART_STATUS(base) IORD(base, 2)
#define IOWR_ALTERA_AVALON_UART_STATUS(base, data) IOWR(base, 2, data)
53Copyright © 2005 Altera Corporation
InterruptsInterrupts
� HAL API for ISRs - Functions− alt_irq_register()
� Associates interrupt with your ISR function.
− alt_irq_disable_all()� Disables all IRQs
− alt_irq_enable_all()� Enables all IRQs
− alt_irq_interruptible()� Used in ISR function body. Allows ISR to be interrupted by
higher priority IRQs.
− alt_irq_non_interruptible()� Used to make ISRs uninterruptible (default behavior).
54Copyright © 2005 Altera Corporation
Nios II OS / RTOS SupportNios II OS / RTOS Support
Extensive drivers and middlewear,
inc USB, IPSec, etc.
Many, inc. FAT and
JFFS2
Incl.YesOpen Source (GPL)
µCLinux
GUI, SNMPRMON, SPAN
Opt.Opt.OSEKµITRON
YesATI/Mentor** Nucleus Plus
µC/OS-II Support
Sockets APIIP, ICMP, UDP, TCP
YesOpen Source* Lightweight IPTCP/IP Stack
KROSTechnologies
Micrium
Provider
POSIX
RTCA/DO-178B
Standards
GUIFlash
Other
Opt.
Opt.
File System
Yes
Yes
SourceCode
Opt.
Opt.
TCP/IPStack
KROS
* MicroC/OS-II
Product
* Included in Nios II Development Kits** Evaluation Version Included in Nios II Development Kits
<continued on next slide>
55Copyright © 2005 Altera Corporation
Nios II MicroC /OS-II Nios II MicroC /OS-II
� Single-seat developers license included for free with Nios II kits
� Licensing fee req’d when you productize your system� Full source code included� Preemptive operating system� Small footprint
− Code Size (min 5KB, max 20KB)− Data Space (min 1KB, max 5KB)
� Supports Semaphores, and Mailboxes for task synchronization
56Copyright © 2005 Altera Corporation
Nios II MicroC /OS-II Nios II MicroC /OS-II
Copyright © Altera Corporation
Software Run & DebugSoftware Run & Debug
58Copyright © 2005 Altera Corporation
Running Code On A TargetRunning Code On A Target
� Nios II IDE can be used to download code to target board
59Copyright © 2005 Altera Corporation
Running Code On A TargetRunning Code On A Target
� Download messages, stdout and stdin appear in console window
60Copyright © 2005 Altera Corporation
Nios II IDE Run OptionsNios II IDE Run Options
� Nios II IDE > Run > Run…
61Copyright © 2005 Altera Corporation
Nios II IDE JTAG DebuggerNios II IDE JTAG Debugger
� Requirements− Must have JTAG
Debug Core enabled in CPU
62Copyright © 2005 Altera Corporation
Nios II IDE Debug PerspectiveNios II IDE Debug Perspective
DoubleDouble--click to click to add breakpointsadd breakpoints
Basic Debug
• Run Controls
• Stack View
• Active Debug Sessions
• Variables
• Registers
• Signals
Memory View
63Copyright © 2005 Altera Corporation
Nios II IDE DebuggerNios II IDE Debugger
Step ReturnStep Return
Step OverStep Over
Step IntoStep Into
Step with FiltersStep with Filters
DisconnectDisconnect
TerminateTerminate
SuspendSuspend
ResumeResume
Run last ConfigurationRun last Configuration
Debug last ConfigurationDebug last Configuration
64Copyright © 2005 Altera Corporation
Nios II IDE DebuggerNios II IDE Debugger
� Standard debug windows− memory− registers− Variables− breakpoints− expressions− signals
65Copyright © 2005 Altera Corporation
Nios II IDE: DebuggerNios II IDE: Debugger
� Debug each CPU by selecting it’s program thread
Copyright © Altera Corporation
AppendixAppendix
67Copyright © 2005 Altera Corporation
� Pipelined RISC Architecture
� 32-Bit Instruction and Data Paths
� 6 Stage Pipeline� 32 General Purpose Registers
� 32 External Interrupt Sources
� Configurable Size Instruction Cache� Dynamic Branch Prediction
� Hardware Multiply
� Barrel Shifter� Custom Instructions
� Configurable Size Data Cache
� Hardware Breakpoints� Optional Hardware Divide
Nios II/f – Fast versionNios II/f – Fast version� 135MHz� 1.2 DMIPS/MHz
� <1800 LEs and <900 ALMs
68Copyright © 2005 Altera Corporation
� Pipelined RISC Architecture
� 32-Bit Instruction and Data Paths
� 5 Stage Pipeline� 32 General Purpose Registers
� 32 External Interrupt Sources
� Configurable Size Instruction Cache� Branch Prediction
� Hardware Multiply
� Barrel Shifter� Custom Instructions
Nios II/s – Standard versionNios II/s – Standard version� 135MHz� 0.75 DMIPS/MHz
� <1400 LEs and <700 ALMs
69Copyright © 2005 Altera Corporation
� Pipelined RISC Architecture
� 32-Bit Instruction and Data Paths
� 5 Stage Single Instruction Pipeline� 32 General Purpose Registers
� 32 External Interrupt Sources
� Custom Instructions
Nios II/e – Economy versionNios II/e – Economy version� 150 MHz
� 0.16 DMIPS/MHz� <700 LEs and <350 ALMs
Recommended