Making the Difference Daily For Internal Use Only FUTURE ELECTRONICS Nios II and SOPC Builder 培训

For Internal Use Only Making the DifferenceDaily

FUTURE ELECTRONICS

Nios II and SOPC Builder 培训


在这一天我们将了解到的

　　什么是软核 CPU ，使用软核 CPU 和传统硬核 CPU 的不同　　什么是 NIOS II ，使用 NIOS 进行系统设计的优势和好处什么是 SOPC 如何使用 SOPC 去构建一个满足客户需求的 NIOS II CPU( 性能分析，器件选择，嵌入式扩展）　　如何将定制好的 CPU 放入 FPGA ，综合步线 , 软件程序编写调试．关于 NIOS2 Avalon Switch Fabric 总线用户指令模块　　 NIOSII 的程序存放空间问题．存储器的选择和使用　　一些成功的 NIOS 设计案例边学边实验

Making the DifferenceDaily

什么是软核 CPU ，使用软核 CPU 和传统硬核 CPU 的不同

传统硬核处理器

传统的硬核处理器件是一种已经设计固定，不可扩充不可修改的固定硬件 CPU,比如ARM核，５１核， powerpc,８６０内核等，其性能， IO,嵌入式设备，中断等硬件指标都是固定芯片设计好的．当我们做一个设计时，就需要我们去在众多的处理器中选择一款适合自己项目的处理器来使用

　　什么是适合自己的处理器呢？

A 运算性能

B 外围接口及嵌入式的硬件设备 , 存储器支持

C IO 中断资源，片内外存储器资源， DMA 通道的数量等

D 功耗


NIOS软核，一种由用户来定制，量身裁减的 CPU内核 nios软核是一种利用 FPGA内部逻辑资源，采用可选的 Alter内核 MCU IP,然后根据用户具体的应用和需要进行外围嵌入式硬件的裁减，定制而成的 CPU.其性能，适用范围，外围硬件扩展能力可以完全由客户自己去选择和生成．而选择和生成所有的这一切过程都由后面将谈到的 SOPC系统来完成．

还是上面的问题 . 那什么是适合自己的处理器呢？

　　 A 运算性能　　　　　　 B 外围接口及嵌入式的硬件接口

　　 MCU 的内核结构（ IP) 　　　　　　　　　例如网口（ MAC),I2C,SPI,SDRAM 接口， DDR/DD2

　　　是可以选择的接口， flash 接口，　　　　　　　　　　　　　　　　　　　

　 C IO 中断资源，片内外　　 D 功耗

　　存储器资源， DMA 通道　整个 MCU 部分被放进 FPGA

　　 IO, 中断 .DMA 通道数量完全是

客户自己来选择的


What is Nios II?What is Nios II?What is Nios II?What is Nios II?

Altera’s Second Generation Soft-Core 32 Bit RISC Microprocessor

– Developed Internally By Altera– Harvard Architecture– Royalty-Free

FPGA

- Nios II Plus All Peripherals Written In HDL

- Can Be Targeted For All Altera FPGAs

- Synthesis Using Quartus II Integrated Synthesis

Av

alo

n S

wit

ch

Fa

bri

c UART

GPIO

Timer

SPI

SDRAMController

On-ChipROM

On-ChipRAM

Nios IICPUDebug

Cac

he


NIOS2 软核更多的特殊特性和优点　　用户自定义硬件指令高度可配置的 DSP 处理性能　　软件逻辑硬件化实现的的 ICH 功能　　与逻辑的高度紧密集合　　所有适合 FPGA 调试的工具都能用到 NIOS ２的调试上来，特别是比如 SignalTap™ II Logic Analyzer 的使用大大简化调试的难度 .

　　　　　　　　　　　　　　　　　　　　　　　　


一种传统的硬件系统构架一种传统的硬件系统构架一种传统的硬件系统构架一种传统的硬件系统构架

Flash

SDRAM

CPU

DSP

I/O

I/O

I/O FPGA

I/O I/O I/O

CPU DSP

Solution: Replace External Devices with Programmable Logic

FPGA


System-On-a-Programmable-Chip System-On-a-Programmable-Chip (SOPC)(SOPC)

System-On-a-Programmable-Chip System-On-a-Programmable-Chip (SOPC)(SOPC)

CPU is a Critical Control Function Required for System-Level Integration

Flash

SDRAM

FPGA


32-BitNios II

ProcessorROM

(with Monitor)

On-Chip Off-Chip

Address (32)

Read

Write

Data In (32)

Data Out (32)

IRQ

IRQ #(6)

Avaln

Sw

itch F

abric

Nios II Processor

Standard Reference Design Block Standard Reference Design Block DiagramDiagram

Standard Reference Design Block Standard Reference Design Block DiagramDiagram

Tri-StateBridge

Le

ve

l S

hif

ter

16MB Compact FLASH

SDRAMController

8MB FLASH

1MB SRAM

Ethernet MAC/PHY

32MB SDRAM

Tri-StateBridge

Compact Flash PIOs

Button PIO7-Segment

LED PIOLCD PIOLED PIO

General Purpose

Timer

Periodic Timer

UART

8 LEDsExpansion

Header J12

2 Digit Display

4 Momentary

buttons

Reconfig PIO


User-DefinedInterface

MemoryInterface

On-ChipDebug Core

Off-ChipSoftware Trace

Memory

UART n

Timer n

SPI n

GPIO n

DMA n

Avalon Switch Fabric

Instr.

Data

AddressDecoder

InterruptController

Wait StateGeneration

Data inMultiplexer

DynamicBus Sizing

AvalonMaster/SlavePort

Interfaces

MasterArbitration

Typical Nios II System ArchitectureTypical Nios II System ArchitectureTypical Nios II System ArchitectureTypical Nios II System Architecture

UART 0

Timer 0

SPI 0

GPIO 0

DMA 0

MemoryInterface

User-DefinedInterface

Nios IICPU

Clock Domain Crossing


Nios II Processor Block DiagramNios II Processor Block DiagramNios II Processor Block DiagramNios II Processor Block Diagram

ProgramController

&Address

Generation Instruction

Cache

clock

reset

irq[31..0]

ControlRegistersctl0 to ctl4

ArithmeticLogic Unit

Hardware-Assisted

Debug Module

InterruptController

JTAG interfaceto Software Debugger

Custom Instruction

Logic

ExceptionController

Instruction Bus

DataCache

Data Bus

General PurposeRegistersr0 to r31

CustomI/O Signals

Nios II Processor Core

Tightly-Coupled Instruction Mem

Tightly-Coupled Instruction Mem

Tightly-Coupled Data Mem

Tightly-Coupled Data Mem


Nios II Processor ArchitectureNios II Processor ArchitectureNios II Processor ArchitectureNios II Processor Architecture Classic Pipelined RISC Machine

– 32 General Purpose Registers– 3 Instruction Formats – 32-Bit Instructions– 32-Bit Data Path– Separate Instruction and Data Cache (configurable sizes)– Tightly-Coupled Memory Options– Branch Prediction– 32 Prioritized Interrupts– On-Chip Hardware (Multiply, Shift, Rotate)– Custom Instructions– JTAG-Based Hardware Debug Unit


Benefits of Processor IntegrationBenefits of Processor Integration

Existing FPGA

DiscreteProcessor

Existing FPGAwith Nios Core

Lower Board Costs, Fewer Components, Obsolescence-Proof

UnusedLogic

Increases Design Flexibility

Simplifies Inventory Management

Portability to Next-Generation FPGAs


Soft Core AdvantagesSoft Core Advantages

Stratix II EP2S180 & Nios II FastCPU 1% of Device220 DMIPs (each)

Complex Embedded System-on-a-Chip

Processor?Processor? How Many Processors?How Many Processors?

Cyclone Series & Nios II EconomyCPU < 20% of Device

20 DMIPsAs Low As 35¢

Low-Cost Embedded Solution

2,910 Logic Elements

179,400 Logic Elements


Data Sharing and Mutual ExclusionData Sharing and Mutual ExclusionData Sharing and Mutual ExclusionData Sharing and Mutual Exclusion

Mailboxes For Inter-Processor (and/or Multi-Threaded) Message

Passing

Hardware Mutex For Safe Resource Sharing

Shared Memory

Mailboxes (New in 5.0)Mutex


使用 NIOS 进行系统设计的优势和好处高度的灵活性

设计成本的降低大大的节省板上空间

降低 PCB 的布难度

更多更灵活的调试方法


SOPC

Altera advanced design tools


什么是 SOPC

SOPC= System-On-a-Programmable-System-On-a-Programmable-ChipChip

一个系统化的集成设计环境一个系统化的集成设计环境


SOPC BuilderSOPC BuilderSOPC BuilderSOPC Builder– System Contents Page


使用使用 SOPCSOPC 设计一款最适合自己的设计一款最适合自己的 NIOS MCUNIOS MCUNios II /f

FastNios II /sStandard

Nios II /eEconomy

Pipeline 6 Stage 5 Stage None

H/W Multiplier & Barrel Shifter 1 Cycle 3 Cycle

EmulatedIn Software

Branch Prediction Dynamic Static None

Instruction Cache ConfigurableConfigurabl

eNone

Data Cache Configurable None None

TCM (Instr / Data) Up to: 4 / 4 Up to: 4 / 0 0 / 0

Logic Usage (Logic Elements) 1400 - 1800 1200 – 1400 600 – 700

CustomInstructions Up to 256


0

50

100

150

200

250

0 500 1000 1500 2000CPU Core Size

(Logic Elements)

Pe

rfo

rma

nc

e(D

MIP

S)

Nios II: Faster & SmallerNios II: Faster & SmallerNios II: Faster & SmallerNios II: Faster & Smaller

Results Based on Stratix II FPGA

Economy

Fast

Standard

50% Smaller

Over 2X Faster10% Smaller

4X Faster


Variation with FPGA DeviceVariation with FPGA DeviceVariation with FPGA DeviceVariation with FPGA Device

0

50

100

150

200

250

0 500 1000 1500 2000Logic Elements

DM

IPS

Stratix II Stratix Cyclone HC-Stratix

Fast

Economy

Standard

Cyclone IICyclone II


0

50

100

150

200

250

300

$0.00 $1.00 $2.00 $3.00 $4.00 $5.00Cost of CPU Logic

Pe

rfo

rma

nc

e(D

MIP

S)

Processor Cost vs. PerformanceProcessor Cost vs. PerformanceProcessor Cost vs. PerformanceProcessor Cost vs. Performance

Stratix

Cyclone

Stratix II

e

s

f

e

s

f

e

s

f

e

s

f

Cyclone II


Nios II: Hard NumbersNios II: Hard NumbersNios II: Hard NumbersNios II: Hard Numbers

•FMax Numbers Based on Reference Design Running From On-Chip• Memory (Nios II/f 1.15 DMIPS / MHz)


外围扩展设备

Altera, Partner & User Cores Processors Memory Interfaces Peripherals Bridges Hardware Accelerators Import User Logic

(ie. custom peripherals) Web-Based IP Deployment

Over 60 Cores Available

Today

Altera, Partner & User Cores Processors Memory Interfaces Peripherals Bridges Hardware Accelerators Import User Logic

(ie. custom peripherals) Web-Based IP Deployment

Over 60 Cores Available

Today


Hardware Multiplier SupportHardware Multiplier SupportHardware Multiplier SupportHardware Multiplier Support

Stratix and Stratix II DSP Blocks Cyclone II Multiplier Blocks

– Multiplication using 18 x 18 Multiplier Block Optional LE Implementation

– Enables HW multiplier support for Cyclone Device Family

– Can also use in Stratix and Stratix II instead of DSP Blocks

– Mul, Shift, Rotate (~ 8 Clocks Per Mul)– Eliminates need for DSP blocks for Nios II

MUL


Hardware Multiplier AccelerationHardware Multiplier AccelerationHardware Multiplier AccelerationHardware Multiplier Acceleration

Nios II Economy version - No Multiply Hardware

– Uses GNUPro Math Library to Implement Multiplier

Nios II Standard - Full Hardware Multiplier

– 32 x 32 32 in 3 Clock Cycles if DSP block present, else uses software only multiplier

Nios II Fast - Full Hardware Multiplier

– 32 x 32 32 in 1 Clock Cycles if DSP block present, else uses software only multiplierAcceleration

HardwareClock Cycles

(32 x 32 32)

None 250

StandardMUL in Stratix

3

FastMUL in Stratix

1


如何实现设计，将定制好的 CPU 放入FPGA ，综合布线．软件程序编写调试


在 SOPC 环境中定制自己的 CPU ．产生 CPU 文

件

将定制好的 CPU 调入 quartus 环境，布局布线

在 NOIS IDE 环境中编写调试软件程序（ C 代码）


SOPC Builder FlowSOPC Builder FlowSOPC Builder FlowSOPC Builder Flow

SOPC Builder GUI

Connect Blocks

Processor Library Custom Instructions

Peripheral Library Select & Configure Peripherals, IP

IP Modules

Configure Processor

C Header files

Custom Library

Peripheral Drivers

Compiler, Linker, Debugger

Software Development

User Code

Libraries

RTOS

GNU Tools

Generate

HDL Source Files

Testbench

Synthesis &Fitter

User Design

Other IP Blocks

Hardware Development

Quartus II

On-ChipDebug

Software TraceHard Breakpoints

SignalTap® II

AlteraPLD

JTAG,Serial, orEthernet

ExecutableCode

HardwareConfiguration

FileVerification

& Debug

Nios II IDENios II IDE


SOPC Builder - System ContentsSOPC Builder - System ContentsSOPC Builder - System ContentsSOPC Builder - System Contents

Component

Connection Panel

Address Map

IRQ Priorities

Clock Domains

Target Board


Hardware designer selects Nios II version

– economy, standard, or fast

Configure the Nios II CPU Configure the Nios II CPU Configure the Nios II CPU Configure the Nios II CPU


Choose JTAG Debug CoreChoose JTAG Debug CoreChoose JTAG Debug CoreChoose JTAG Debug Core Select appropriate JTAG Debug level when configuring Nios II

processor core


Select Cache and TCM SettingsSelect Cache and TCM SettingsSelect Cache and TCM SettingsSelect Cache and TCM Settings Adjust Size of Instruction and Data Cache Memory

– Can now completely disable data cache on fast core– And also disable instruction cache as long as TCM used

Enable Instruction / Data Tightly Coupled Memory masters Control Data Cache Width

– Up to 32 byte cache line width now possible for better burst support


Tightly Coupled MastersTightly Coupled MastersTightly Coupled MastersTightly Coupled Masters Connected to tightly-coupled slaves through

– “Tightly Coupled Memory Interfaces”

– “Slaves” are on-chip true dual port memories• They allow “Normal” data master to

connect to second port, allowing reading and writing of data

Nios II CPU

Instruction Master

Data Master


Avalon Slave

Avalon SlaveTightly Coupled Instruction Master

Tightly Coupled Data Master

Slave

Slave

TCMsTCMs

Regular Instruction and Data Masters

Tightly-Coupled

Instruction and Data Masters

3232

Tightly Coupled Memory InterfaceTightly Coupled Memory Interface


SOPC Builder Produces a .PTF FileSOPC Builder Produces a .PTF FileSOPC Builder Produces a .PTF FileSOPC Builder Produces a .PTF File

Text file that records SOPC Builder edits Describes Nios II System Used by software development tools


Instantiating Top Module Into HDL Instantiating Top Module Into HDL CodeCode

Instantiating Top Module Into HDL Instantiating Top Module Into HDL CodeCode

.

.

.// The_led_pio

out_port_from_the_led_pio,

// The_my_pwm

pwm_out_from_the_my_pwm,

// The_reconfig_request_pio

bidir_port_to_and_from_the_reconfig_request_pio,

// The_sdram

zs_addr_from_the_sdram,

zs_ba_from_the_sdram,

zs_cas_n_from_the_sdram,

zs_cke_from_the_sdram,

zs_cs_n_from_the_sdram,

zs_dq_to_and_from_the_sdram,

zs_dqm_from_the_sdram,

zs_ras_n_from_the_sdram,

zs_we_n_from_the_sdram,

// The_seven_seg_pio

out_port_from_the_seven_seg_pio,

// The_uart1

rxd_to_the_uart1,txd_from_the_uart1); .

.

.

NoteNote: :

Look into your SOPC Look into your SOPC Builder output file (eg. Builder output file (eg. <my_SOPC_system>.v <my_SOPC_system>.v or .vhd file for system or .vhd file for system module definition)module definition)

１

top_module (outa, outb, clk, rst, ina,inb,inc, <etc.> );.

..

// SOPC Builder Instance in Top-Level Code:SOPC_system SOPC_instance_0 ( // 1) global signals: clk, reset_n, // The_button_pio in_port_to_the_button_pio, // The_ext_ram_bus_avalon_slave be_n_to_the_ext_ram, ext_ram_bus_address, ext_ram_bus_byteenablen, ext_ram_bus_data, ext_ram_bus_readn, ior_n_to_the_lan91c111, iow_n_to_the_lan91c111, irq_from_the_lan91c111, read_n_to_the_ext_ram, reset_to_the_lan91c111, select_n_to_the_ext_flash, select_n_to_the_ext_ram, write_n_to_the_ext_flash, write_n_to_the_ext_ram, // The_lcd_display LCD_E_from_the_lcd_display, LCD_RS_from_the_lcd_display, LCD_RW_from_the_lcd_display, LCD_data_to_and_from_the_lcd_display,

.

.

.


Integrating Block Symbol into SchematicIntegrating Block Symbol into SchematicIntegrating Block Symbol into SchematicIntegrating Block Symbol into Schematic

Drop in component as shown below Then compile design


Using Quartus II ProgrammerUsing Quartus II ProgrammerUsing Quartus II ProgrammerUsing Quartus II Programmer Launch from Quartus II after compile to program FPGA

<hardware>.sof<hardware>.sof programming file generated programming file generated during the Quartus II hardware compileduring the Quartus II hardware compile


JTAG UART

– Single JTAG Connection For:

• Device Configuration• Flash Programming• Code Download • Debug• Target STDIO

(printing)

Some Important Peripherals for Nios IISome Important Peripherals for Nios IISome Important Peripherals for Nios IISome Important Peripherals for Nios II

Compact Flash Interface

– Mass Storage Support• True IDE Mode• Compact Flash Mode

– Software Supports• Low-Level API• MicroC/OS-II File

System Support• µCLinux File System

Support

Peripheral Now Provided with the Nios II IDE and Supported through the

Nios Forum

www.niosforum.com


Some Important Peripherals for Nios IISome Important Peripherals for Nios IISome Important Peripherals for Nios IISome Important Peripherals for Nios II

SSRAM Controller– Cypress CY7C1380C Sync SRAM controller

• Provided to support SSRAM component on Cyclone II dev kit board

• Not a fully configurable general purpose controller Support for DDR/DDR2 in SOPC Builder GUI

– With burst adapter• Sequential master to interleaved slave enhancement

– Separate READ/Write duplex slaves• Automatically matches address of read/write slaves• Arbitration logic connects read/write masters to both slaves

Support for PCI and Bursting DMA in SOPC Builder GUI– Higher bandwidth transfers through PCI


Nios II Nios II SoftwareSoftware DevelopmentDevelopment

Nios II Nios II SoftwareSoftware DevelopmentDevelopment


Nios II IDE (Integrated Development Environment)*Nios II IDE (Integrated Development Environment)*Nios II IDE (Integrated Development Environment)*Nios II IDE (Integrated Development Environment)*

* Based on Eclipse Project

Leading Edge Software Development Tool

Target ConnectionsHardware (JTAG)Instruction Set

SimulatorModelSim®-Altera

SoftwareAdvanced Hardware Debug

FeaturesSoftware and

Hardware Break Points, Data Triggers, Trace

Flash Memory Programming Support


Opening the Nios II IDEOpening the Nios II IDEOpening the Nios II IDEOpening the Nios II IDELaunch the Nios II IDE from Launch the Nios II IDE from the SOPC Builder or from the SOPC Builder or from the Windows Start menuthe Windows Start menu


Workspace Dialog BoxWorkspace Dialog BoxWorkspace Dialog BoxWorkspace Dialog Box Appears when you first open Nios II IDE

– Before main tool opens Can now open Multiple Nios II IDE sessions

– Pick workspace each time Nios II IDE opened• Default C:\altera\kits\nios2\bin\eclipse\workspace

Each “workspace” has its own settings

File > switch workspace


Nios II IDE Welcome PageNios II IDE Welcome PageNios II IDE Welcome PageNios II IDE Welcome Page Get A Tool Overview Access Tutorials

Check Out New Features Open IDE Workbench


Creating a C/C++ ApplicationCreating a C/C++ ApplicationCreating a C/C++ ApplicationCreating a C/C++ ApplicationFile > New > Project


Creating a C/C++ ApplicationCreating a C/C++ ApplicationCreating a C/C++ ApplicationCreating a C/C++ Application

Link to a System Library- Select a pre-existing library- Or create a new library


Nios II IDE WorkbenchNios II IDE WorkbenchNios II IDE WorkbenchNios II IDE Workbench

List of Open Projects

Terminal window

File Viewer Window

(for C code, C++, and assembly*)

•Note: C++ files must have extension .cpp In-line assembly code offset by asm();

Outline View (view and/or open funcs, enums, classes, unions, structs, typedefs, etc.)


This Creates Two Software ProjectsThis Creates Two Software Projects- Application - Application andand System Library Project System Library Project

This Creates Two Software ProjectsThis Creates Two Software Projects- Application - Application andand System Library Project System Library Project

System Library Project

- contains system

header file, etc.

Application Project

- contains application source code


Application Application andand System Library System Library ProjectsProjects

Application Application andand System Library System Library ProjectsProjects

Application Projects build executables System Library Projects contain interface to the

hardware

– Nios II device drivers (Hardware Abstraction Layer)

– Optional RTOS (MicroC/OS-II)– Optional software components

•Eg. Lightweight TCP/IP stack, Read Only Zip File System


Adding Source Files to a ProjectAdding Source Files to a ProjectAdding Source Files to a ProjectAdding Source Files to a Project From within the Nios II IDE

– Specify Application Project folder and <file_name>.c


Adding Source Files to a ProjectAdding Source Files to a ProjectAdding Source Files to a ProjectAdding Source Files to a Project Or move source code directly into Application Project

– Right-Click and Refresh to update project


Moving Files within WindowsMoving Files within WindowsMoving Files within WindowsMoving Files within Windows Can even add files from outside Nios II IDE Project

– Right-Click and Refresh to update project


The Application and System Library both have project Properties pages

Setting Project Properties Setting Project Properties Setting Project Properties Setting Project Properties


System Library Project PropertiesSystem Library Project PropertiesSystem Library Project PropertiesSystem Library Project Properties

Specify stdio devices

Partition the memory map


Software CompilationSoftware CompilationSoftware CompilationSoftware Compilation

To compile a software application, highlight your project and select Build Project from the Projects menu

– Evaluates makefile for compiling application code


Hardware Abstraction LayerHardware Abstraction LayerHardware Abstraction LayerHardware Abstraction Layer A lightweight runtime environment for Nios II software

– Provides a level of abstraction between application code and low level hardware

– HAL libraries are generated by Nios II IDE HAL contains:

– device drivers– initialization software– file system– stdio, stderr

Device drivers automatically configured to match PTF


HAL ReferencesHAL ReferencesHAL ReferencesHAL References Each HAL project references library routines and drivers for the components

included in your Nios II system

– Located in the System Library Project


HAL System Header FileHAL System Header FileHAL System Header FileHAL System Header File

system.hsystem.h

SOPC Builder System ContentsSOPC Builder System Contents

System Library SettingsSystem Library Settings


system.hsystem.hsystem.hsystem.h

Contains macro definitions for system parameters, including peripheral configuration, for instance:

– Hardware configuration of the peripheral– Base address– IRQ priority (if any)– Symbolic name for peripheral

Does not include: static information, function prototypes, or device structures (unlike the old excalibur.h)

Located in the syslib project directory Rarely necessary to include it explicitly in your

application code, which improves rebuild time


system.h - examplesystem.h - examplesystem.h - examplesystem.h - example

.

.

./*

* button_pio configuration

*

*/

#define BUTTON_PIO_NAME "/dev/button_pio"

#define BUTTON_PIO_TYPE "altera_avalon_pio"

#define BUTTON_PIO_BASE 0x00920830

#define BUTTON_PIO_IRQ 2

#define BUTTON_PIO_HAS_TRI 0

#define BUTTON_PIO_HAS_OUT 0

#define BUTTON_PIO_HAS_IN 1

#define BUTTON_PIO_CAPTURE 1

#define BUTTON_PIO_EDGE_TYPE "ANY"

#define BUTTON_PIO_IRQ_TYPE "EDGE"

#define BUTTON_PIO_FREQ 50000000

/*

* system configuration

*

*/

#define ALT_SYSTEM_NAME "std_1s10ES"

#define ALT_CPU_NAME "cpu"

#define ALT_CPU_ARCHITECTURE "altera_nios2"

#define ALT_DEVICE_FAMILY "STRATIX"

#define ALTERA_NIOS_DEV_BOARD_STRATIX_1S10_ES

#define ALT_STDIN "/dev/jtag_uart"

#define ALT_STDOUT "/dev/jtag_uart"

#define ALT_STDERR "/dev/jtag_uart"

#define ALT_CPU_FREQ 50000000

#define ALT_CPP_CONSTRUCTORS

#define ALT_IRQ_BASE NULL

.

.

.

Defines system settings and peripheral configurations:– Replaces excalibur.h (from Nios)


Reading/Writing Hardware in Nios IIReading/Writing Hardware in Nios IIReading/Writing Hardware in Nios IIReading/Writing Hardware in Nios II

I/O macros used to access hardware

– I/O macros bypass the cache for hardware accesses

– They use STxIO or LDxIO instructions

– IORD(BASE, REGNUM)• Reads value at register

REGNUM offset from base address BASE

– IOWR(BASE,REGNUM,DATA)• Writes DATA to register

REGNUM offset from base address BASE

REGNUM = 0REGNUM = 0





BASE+8BASE+8

BASEBASE

BASE+16BASE+16


Header Files for Nios II PeripheralsHeader Files for Nios II PeripheralsHeader Files for Nios II PeripheralsHeader Files for Nios II Peripherals

Each Nios II peripheral has specific read/write macros for each register

– Example: UART (altera_avalon_uart_regs.h)

#define IORD_ALTERA_AVALON_UART_RXDATA(base) IORD(base, 0)

#define IOWR_ALTERA_AVALON_UART_RXDATA(base, data) IOWR(base, 0, data)

#define IORD_ALTERA_AVALON_UART_TXDATA(base) IORD(base, 1)

#define IOWR_ALTERA_AVALON_UART_TXDATA(base, data) IOWR(base, 1, data)

#define IORD_ALTERA_AVALON_UART_STATUS(base) IORD(base, 2)

#define IOWR_ALTERA_AVALON_UART_STATUS(base, data) IOWR(base, 2, data)


Nios II RTOS SupportNios II RTOS SupportNios II RTOS SupportNios II RTOS Support


Nios II Middleware SupportNios II Middleware SupportNios II Middleware SupportNios II Middleware Support


Micrium MicroC/OS-IIMicrium MicroC/OS-IIMicrium MicroC/OS-IIMicrium MicroC/OS-II

Micrium MicroC/OS-II

– Real-Time Operating System

– Scalable, Preemptive– Full Source Code– Developer’s License

Included– Annual Shipper’s

License Subscription Available

Read-Only ZIPFS File System

Lightweight IP

– Open Source TCP/IP

Stack

– Works with uC/OS-II

• Note: Stand-alone

version available on the

Nios Community Forum

– Small Code Footprint

– Berkeley Sockets API

– Protocol Support:

• IP, ICMP, UDP, TCP


Software Run & DebugSoftware Run & DebugSoftware Run & DebugSoftware Run & Debug


Software Run and DebugSoftware Run and DebugSoftware Run and DebugSoftware Run and Debug Nios II Run Nios II IDE JTAG Debugger Nios II ISS Nios II Console Third Party tools


Running Code On A TargetRunning Code On A TargetRunning Code On A TargetRunning Code On A Target Nios II IDE can be used to download code to target board


Running Code On A TargetRunning Code On A TargetRunning Code On A TargetRunning Code On A Target Download messages, stdout and stdin appear in console

window


Nios II IDE Run OptionsNios II IDE Run OptionsNios II IDE Run OptionsNios II IDE Run Options Nios II IDE > Run > Run…


Nios II IDE JTAG DebuggerNios II IDE JTAG DebuggerNios II IDE JTAG DebuggerNios II IDE JTAG Debugger Requirements

– Must have JTAG Debug Core enabled in CPU


Nios II IDE Debug PerspectiveNios II IDE Debug PerspectiveNios II IDE Debug PerspectiveNios II IDE Debug Perspective

Double-click to Double-click to add breakpointsadd breakpoints

Basic Debug

• Run Controls

• Stack View

• Active Debug Sessions

•Variables

•Registers

•Signals

Memory View


Re-Run Re-Run ProgramProgram

Re-start Re-start DebuggerDebugger

Nios II IDE DebuggerNios II IDE DebuggerNios II IDE DebuggerNios II IDE Debugger

Step ReturnStep Return

Step OverStep Over

Step IntoStep Into

Step with FiltersStep with Filters

DisconnectDisconnect

TerminateTerminate

SuspendSuspend

ResumeResume

Switch between Debug ConfigurationSwitch between Debug Configuration

And Run ConfigurationAnd Run Configuration


Nios II IDE DebuggerNios II IDE DebuggerNios II IDE DebuggerNios II IDE Debugger Standard debug windows

– Memory– Registers– Variables– Breakpoints– Expressions– Signals


Built-In TraceBuilt-In TraceBuilt-In TraceBuilt-In Trace Trace is Triggered on any Breakpoint or Watchpoint


Mixed Source / Disassembly ViewMixed Source / Disassembly ViewMixed Source / Disassembly ViewMixed Source / Disassembly View

User Can Now View Interleaved Source and Assembly

– Window > Show View > Other... > Debug > Disassembly


Nios II IDE Nios II IDE - - Multi-Processor LaunchMulti-Processor LaunchNios II IDE Nios II IDE - - Multi-Processor LaunchMulti-Processor Launch


Altera and Third Party Debug ChoicesAltera and Third Party Debug ChoicesAltera and Third Party Debug ChoicesAltera and Third Party Debug Choices


Nios II / FS2 ConsoleNios II / FS2 ConsoleNios II / FS2 ConsoleNios II / FS2 Console Command line debugger

– Investigate embedded hardware with or without software code running on system


Nios II / FS2 Console LaunchNios II / FS2 Console LaunchNios II / FS2 Console LaunchNios II / FS2 Console Launch FS2 Console Launches then minimizes

Note:

can also launch from SDK Shell

(nios2-console)


Avalon Switch FabricAvalon Switch FabricAvalon Switch FabricAvalon Switch Fabric


Avalon Switch FabricAvalon Switch FabricAvalon Switch FabricAvalon Switch Fabric Proprietary interconnect specification used with Nios II

Principal design goals– Low resource utilization for bus logic– Simplicity– Synchronous operation

Transfer Types– Slave Transfers– Master Transfers– Streaming Transfers– Latency-Aware Transfers– Burst Transfers

32-BitNios II

Processor

Switch PIO

LED PIO

7-SegmentLED PIO

PIO-32

User-Defined Interface

ROM(with Monitor)

UART Timer

Address (32)

Read

Write

Data In (32)

Data Out (32)

IRQ

IRQ #(6)

Avalo

n S

witch

Fab

ric

Nios II Processor


Custom-Generated for Peripherals

– Contingencies are on a Per-Peripheral Basis– System is Not Burdened by Bus Complexity

SOPC Builder Automatically Generates

– Arbitration– Address Decoding– Data Path Multiplexing– Bus Sizing– Wait-State Generation– Interrupts

Avalon Switch FabricAvalon Switch FabricAvalon Switch FabricAvalon Switch Fabric


Avalon Master PortsAvalon Master PortsAvalon Master PortsAvalon Master Ports Initiate Transfers with Avalon Switch Fabric Transfer Types

– Fundamental Read – Fundamental Write

Transfer Properties

– Latency– Streaming– Burst


Avalon Slave PortsAvalon Slave PortsAvalon Slave PortsAvalon Slave Ports Respond to Transfer Requests from Avalon Switch Fabric Transfer Types

– Fundamental Read – Fundamental Write

Transfer Properties

– Wait States– Latency– Streaming– Burst


Slave Read TransferSlave Read TransferSlave Read TransferSlave Read Transfer 0 Setup Cycles 0 Wait Cycles

clk

address,be_n

readn

chipselect

readdata

address, be_n

readdata

A C D EB


clk

address,be_n

chipselect

readn

readdata

address, be_n

readdata

Tsu

A B C D E F G H

Slave Read Transfer with Wait Slave Read Transfer with Wait StatesStates

Slave Read Transfer with Wait Slave Read Transfer with Wait StatesStates

1 Setup Cycle 1 Wait Cycle


clk

address,be_n

writedata

writen

chipselect

address, be_n

writedata

A B C D

Slave Write TransferSlave Write TransferSlave Write TransferSlave Write Transfer 0 Setup Cycles 0 Wait Cycles 0 Hold Cycles


Multiple Clock Domains Multiple Clock Domains SupportedSupported

Multiple Clock Domains Multiple Clock Domains SupportedSupported

CDX = Clock Domain Crossing Logic (inserted automatically by SOPC Builder)

MasterClock Domain 1

Slave Clock Domain 2


CDXCDX


CDXCDX


ArbiterArbiter










Multi-Clock Domain SupportMulti-Clock Domain SupportMulti-Clock Domain SupportMulti-Clock Domain Support

CDX = Clock Domain Crossing Logic

MasterClock

Domain 1



MasterClock

Domain 2

CDXCDX


ArbiterArbiter

CDXCDX

MasterClock

Domain 1

SlaveClock Domain 2

SlaveClock Domain 2

MasterClock

Domain 1


CDXCDX

ArbiterArbiter


Multi-Clock Domain SupportMulti-Clock Domain SupportMulti-Clock Domain SupportMulti-Clock Domain Support

CDX = Clock Domain Crossing Logic

MasterClock

Domain 1



MasterClock

Domain 2

CDXCDX


ArbiterArbiter

CDXCDX

MasterClock

Domain 1

SlaveClock Domain 2

SlaveClock Domain 2

MasterClock

Domain 1


CDXCDX

ArbiterArbiter


如何将外设与 Avalon 总线关联


No Need to Worry about Bus Interface Implement Only Signals Needed Peripherals Adapted to by

Avalon Switch Fabric Timing Handled Automatically Fabric Created for You Arbiters Generated for You

Creating Avalon SlaveCreating Avalon SlaveCreating Avalon SlaveCreating Avalon Slave

Concentrate Effort onPeripheral Functionality!

User Logic


Register File


Tri-State PeripheralsTri-State PeripheralsTri-State PeripheralsTri-State Peripherals Will Require Tri-State Bridge

– Available as an SOPC Builder component

Tri-State peripheral is defined by the presence of a bi-direction data port

Nios IIProcessor

Ava

lon

Tri-

Sta

te

Brid

ge

Inte

rfac

e to

U

ser

Logi

c

Off Chip Off Chip PeripheralPeripheral

FPGA


New Component EditorNew Component EditorNew Component EditorNew Component Editor


1. Create External Component Interface1. Create External Component Interface1. Create External Component Interface1. Create External Component Interface To communicate with off-

chip peripherals Base interface type on

data sheet

AMD29LV065AD CFI Flash Chip

Note: Use avalon tri-state slave interface type if interfacing to an off-chip tri-state bus


Add HDL File - For peripheral that has been encoded for FPGA

2. Interface to HDL File2. Interface to HDL File2. Interface to HDL File2. Interface to HDL File


Define Interface for Each Signal Define Interface for Each Signal TypeType

Define Interface for Each Signal Define Interface for Each Signal TypeType

Choose Interface Type: Register Slave uses native

alignment

Memory Slave uses dynamic alignment

Control Read and Write Timing Add wait and hold states View waveforms


Address Alignment – Narrow SlaveAddress Alignment – Narrow SlaveAddress Alignment – Narrow SlaveAddress Alignment – Narrow Slave

Dynamic Address Alignment (set as “Memory Slave”)

– LD from Base + 0x0: dd cc bb aa– LD from Base + 0x4: uu uu uu ee

Native Address Alignment (set Avalon “Register Slave”)

– LD from Base + 0x0: uu uu uu aa– LD from Base + 0x4: uu uu uu bb– LD from Base + 0x8: uu uu uu cc

32-BitNios II

Processor

8 Bit Peripheral

Avalo

n

32

8

aa

bb

cc

dd

ee

Peripheral Registers

Base

Base + 0x1

Base + 0x2

Base + 0x3

Base + 0x4


Address Alignment – Narrow MasterAddress Alignment – Narrow MasterAddress Alignment – Narrow MasterAddress Alignment – Narrow Master

Dynamic Address Alignment– LD from Base + 0x0: 33 22 11 00– LD from Base + 0x4: 77 66 55 44– LD from Base + 0x8: bb aa 99 88

Native Address Alignment– LD from Base + 0x0: 33 22 11 00– LD from Base + 0x4: bb aa 99 88– LD from Base + 0x8: ?? ?? ?? ?? – High bytes are unobtainable – warning issued

64 Bit Memory

Avalo

n

32

64

Memory Contents

Base

Base + 0x8

Base + 0x16

77 66 55 44 33 22 11 00

ff ee dd cc bb aa 99 88

?? ?? ?? ?? ?? ?? ?? ??

32-BitNios II

Processor


EgEg: Add User-Defined PWM to System: Add User-Defined PWM to SystemEgEg: Add User-Defined PWM to System: Add User-Defined PWM to System

This will be added to our Nios II system in the next Lab

– HDL for PWM already exists with standard micro-processor type interface

Av

alo

n

Nios II System


Custom InstructionsCustom Instructions



Add custom functionality to the Nios II design

– To take full advantage of the flexibility of FPGA

Dramatically Boost Processing Performance

– With no Increase in fMAX required

Application Examples

– Data Stream Processing (eg. Network Applications)– Application Specific Processing (eg. MP3 Audio Decode)– Software Inner Loop Optimization



Augment Nios II Instruction Set– Mux User Logic Into ALU Path of Processor Pipeline


Several Levels of CustomizationSeveral Levels of CustomizationOptional Interface to FIFO, Memory, Other Logic

Internal

Register File

a

5

b 5

5

c

readra

readrb

writerc

n

8Extended

clk

clk_en

reset

start

Multi-Cycle done

dataa

32datab

32

Combinatorialresult

32


Custom Instructions TabCustom Instructions Tab Enabled from the Custom Instructions tab in the Nios II CPU settings

in SOPC Builder


Software Interface - CSoftware Interface - CSoftware Interface - CSoftware Interface - C NIOS II IDE generates macros automatically during build process

Macros defined in system.h file

#define ALT_CI_<your instruction_name>(instruction arguments)

Example of user C-code that references Bitswap custom instruction:

#include "system.h" int main (void) { int a = 0x12345678; int a_swap = 0; a_swap = ALT_CI_BSWAP(a); return 0; }


Assembly Language Interface Assembly Language Interface Assembly Language Interface Assembly Language Interface Assembler syntax for the custom instruction:

custom N, rC, rA, rB

Two Examples:

custom 0, r6, r7, r8custom 3, c1, r2, c4

Custom Custom instruction instruction

opcode opcode numbernumber

Destination Destination register register for resultfor result

Operand 1Operand 1 Operand 2Operand 2

r = Nios II processor r = Nios II processor registerregister

c = Custom instruction c = Custom instruction internal registerinternal register


Why Custom Instruction?Why Custom Instruction?Why Custom Instruction?Why Custom Instruction? Reduce Complex Sequence of Instructions to One Instruction Example: Floating Point Multiply

Typical Flow

– Profile Code– Identify Critical Inner Loop– Create Custom Instruction Logic

• Replace One or All Instructions in Inner Loop– Import Custom Instruction Logic into Design– Call Custom Instruction from C or Assembly

float a, b, result_slow, result_fast;

result_slow = a * b; /* Takes 266 clock cycles */result_fast = ALT_CI_fpmult(a,b); /* Takes 6 clock cycles*/

Significantly Faster!

float a, b, result_slow, result_fast;

result_slow = a * b; /* Takes 266 clock cycles */result_fast = ALT_CI_fpmult(a,b); /* Takes 6 clock cycles*/

Significantly Faster!


Verilog and VHDL Templates AvailableVerilog and VHDL Templates AvailableVerilog and VHDL Templates AvailableVerilog and VHDL Templates Available

C:\altera\kits\nios2_7.2\examples\verilog\custom_instruction_template\ “ “ “ “ \VHDL\ “ …Combinatorial …Extended …Internal_Register_File …Multi-Cycle


ExampleExample: Verilog HDL Template: Verilog HDL TemplateExampleExample: Verilog HDL Template: Verilog HDL Template

// Verilog Custom Instruction Template File for Combinatorial Logic

module custominstruction(dataa, // Operand A (always required)datab, // Operand B (optional)result // result (always required)

);

// INPUTSinput [31:0] dataa;input [31:0] datab;

// OUTPUTSoutput [31:0] result;

// Custom instruction logic (note: no external interfaces are allowed in combinatorial logic)endmodule


Multi-Cycle Custom InstructionsMulti-Cycle Custom InstructionsMulti-Cycle Custom InstructionsMulti-Cycle Custom Instructions

Port list for Multi-Cycle Custom Instructions– Must have all of these ports with exact names


Extended Custom InstructionsExtended Custom InstructionsExtended Custom InstructionsExtended Custom Instructions Uses n[7..0] port to select an operation to perform.


Register File Custom InstructionsRegister File Custom InstructionsRegister File Custom InstructionsRegister File Custom Instructions

Custom

Logic

dataa[31..0]

reada

a[4..0]

result[31..0]

writec

c[4..0]

Custom instructions can select inputs from internal registers or dataa, datab ports

Custom instructions can write results to an internal register file


NIOS2 的程序存储和加载


Nios II 的 boot 过程要经历两个过程FPGA 器件本身的配置过程。 FPGA 器件在外部配置控制器或自身携带的配置控制器的控制下配置 FPGA 的内部逻辑。如果内部逻辑中使用了 Nios II ，则配置完成的 FPGA 中包含有 Nios II 软核 CPU 。Nios II 本身的引导过程。一旦 FPGA 配置成功后， Nios II 就被逻辑中的复位电路复位，从 reset 地址开始执行代码。 Nios II 的 reset 地址可以在 SOPC builder 的“ Nios II More‘CPU’setting” 页表中设置。


几种常见的

常见的几种加载方式从 EPCS 串行存储器中加载这种 boot 方式， FPGA 的配置数据和 Nios II 的程序都存放在 EPCS 器件中。 FPGA配置数据放在最前面，程序放在后面，程序可能有多个段，每个段前面都插有一个“程序记录”。一个“程序记录”由 2 个 32 位的数据构成，一个是 32 位的整数，另一个是 32 位的地址，分别用于表示程序段本身的长度和程序段的运行时地址。这个“程序记录”用于帮助 bootloader 把各个程序段搬到程序执行时真正的位置。 EPCS 是串行存贮器， Nios II 不能直接从 EPCS 中执行程序，它实际上是执行 EPCS 控制器的片

内 ROM 的代码（即 bootloader ），把 EPCS 中程序的搬到 RAM 中执行

FPGA NIOS

NIOS 程序

FPGA 配置

EPCS控制器

件


从 EPCS 中 boot 用户必须在 SOPC builder 中添加一个 EPCS 控制器，无须给它分配管腿， Quartus II 会自动给它分配到专用管腿上。添完 EPCS 控制器后， SOPC builder 会给它分配一个 base address ，这个地址是EPCS 控制器本身携带的片上 ROM 在 Nios II 系统中的基地址，这个ROM 存有一小段 bootloader 代码，用于引导整个过程。所以，必须在 SOPC builder 的“ Nios II More‘CPU’setting” 页表中把 reset地址设置为这个基地址，使得 Nios II 复位后从这个地址开始执行以完成整个引导过程

整个 boot 过程是由 nios ide 软件加入到用户程序中完成 .

实际上 , 程序也是可以直接在 EPCS 中运行的 , 但是速度非常的慢 .


从外部 CFI 并行 flash 中加 BOOT这种 boot 方式还可以分为 2 种情况。

程序直接在 flash 中运行。这种情况程序不需要另外的 bootloader ， Nios II 复位时 reset 地址（指向 flash 内部）开始执行程序，程序必须有启动代码用于搬移 .rwdata 段（因为 .rwdata 段是可读写的不能存放在 flash 中），同时如果 .RODATA 段和 .EXCEPTIONS 段连接时没有指定在 flash 中话（比如在RAM 中），也会被搬到 RAM 中，并对 .bss 段清零，设置栈的指针。这些工作都在 Crt0.s 中完成。

程序在 RAM （包括 On-chip Ram ， SDRAM ， SSRAM…泛指一般的 RAM ）中运行。这种情况需要有一个专门的 bootloader ，它把存放在 flash 中的各个程序段搬到程序执行时各个段真正的位置 .


FPGA NIOS

NIOS 程序

FPGA 配置

CFI 控制器件

CPLD

or

MCU

FPGA NIOS

NIOS 程序

CFI flash

CFI 控制器件

EPCSJTAG


从并行 flash 中 bootNios II应用常常把 Nios II 程序和 FPGA 配置数据都存放在 flash 中。这就需要一个配置控制器来驱动 flash输出配置数据完成 FPGA 的配置。配置控制器可以用一片 CPLD来实现 , 也可以使用一个小 CPU来完成。

配置完成 FPGA 后 NIOS 开始准备加载程序 , 这时候有两中选择程序的运行方式

A 直接运行 FLASH 上程序

B 使用 bootload 程序把 flash 上程序搬出影射到 RAM 中运行


Bootload 程序的插入整个 Bootload 程序的插入的过程在 NIOS2 IDE 中都是由 flash programmer 来自动判断完成的

首先 , 是我们在 IDE 的 GUI界面中分配程序运行的各个空间



当我们完成上述的分配后 ,再配合在 SOPC 中已经选定的 reset 指定位置 ,通过编译程序生成的 .ELF文件里就已经存储了这些映射关系 .

空间存储的信息 ,我们也可以通过生成 .objdump文件来了解更多的内容

Under NiosII IDE ->

Windows -> Preferences ->

NiosII



如何完成程序的烧录工作

使用 NIOS2 IDE 中的 flash programmer来自动完成这一过程

Under NiosII IDE -> tools ->

flash programmer


衍生的问题

如何加密讨论

FPGA NIOS

NIOS 程序

FPGA 配置

CFI 控制器件

CPLD

or

MCU

小加密存储器件

I2C


FPGA Hardware Design FlowFPGA Hardware Design Flowand some solusionand some solusion

FPGA Hardware Design FlowFPGA Hardware Design Flowand some solusionand some solusion


Timing Analysis - Verify Performance Specifications Were Met - Static Timing Analysis

Gate Level Simulation - Timing Simulation - Verify Design Will Work in Target Technology

tclk

Test FPGA on PC Board - Program & Test Device on Board - Use SignalTap II or Signal Probe for Debugging


Capture the state of internal nodesIn-system, at full system speeds

SignalTap™ II Logic AnalyzerSignalTap™ II Logic AnalyzerSignalTap™ II Logic AnalyzerSignalTap™ II Logic Analyzer Up to 270 MHz Multi-Analyzer

Support 1,024 Channels 128K Samples 10 Trigger Levels No Probes! Can be used

simultaneously with the Nios II IDE debugger and the FS2 console!


SignalTap™ II Logic AnalyzerSignalTap™ II Logic AnalyzerSignalTap™ II Logic AnalyzerSignalTap™ II Logic Analyzer


Future Nios II development kit provides a consistent development platform which works for all Nios II embedded processor systems. A designer using our kit needs only a PC and a JTAG download cable to create a “perfect fit” in terms of processors, peripherals, memory interfaces, performance characteristics and cost. A detailed manual is intended as a tutorial to demonstrate how the Nios II soft-core processor is built and added into the default reference design which comes programmed into the future Cyclone II badge board.

Brief introductionBrief introduction


DEMOBOARD’S FEATUREDEMOBOARD’S FEATURE Integrated LCD 、 VGA display controllers Interfaces available for PS2, URAT, VGA, Touch Screen and more, for a user’s designFull programmability of custom logic and peripherals Step-by-step reference manual for the Nios II build and work process JTAG-based debug logic supports hardware breakpoints, data triggers and on- and off-chip trace Can be used ‘as-is’ as a final hardware platform


Future Nios II Development kitFuture Nios II Development kit

Board InformationCommon Board Hardware in Kits

Common Hardware Configuration: 5 MByte SRAMTwo Serial Ports (RS-232) One Daughter Board Nec LCD control board Ps2 interfaceTouch screen interface 50-MHz Crystal (Socket), External Clock InputDMA channel Nine indication LEDs


Single Video Channel Input System


Multiple Video Channel Input System


TARGETTARGET Any field need a logic function Any field need a logic function or the exact microprocessor, or the exact microprocessor, need complete with custom need complete with custom instructions and peripherals. instructions and peripherals. Such as Mobile Video Such as Mobile Video Conferencing System, Auto Conferencing System, Auto Navigation System, Professional Navigation System, Professional Audio Mixing Console, Audio Mixing Console, Connection Module for Magic Connection Module for Magic Media Protocol, Fish Finder, Media Protocol, Fish Finder, Mobile Radio, Automotive Mobile Radio, Automotive Diagnostic Tool ,etc.Diagnostic Tool ,etc.


Agilent Alcatel Boeing Bosch Canon Casio Cisco Systems Eastman Kodak EMC Fujitsu General Instrument Hewlett Packard Hitachi IBM Kodak LM Ericsson Lucent Technologies SAS Matsushita Matsushita Communications

Motorola Motorola Communications NEC Nintendo Nokia Telecommunications Nortel Philips Research Philips Business Communications Philips Multimedia Rockwell Sanyo Sharp Siemens Siemens Information & Communications Sony Thomson Toshiba

Nios & Nios II Developers Nios & Nios II Developers (Partial List)(Partial List)Nios & Nios II Developers Nios & Nios II Developers (Partial List)(Partial List)


Siemens

WayMAX Base Station

Cisco Systems

Cisco 2600 Series RouterCisco 3600 Series Router


Sanyo PLV-Z4 Home Entertainment LCD Projector

45-inch and 55-inch Rear Projection TV


Remote Meter ReadingRemote Meter ReadingCustomer: Wireless Reading Systems, Norway

Product: Remote Energy Consumption Acquisition Processor System (RECAPS).

Reasons for Choosing Nios:

Control of Radio Transmitter/OCR Functions

Replace FPGA & Standalone Processor with Cyclone at 1/5

Cost

Increased Integration Reducing Size

Decrease in System Power

For More Details:

www.altera.com/corporate/news_room/releases/products/nr-wireless_meter_reading.html


Streaming Video InterfaceStreaming Video InterfaceCustomer: Media Works Technology, USA

Product: Video Capture Card

Reasons for Choosing Nios:

Custom Processor (Exact Fit)

Configurable Feature Allows Future Extensions of Wireless Interface

Capability to Profile Application to Adjust Hardware & Software Partitions

Custom Instruction & Hardware Acceleration Feature

For More Details:

www.eetimes.com/in_focus/communications/OEG20021202S0060


Telephony SystemTelephony SystemCustomer: Philips, France

Product: SOPHO iS3000 series of iSPBX

Reasons for Choosing Nios: Allowed Implementation of Field Upgradable ISDN Protocol

Handler Reconfiguration Lowered Costs for:

– Maintenance– Development– Final Product

Improved Performance & Reliability of Video Conference, IP Gateway Services & Computer Telephony Product Features

For More Details:

www.altera.com/corporate/news_room/releases/releases_archive/2002/products/nr-nio_philips_sopho.html


Automotive AV SystemAutomotive AV SystemCustomer: Johnson Controls Inc, USA

Product: Automotive AV System

Reasons for Choosing Nios:“For our new automotive audio video system, we have selected Altera's FPGAs because their performance, quality, & temperature specifications meet our automotive requirements. The flexibility & programmability of Altera's devices combined with its powerful Nios embedded processor provide us with the perfect solution for developing new products”

For More Details:

www.altera.com/corporate/news_room/customer_quotes/cqt-index.html


Access RouterAccess RouterCustomer: Telena Communications, USA

Product: Access Router

Reasons for Choosing Nios: Nios Development Board Enabled Early Prototyping of

Software

– Became Part of First Prototype Availability of Software & Hardware to Support LCD

Interface Enabled Internal Status to Be Read Efficient On-Chip Interfacing to L2 & L3 Hardware Features

of the ATM & Packet Over-SONET Design

For More Details:

www.altera.com/corporate/news_room/customer_quotes/cqt-index.html


Industrial Control TerminalIndustrial Control TerminalCustomer: AltaCom, France

Product: Flexible Industrial Control Terminal

Reasons for Choosing Nios: Flexibility to Implement Custom Options

– 240*128 Pixel Graphics Control– 40*16 Character Mode Display– Up to 512K SRAM– 1 M Flash– 2 UART, RS232/485– 1 SPI– 10-BaseT

For More Details:

www.altacom.fr


IP Switch RouterIP Switch RouterCustomer: Marconi

Product: BXR-48000 IP & Multiservice Switch Router

Reasons for Choosing Nios:Unprecedented Versatility with Stratix FPGAs Performance & Cost Savings128-bit High-speed Transceiver Logic (HSTL) Bus at 200 MHz.

“Our Development Team Determined That Altera FPGAs Were The Only Devices That Could Perform These Tasks, Given That They Combine Significant Embedded Memory With Exceptional Speed”

For More Details:

www.altera.com/corporate/news_room/releases/releases_archive/2003/products/nr-marconi.html


Night Vision CameraNight Vision CameraCustomer: Intevec Inc, USA

Product: Night Vision Camera Image Processing & Control

Reasons for Choosing Nios:Replace DSP with Cyclone & Nios

–Reduced Cost By 20%–Reduce Power Consumption (1/5 Previous System)

Form Factor Reduction of 50%

–Reduce 5 Separate Boards to One–Lower Manufacturing Costs–Higher Reliability

Rapid Development (4 Months)Field Upgrade Enabled Expanded Roadmap

For More Details:

www.altera.com/corporate/news_room/releases/products/nr-NightVista-Intevac.html


The End

Documents

Making the Difference Daily For Internal Use Only FUTURE ELECTRONICS Nios II and SOPC Builder 培训