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Overview
• Binary Addition– Half Adder– Full Adder– Ripple Carry Adder– Carry Lookahead Adder
• Decimal Addition (Section 3.12)– BCD Adder
Chapter 3-iv: Combinational Logic Design (3.8)
2
1-bit Adder
• Performs the addition of two binary bits.• Four possible operations: 0+0=0 0+1=1 1+0=1 1+1=10
• Circuit implementation requires 2 outputs; one to indicate the sum (S) and another to indicate the carry (C).
Chapter 3-iv: Combinational Logic Design (3.8)
3
Half Adder
• Performs 1-bit addition. • Inputs: A0, B0
• Outputs: S0, C1
• Index indicates significance, 0 is for LSB and 1 is for the next higher significant bit.
• Boolean equations:– S0 = A0B0’+A0’B0 = A0 + B0
– C1 = A0B0
AA00 BB00 SS00 CC11
00 00 00 0000 11 11 0011 00 11 0011 11 00 11
4Chapter 3-iv: Combinational Logic Design (3.8)
Truth Table
Half Adder (cont.)
• S0 = A0B0’+A0’B0 = A0 B0
• C1 = A0B0
5Chapter 3-iv: Combinational Logic Design (3.8)
1 bit1 bithalf adderhalf adder
Logic DiagramBlock Diagram
+
n-bit Addition
• Design an n-bit binary adder which performs the addition of two n-bit binary numbers and generates a n-bit sum and a carry out.
• Example: Let n=4
Cout C3 C2 C1 C0 1 1 0 1 0A3 A2 A1 A0 1 1 0 1
+ B3 B2 B1 B0 + 1 1 0 1---------------------- ---------------
S3 S2 S1 S0 1 0 1 0
• This requires 3-bit addition!
Chapter 3-iv: Combinational Logic Design (3.8)
6
Full Adder
• Full adder (for higher-order bit addition)• Combinational circuit that performs the
additions of 3 bits (two bits and a carry-in bit)
7Chapter 3-iv: Combinational Logic Design (3.8)
1 bit1 bitfull adderfull adder
AAii BBii
CCi+1i+1
SSii
CCii
Full Adder (cont.)
AAii BBii CCii SSii CCi+1i+1
00 00 00 00 0000 00 11 11 0000 11 00 11 0000 11 11 00 1111 00 00 11 0011 00 11 00 1111 11 00 00 1111 11 11 11 11
Chapter 3-iv: Combinational Logic Design (3.8)
8
The K-maps forCi+1:
Si:1110
0100
BBiiCCiiAAii
0101
1010
BBiiCCiiAAii
Full Adder (cont.)
Chapter 3-iv: Combinational Logic Design (3.8)
9Oct-22-10
Boolean equations:Boolean equations: CCi+1i+1 = = AAiiBBii + + AAiiCCii + + BBiiCCii
SSii = = AAiiBBii’ ’ CCii’ + ’ + AAii’B’Bii’C’Cii + + AAii’B’BiiCCii’ + ’ + AAiiBBiiCCii= A= Aii BBii CCii
You can design full adder circuit You can design full adder circuit directlydirectlyfrom the above equations (requires 3 from the above equations (requires 3 ANDs and 1 OR for CANDs and 1 OR for Ci+1i+1 and 2 XORs for Sand 2 XORs for Sii) ) Can we do better?Can we do better?
+ +
Full Adder using 2 Half Adders
Chapter 3-iv: Combinational Logic Design (3.8)
10Oct-22-10
A full adder can also be realized with two half adders and an OR gate, since Ci+1 can also be expressed as:Ci+1 = AiBi + AiBi’Ci + Ai’BiCi
= AiBi + (AiBi’ + Ai’Bi)Ci= AiBi + (Ai Bi)Ci
and Si = Ai Bi Ci+ ++
n-bit Combinational Adders
• Perform parallel multi-bit addition• Ripple Carry Adder
– Simple design– Time consuming. Why? (you’ll see in a bit!)
• Carry Lookahead Adder– More complex than ripple-carry adder– Reduces circuit delay
Chapter 3-iv: Combinational Logic Design (3.8)
11
n-bit Ripple Carry Adder
• Constructed using n 1-bit full adder blocks in parallel.
• Cascade the full adders so that the carry out from one becomes the carry in to the next higher bit position.
Chapter 3-iv: Combinational Logic Design (3.8)
12
Example: 4-bit Ripple Carry Adder
Chapter 3-iv: Combinational Logic Design (3.8)
13
CC44 C3 C2 C1 C0 C3 C2 C1 C0 A3 A2 A1 A0 A3 A2 A1 A0 +B3 B2 B1 B0 +B3 B2 B1 B0 ----------------------------S3 S2 S1 S0 S3 S2 S1 S0
Ripple Carry Adder Delay• Circuit delay in an n-bit ripple carry adder is determined by
the delay on the carry path from the LSB (C0) to the MSB (Cn).
• Let the delay in a 1-bit FA be Δ. Then, the delay of an n-bit ripple carry adder is nΔ.
14Chapter 3-iv: Combinational Logic Design (3.8)
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