institute-of-engineering-and-technology-lucknow documents

An advancement in the N×N Multiplier Architecture Realization via the Ancient Indian Vedic Mathematics
Engineering An advancement in the N×N Multiplier Architecture Realization via the Ancient Indian Vedic Mathematics
Cost Efficient Design of Reversible Adder Circuits for Low Power Applications
Engineering Cost Efficient Design of Reversible Adder Circuits for Low Power Applications
Elucidating Digital deception: Spot counterfeit fragment
Engineering Elucidating Digital deception: Spot counterfeit fragment
Preternatural Low-Power Reversible Decoder Design in 90 nm Technology Node
Engineering Preternatural Low-Power Reversible Decoder Design in 90 nm Technology Node
Xilinx HDLC
Documents Xilinx HDLC
EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N DECODER BY REVERSIBLE TECHNIQUE
Engineering EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N DECODER BY REVERSIBLE TECHNIQUE
reversible ALU
Documents reversible ALU
Reversible BCD adder
Documents Reversible BCD adder