Reversible BCD adder

Australian Journal of Basic and Applied Sciences, 9(31) September 2015, Pages: 286-298

ISSN:1991-8178

Australian Journal of Basic and Applied Sciences

Journal home page: www.ajbasweb.com

Corresponding Author: Neeraj Kumar Misra, Department of Electronics Engineering, Institute of Engineering and

Technology, Lucknow, India. E-mail id: [email protected]

Frame of Reversible BCD Adder and Carry Skip BCD Adder and Optimization Using

New Reversible Logic Gates for Quantum-Dot Cellular Automata

1Neeraj Kumar Misra, 2Subodh Wairya, 3V. K. Singh

1 ,2 ,3Institute of Engineering and Technology, Electronics Engineering department, Lucknow, India

A R T I C L E I N F O A B S T R A C T

Article history:

Received 28 August 2015

Accepted 15 September 2015

Available online 15 October 2015

Keywords:

Reversible logic, Reversible BCD

adder, Carry Skip BCD adder,

Garbage Output, Quantum cost,

Quantum-dot cellular automata.

Objective: Reversible logic has become more prominent in the field of low power

nanotechnology era. It has specially used in Quantum-dot cellular Automata (QCA)

which substituted the CMOS technology. In designing with CMOS it requires a large

layout area in making the contacts between the different devices. This work

demonstrates the reversible BCD adder and carry skip BCD adder circuit based on

three new type of reversible gates, namely, Full adder subtraction (FAS), Half adder

subtraction (HAS) and Overflow detection (OD) gates, to optimize the adders circuit.

The new type of reversible full adder using FAS gate is best circuit in terms of quantum

cost. By utilizing these three new types of gates, reversible n-digit BCD adder and 1-

digit carry skip BCD adder are also proposed with its algorithm. In addition, lower

value of reversible parameters has been presented and has more influence on reducing

the circuit cost which is far lower. This OD gate is first ever gate layout design

implemented in the QCA and that layout in QCA provided, the more suitable

simulation waveform for overflow detection. Also, the realization of the OD gate with

QCA results in minimum cell complexity, clock cycle delay (latency) and area which

are found to be 174, 3 and 0.27µm2 respectively. Area and delay analysis also show

that the circuits is optimized in terms of architectural complexity and speed.

© 2015 AENSI Publisher All rights reserved.

To Cite This Article: Neeraj Kumar Misra, Subodh Wairya and V. K. Singh, Paper title. Frame of Reversible BCD Adder and Carry Skip BCD

Adder and Optimization Using New Reversible Gates for Quantum-Dot Cellular Automata. Aust. J. Basic & Appl. Sci., 9(31): 286-298, 2015

INTRODUCTION

Reversible logic has the popular perspective of

designing digital logic operation with negligible

power consumption. It is explained by Landauer

that the loss of each bit of information dissipates

heat energy KT ln2 joules, where T is temperature

and K is the Boltzmann’s constant (Landauer, 1961). Sometime on Bennett explain that the

energy losses could be prevented, if the logic

computation is turn to reversible way (Bennett,

1973). A reversible circuit is designed by reversible

gates. In reversible gate expression, it computes is

bijective, that is, every distinct input pattern yields

a distinct output pattern (Bibhash Sen et al, 2013;

Guown yang et al, 2005;M.Mustafa et al, 2013;

Neeraj Kumar Misra et al, 2015).

Presently Quantum-dot Cellular Automata

(QCA) become an attractive research area due to high computing speed, low power and high device

density in nano-electronics digital circuits (Bibhash

Sen et al, 2015; C.S, Lent et al., 1993, Ali Newas

bahar et al, 2015).In QCA cell formation of four

quantum dots placed at the corner of a square and

comprise two free electrons (Shaahi nangiziet al,

2014, S. Hashemi et al., 2013). In QCA logic state

is laid down by the polarization of electrons. The

two stable polarization of electrons are binary logic

0 (P= -1) and binary logic 1 (P=1) as depicted in

Fig. 1e. The timing in QCA is versed by the

synchronized of four clock zones and each clock

zone has 900 phase shift as depicted in Fig 1f. The

fundamental QCA layout design are the three input majority voter gate (MV) and an inverter, depicted

in Fig 1b, 1c. The majority voter gate described as

MV (A, B, C) = AB+BC+CA. We look into that

majority vote (MV) is the optimum preference in

designing of logic design such as AND, OR as

depicted in Fig. 1d, 1h.

Arithmetic circuits like binary

Adder/Subtraction are the essential blocks of digital

circuit design (Himanshu thapliyal et al, 2008;

Majid Haghparast et al, 2008; D. Krishnaveni et al,

2011, Amir Mokhtar chabi et al, 2014). This essential blocks is mostly used in digital signal

processing (DSP) application like convolution, Fast

Fourier transform (FFT) and Laplace etc.

The rest of the paper is organized as follows:

Section 2 is dedicated to the preliminary approach

of BCD adder. The proposed three new types of

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Neeraj Kumar Misra et al, 2015

Australian Journal of Basic and Applied Sciences, 9(31) October 2015, Pages: 286-298

reversible gates and there quantum circuits are

presented in Sub-section 3.1. In Section 3.4, related

work on this BCD adder and various design issue

lemmas are reported. The carry skip BCD adder

design procedure is reported in Section 3.5. In

Section 4, deals with proposed OD gate layout and

simulation result in QCA framework.

Fig. 1: QCA fundamentals (a) Quantum cell (b) QCA, Majority voter (c) QCA, Inverter (d) QCA, AND gate

(e) Four-dot QCA cell with two different polarization (f) QCA, clock (g) QCA, Wire (h) QCA, OR gate.

2. State of the Art:

Several efforts have already been constituted to

design of reversible BCD adder and carry skip BCD adder. Preparatory, a reversible BCD adder was

presented by Ashish Kumar Biswas et al. [2008]. The

design was based on the novel MTSG gate. The BCD

adder circuit consist of 10 gate count, 10 garbage

output and 55 quantum cost. In Rigui Zhou et al.

[2012], a design frame the BCD adder, based on

novel ZRQG gate and NCG gate was designed. This

BCD adder requires 8 gate count, 11 garbage output

and 54 quantum cost. The some other parallel

adder/Subtraction and BCD adder designs are

explored (Rekha James et al, 2007; Himanshu

thapliyal et al, 2007; Majid Mohammadi et al, 2008 and H. G. Rangaraju et al, 2010). Thus, from a

careful review of the previous work on reversible

BCD adder and carry skip BCD adder design, no

such designs in QCA framework.

3. Proposed Design of Reversible BCD Adder

In this section, we design a compact circuit of

reversible BCD adder. To design a compact BCD adder, we propose three new type of reversible gates

in Subsection 3.1. In approach to less architectural

complexity, we design FAS cell and F_F_H cell in

subsection of design of parallel adder and design of

carry skip adder. These designs are then extensively

utilized to design 1-digit and n-digit BCD adder.

3.1 Three Proposed Reversible Gates:

Three new types of reversible gates are

proposed which are helpful for the design of

reversible BCD adder and carry skip BCD adder

circuit. The first is the 3x3 HAS gate. Fig. 2a, 2b depicted the block diagram and quantum

implementation of the HAS gate. The HAS gate has

a quantum cost and hardware complexity are 5 and

3α+2β+δ respectively. It consist of four XOR gates,

Tunnelling

Potential

Junction

TunnelQuantum

Well

(a)

D

A

B

C

A

B

C

MVA

CB

CA

BM

aj

ajM

(b)

0

0

11

(c)

A

B

P= -1

ABY ABY AB

(d)

Binary ‘0’,

P= -1

Binary ‘1’,

P= +1

Localised

Electron0

90 045

(e)

1Switch

2Hold

Release

Relax

3

4

(f)

A

A

BB

Wire-crossing

(g)

A

B

P= 1

BAY AB BAY

(h)



two controlled-V and one controlled-V+ gate. The

truth table of this 3x3 HAS gate is shown in Table 1.

The proposed HAS gate, can implement the

operation of half adder and half subtraction,

depicted in Fig. 2c.

HAS

Gate

A

B

C CAABR

CBAQ

AP

(a)

A

B

C

CBA

CAAB

AA

B

C

CBA

CAAB

A

(b)

HAS

Gate

A

BHAS

Gate

A

C

BASum

ABCarry

A A

CADifference

CABorrow0

0

(c)

Fig. 2: Proposed reversible HAS gate (a) Block diagram (b) Quantum implementation. (c) HAS gate implement

as half adder and half subtraction.

Table 1: Reversibility of the proposed HAS gate.

INPUT OUTPUT

A B C P Q R

0 0 0 0 0 0

0 0 1 0 1 1

0 1 0 0 1 0

0 1 1 0 0 1

1 0 0 1 1 0

1 0 1 1 0 0

1 1 0 1 0 1

1 1 1 1 1 1

The second new type of 4x4 proposed gate is the FAS gate. Fig. 3a, 3b depicted the block diagram

and quantum implementation of the FAS gate. The

FAS gate has a quantum cost and hardware

complexity are 8 and 8α+2β respectively. It consist

of six XOR gates, two controlled-V and one controlled-V+ gate. The truth table of this 4x4 FAS

gate is shown in Table 2.The proposed FAS gate,

can perform the operation of full adder and full

subtraction, depicted in Fig. 3c.



FAS

Gate

A

B

C

D

CBAP

B)DC(A)DCB(Q

CR

DCBS

(a)

A

B

C

D

CBA

B)DC(A)DCB(

C

DCB

A

B

C

D

CBA

B)DC(A)DCB(

C

DCB

(b)

FAS

GateA

B

C

FAS

Gate

CBADiff

CR

0 1

CBASum

ABC)BA(Carry

CR

BAS

A

B

C

BAS

BAC)BA(Borr

(c)

FAS

Gate

BFAS

Gate

0

C

0

CBP

BCQ

CR

CBS

A

B

0

1

BAP

BAQ

1R

BS (d)

Fig. 3: Proposed reversible FAS gate (a) Block diagram (b) Quantum implementation (c) FAS gate implement

as full adder and full subtraction (d) FAS gate implement as XOR, AND, XNOR, OR and Inverter.

Table 2: Reversibility of the proposed FAS gate.

INPUT OUTPUT

A B C D P Q R S

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 1 0 1 1

0 0 1 1 1 0 1 0

0 1 0 0 1 0 0 1

0 1 0 1 1 1 0 0

0 1 1 0 0 1 1 0

0 1 1 1 0 0 1 1

1 0 0 0 1 0 0 0

1 0 0 1 1 1 0 1

1 0 1 0 0 1 1 1

1 0 1 1 0 0 1 0

1 1 0 0 0 1 0 1

1 1 0 1 0 1 0 0

1 1 1 0 1 1 1 0

1 1 1 1 1 1 1 1

The third new type of 5x5 proposed gate is the OD

gate, which produce outputs AD)CB(P ,

BQ , CR , DS and ADED)CB(T .

Fig. 4a, 4b depicted the block diagram and quantum

implementation of the OD gate. The OD gate has a quantum cost and hardware complexity are 10 and

4α+2β respectively. It consist of seven XOR gates,

four controlled-V and two controlled-V+ gate.

The truth table of this 4x4 OD gate is shown in Table 3. When the first input is set to 0, and other four inputs

are set to 1SB , 2SC , 3SD and 3CE the OD

gate simultaneously realizes 1SQ , 2SR , 3SS

and 3213 C)SS(ST , the logic expression is

used for overflow detection, depicted in Fig. 4c.



O D

Gate

A

B

C

D

BQ

CR

E

AD)CB(P

ADED)CB(T

DS

(a)

A

B

C

D

E

AD)CB(

ADED)CB(

B

C

D

A

B

C

D

E

AD)CB(

ADED)CB(

B

C

D

(b)

3C

1S

2S

3S

0

3213 C)SS(S

1GO

OD

Gate

1S

2S

3S

(c)

Fig. 4: Proposed reversible OD gate (a) Block diagram (b) Quantum implementation (c) Block diagram of

overflow detection

Table 3: Reversibility of the proposed OD gate.

INPUT OUTPUT

A B C D E P Q R S T

0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0 1

0 0 0 1 0 1 0 0 1 0

0 0 0 1 1 1 0 0 1 1

0 0 1 0 0 1 0 1 0 0

0 0 1 0 1 1 0 1 0 1

0 0 1 1 0 0 0 1 1 1

0 0 1 1 1 0 0 1 1 0

0 1 0 0 0 1 1 0 0 0

0 1 0 0 1 1 1 0 0 1

0 1 0 1 0 0 1 0 1 1

0 1 0 1 1 0 1 0 1 0

0 1 1 0 0 1 1 1 0 0

0 1 1 0 1 1 1 1 0 1

0 1 1 1 0 0 1 1 1 1

0 1 1 1 1 0 1 1 1 0

1 0 0 0 0 1 0 0 0 0

1 0 0 0 1 1 0 0 0 1

1 0 0 1 0 0 0 0 1 1

1 0 0 1 1 0 0 0 1 0

1 0 1 0 0 0 0 1 0 0

1 0 1 0 1 0 0 1 0 1

1 0 1 1 0 1 0 1 1 0

1 0 1 1 1 1 0 1 1 1

1 1 0 0 0 0 1 0 0 0

1 1 0 0 1 0 1 0 0 1

1 1 0 1 0 1 1 0 1 0

1 1 0 1 1 1 1 0 1 1

1 1 1 0 0 0 1 1 0 0

1 1 1 0 1 0 1 1 0 1

1 1 1 1 0 1 1 1 1 0

1 1 1 1 1 1 1 1 1 1



3.2 Design of Parallel adder

In reversible design, the FAS gate can be used as

the full adder module. Therefore, 4-bit parallel adder

we use four FAS gates is depicted in Fig. 5. The

quantum cost of single FAS gate is 8.Therefore, the

quantum cost of 4-bit parallel adder is 32.

QC (4-bit parallel adder) = 4QC (FAS gate)

= 4x8 = 32.

FAS

Gate

FAS

Gate

FAS

Gate

FAS

Gate

FAS

Cell

1A

1B2

A2

B3

A3

B0 0004A

4B 1

A1

B2

A2

B3

A3

B4

A4

B

1S

2S

2S 3

S3

S

GO GO GO GO

inC

inC

0S1S3C 0S

1C2C

3C

0C

Fig. 5: Block diagram of 4-bit reversible parallel adder.

3.3 Design of Overflow Detection and Correction

Circuits:

In this section, we propose a new type of overflow

detection and correction circuit. A lemmas is offered

for circuit design.

Lemma-1:

In BCD addition, the overflow detection circuit can be realized by at least one reversible OD gate.

Proof:

A BCD number overflow occurs if the final

obtained result is greater than 9 (1001). In FAS cell,

the carry-out shown by C3and it is fixed by the FAS

cell, depicted in Fig 3c. For overflow detection carry-

out (C3) is applied to OD Gate and also other inputs its

enable the overflow detection circuit and generate

logic bit expression 3321out CS)SS(C .If

Cout=0, nothing is required for addition and another

case Cout = 1, binary 0110 (6) should be added to the

BCD sum. In overflow detection circuit utilize only

one OD gate, depicted in Fig. 4c.

Lemma-2:

A reversible BCD adder circuit, overflow

correction logic can be realized by at least three

reversible gates with 14 quantum cost.

Proof:

An overflow correction required when Cout is 1

and no correction required when Cout is 0. When Cout

= 1 required to add of 0110 (6). In this circuit, we use

one FG as a sum logic, one FAS gate implement as a

full adder and one HAS gate as half adder. The

proposed BCD overflow correction is depicted in Fig.

6. The QC of FG, FAS and HAS gate are 1, 8 and 5,

respectively; therefore the QC of the circuit is 14.

QC (Circuit of BCD overflow detection) = 1QC (FG)

+ 1QC (FAS) + 1QC (HAS) = 1+8+5=14

FAS

Gate

HAS

GateFG

outC0

1outCoutC

2outC0

2~1GO

F_F_H

Cell

3S

2Z3Z 2outC

1S2S 2S 1S outC

outC1Z2Z3Z 1Z

3S

Fig. 6: Block diagram of BCD overflow correction.

3.4 Design of BCD adder using proposed gates: A design of 1-digit BCD adder has three levels:

First level is parallel adder (Used as FAS cell), second

as overflow detection (Used as OD gate), and the third

is the overflow correction (Used as F_F_H cell),

depicted in Fig. 7a.



FAS

Cell

1S

2S

3S

outC

OD

GateF_F_H

Cell

3C

01

S

2S

3S

GO0Z

1Z

2Z

3Z

outC

1A

1B

2A

2B

3A

3B

4A

4B

Fig. 7a: Design of 1-digit BCD adder.

First level:

4-bit parallel adder operation uses an FAS cell,

initially set Cin= 0 and added a bit (B4 A4, B3 A3, B2

A2, B1 A1) and generate output marked as (S3 ,S2 ,S1

,S0) and the final carry output marked as C3

Second level:

Overflow occurs when the output logic is greater than

9 (1001) and the Coutis set by the OD gate by using

logic expression 3321out CS)SS(C .Overflow

detection design utilizes only one reversible OD gate.

Third level:

In overflow correction utilize F_F_H Cell.

The new type of 1-digit BCD adder is depicted in

Fig. 7a. It has 8 gate count, 11 garbage outputs and 7

constant inputs. Quantum cost of FAS cell, OD gate

and F_F_H cell are 32, 10 and 14, respectively;

therefore, the quantum cost of 1-digit BCD adder is

QC (1-digit BCD adder) = 1QC (FAS cell) + 1QC

(OD gate) + 1 QC (F_F_H cell) = 32+10+14 = 56

Fig. 7b depicted the circuit of n-digit BCD adder

which is designed by cascading of 1-digit BCD adder.

FAS

Cell

outC

OD

Gate

F_F_H

Cell

0 GO

P'Z

PZ

1PZ

2PZ

outC

PA

PB

1PA

1PB

2PA

2PB

3PA

3PB

PS

1PS

2PS

PC

FG

4PC

FAS

Cell

outC

OD

Gate

F_F_H

Cell

0 GO

q'Z

qZ

1qZ

2qZ

outC

qA

qB

1qA

1qB

2qA

2qB

3qA

3qB

qS

1qS

2qS

4qC

2PS

1PS

PS

0

qC

2qS

1qS

qS

Fig. 7b: Design of n-digit BCD adder.

3.5 Design of Carry Skip BCD adder using proposed

gate:

The design of carry skip 1-digit BCD adder uses

four levels. Fig. 9 depicts the carry skip 1-digit BCD

adder design.

First level indicates the design operation

performed by FAS carry skip cell (Fig. 8). The

quantum cost of single FAS gate is 8.Therefore, the

quantum cost of FAS carry skip cell is 32.

QC (FAS carry skip cell) = 4QC (FAS gate)

= 4x8 = 32.

Second level indicates the design of Carry Skip

logic, which consists of four gates of two types (3

HAS gate +1 FRG gate).The carry bit named (Y) is found by preparation of propagation logic P =

(P1P2P3P4) where iii BAP i.e4in CPPCY

for analyzing this expression set P=0 then the carry

C4propagates like in parallel adder else case Cin

propagate for carry skip logic. The generation of C4

will take time. FRG will hold for a generation of the

carry bit (Y) until C4 is solved. Third level: Design operation performed by OD

gate.

Fourth level: Design operation performed by

overflow correction by using F_F_H cell.



FAS

Gate

FAS

Gate

FAS

Gate

FAS

Gate

FAS

Carry skip

Cell

1A

1B2

A2

B3A

3B0 0004

A4

B

1S

2S

3S4

S4

C

GO GO GO GO

11BAP

22BAQ

33BAR 44

BAS

1A

1B

2A

2B

3A

3B

4A

4B

PQRS 4S 1S2S3S4C

inC

Fig. 8: Block diagram of FAS carry skip cell.

FAS

Carry skip

Cell

1A

1B

2A

2B

3A

3B

4A

4B

OD

Gate

FRG

HASGate

HASGate

HASGate

FG

Gate

F_F_H

Cell

inC

X

Y

GO

0

0 0

P 1S2SQ3SR4SS4C

GO

GOGO

2S3S4SoutC

1Z2Z1outC3Z4Z

0

GO

Fig. 9: Proposed design of Carry Skip 1-digit BCD adder.

The new type of carry skip BCD adder is depicted

in Fig. 9. It has 13 gate count, 15 garbage output and

11 constant input. Quantum cost of FAS cell, HAS,

FG, FRG, OD and F_F_H cell are 32, 5, 1, 5, 10 and

14, respectively; therefore, the quantum cost of 1-

carry skip BCD adder is

QC (1-digit carry skip BCD adder) = 1QC (FAS cell)

+ 3QC (HAS) + 1QC (FG) + 1QC (FRG) + 1QC (OD

gate) + 1 QC (F_F_H cell)

= 1x32+3x5+1+ 1x5+1x10+1x14

= 77.



4. QCA Implementation of OD Gate: We designed the QCA layout structure of the OD

gate is depicted in Fig. 11 that is composed of 174 cells

and one layer. Fig. 10 shows the QCA block diagram

of OD gate. Five of these, acting as inputs to the cell,

are marked A, B, C, D and E. The layout of the OD

gate show that there is the minimum cell used with

minimum area. The QCA layout of OD gate performs

the Boolean expression DA)CB(P , Q=B,

R=C, S=D and ADED)CB(T

5. Simulation Results and Discussion

The design of OD gate is simulated to test the

workability with QCADesigner version of 2.0.3 and

follow the truth table of this gate, depicted in Fig 12.

We simulate OD gate by using bistable approximation

with default parameters.

In addition, the overflow detection operation

performed by OD gate. The OD gate capability of

performing overflow detection condition by fixing

input A=0; and other four inputs B (S1), C (S2), D (S3)

and E (C3) are for four bits to be added the OD gate

simultaneously implements Q (S1), R (S2), S (S3) and

T (Cout). Fig. 13 reveals that when the input S3=1 and

S1=1, then the output becomes Cout=1, when the input

S3=1 and S2=1, then the output becomes Cout=1 and

when C3=1, then output become Cout=1. In a similar

way when output (Cout=1) signifies correction

required. In other case Cout=0 means no correction required. From Fig.12 and 13, we can see that

polarization value of all four output signals is fairly

better.

Maj

D means Clock0 to Clock3

D

1

B C

R

P

D1 D11 11

D2

D0

D

D3

D0

D0D1D2D3 A

D3

1

D3

D01

D1

D1

D21

D1

D1 D21

D0D3D2

D2D1D0E1

T

1D1

D1

D2

Q

1

1

1

1

1

Fig. 10: QCA block diagram of OD gate with clock zone.

Algorithm. I. Carry Skip 1-digit BCD adder.

Select 4-bit arguments (B4,A4, B3,A3, B2 , A2, B1 , A1), carry in (Cin) and generate outputs as (Cout, Z4, Z3, Z2,

Z1)

1. Begin

Level 1

2. For (i =1 to 4)

{

3. iii BAP // Propagate bit (Pi) is generated from FAS carry skip cell.

}

4. P = (P1 P2 P3 P4) // Generate P from each HAS gate.

Level 2

5. Find )CBA(S iiii // Sum from FAS carry skip cell.

6. Carry = }BAC)BA{( iiiii // Carry from FAS carry skip cell.

Level 3

7. Find outin CXXCY // Generate Y from FRG gate.

Level 4

8. Find }Y)SS(S{C 324out // Generate Cout from OD Gate.

Level 5

9. Find Cout> (9) // Overflow condition occur then add 0110 and use F_F_H Cell for correction logic.

Level 6

10. Record each output (Cout, Z4, Z3, Z2, Z1)

11. End;



Fig. 11: QCA layout of OD gate.

Fig. 12: Simulation result of OD Gate.



Fig. 13: Simulation result of overflow detection by using OD gate.

6. Design Complexity analysis of proposed OD gate

in QCA:

To evaluate the performance of the new type of OD

gate layout in QCA at different operative temperature,

they are tested at 1K to 10K. The result are obtained

by selecting coherent vector simulation in

QCADesigner-2.0.3 tool with default parameters. The

results are plotted in Fig 14. It can be authenticated

form Fig 14 the QCA layout of OD gate has work with high temperature with lesser changes in average

output node polarization. But in case of output T of

the OD gate is decrease approximately by increasing

the temperature. According to Pudi et al., the average

output polarization of any output QCA cell of the

QCA layout is decrease by raising the temperature

(Pudi and Sridharan 2011)

Table 4 represent the comparison of previous work

as well as proposed work designs with the evaluation

parameters in terms of number of gates, garbage

outputs, constant inputs, unit delay, and quantum cost

as well as circuit area in QCA.

Table 5 and 6 demonstrates the comparison of

previous works in 1-digit BCD adder and 1-digit carry

skip adder circuits with the proposed adders in terms of reversible evaluation parameters.

Table 7, it can be shown that QCA layout of OD

gate with QCA primitives requires only 174 cell

complexity, 0.27µm2 total area, 0.56 µm2 cell area,

area utilize 20.466%, 15 majority voter gates and 2 of

inverters.

Table 4: Comparison of BCD overflow detection.

Methods NOG GO CI UD QC Circuit area in

(µm2 )

Proposed design

(OD gate) 1 1 1 1 10 0.27

In

Hasan Babu et al. 2006 3 6 3 3 15 Not mentioned

In

James et al. 2007 2 1 4 2 22 Not mentioned

In

Ashiskumar Biswas et al.

2008

3 1 1 3 15 Not mentioned

In

Haghparast et al. 2008 3 6 1 3 27 Not mentioned

In 1 1 1 1 9 Not mentioned



Rigui Zhou et al. 2012

Table 5: Comparison between Proposed and existing design of BCD adder in terms of evaluation parameters.

Methods 1-digit BCD adder

NOG GO CI UD QC

Proposed work 8 11 7 8 56

In

Hasan Babu et al. 2006 23 22 9 21 139

In

James et al. 2007 9 11 8 9 144

In

Ashis kumar Biswas et al. 2008 10 10 7 10 55

In

Haghparast et al. 2008 14 22 9 13 79

In

Rigui Zhou et al. 2012 8 11 7 8 54

Table 6: Comparison between proposed and existing design of carry skip BCD adder in terms of evaluation parameters

Methods 1-digit Carry skip BCD adder

NOG GO CI UD QC

Proposed work 13 15 11 13 77

In

Himanshu Thapliyal et al. 2006 21 27 11 12 143

In

Ashis kumar Biswas et al. 2008 15 14 12 10 71

Table 7: QCA, Overflow detection behaviour analysis by using OD gate

Reversible OD gate No. of MV’s used Cell complexity Total area

(nm2) Cell area (nm2) Area usage (%)

Proposed design 15 Majority+3 Inverter 174 27,5455 56,376 20.466

Fig. 14: Temperature versus Average Output node polarization of proposed OD gate layout in QCA.

3.55

3.6

3.65

3.7

3.75

3.8

3.85

3.9

3.95

4

1K 2K 3K 4K 5K 6K 7K 8K 9K

Temperature versus average output node

polarization of OD gate

P Q R S T



Conclusion: In this paper, a new and improved type of

reversible BCD adder and carry skip BCD adder are

presented. The proposed circuits is demonstrated

around the QCA technology in terms of low clock

cycle delay, high device density, high computing

speed and no loss of power in signal transition and

propagation. In addition, we have proposed three new

reversible gates named as HAS gate, FAS gate and

OD gate to optimize adder circuit. The new FAS gate

can be utilized as a reversible full adder with using

only one gate count and eight quantum cost. The OD

gate layout verifying the QCADesigner framework

and the simulation result found to ensures the correctness of the design. During the QCA layout

design of OD gate we take care of minimizing the

cells, clock cycle delay (Latency), total area and cell

area which is found to be 174, 3, 27,5455nm2 and

56,376nm2 respectively. We have established the

optimal parameter with several definitions and

lemmas for adder circuit design. Hence we conclude

that the new reversible gates, BCD adder and carry

skip adder will be absolutely useful in low power

digital computing circuits, arithmetic and logic unit,

low power nanotechnology era and quantum computer.

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Reversible BCD adder