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  • 1. Start Group tutorial [2]Prepared byAlaa Salah ShehataMahmoud A. M. Abd El LatifMohamed Mohamed TalatMohamed Salah Mahmoud Version 02 October 2011Copyright 2006 Biz/ed

2. -Using Xilinx IP Cores-ISIM Simulator-Language Templates B 2 Copyright 2006 Biz/ed 3. Xilinx IP Cores Copyright 2006 Biz/ed 4. tutorial IP cores An IP (intellectual property) core is a block of logic or data that is used in FPGAs or ASIC for a product. Features 1-Repeated use of previously designed components. 2-Portable that is able to easily be inserted into any design methodology. 4 Copyright 2006 Biz/ed 5. tutorial StepGenerating IP Core5Copyright 2006 Biz/ed 6. tutorial 2006 Biz/ed 7. tutorial the IP selection window, find the IP tocustomize.7Copyright 2006 Biz/ed 8. tutorial For information about the customization options, click the Data Sheet button in the core customization GUI. The data sheet that appears explains all of the options. 8 Copyright 2006 Biz/ed 9. tutorial Now, we generated an IP core and this core is on this project, before generating this code you must read the data sheet to deal with its GUI, know the timing diagram and pins I/O interface of this core. 9 Copyright 2006 Biz/ed 10. tutorial Sheet 10Copyright 2006 Biz/ed 11. tutorial Step Using IP Core11 Copyright 2006 Biz/ed 12. tutorial IEEE; Now, we will make a project that adds twouse IEEE.STD_LOGIC_1164.ALL; numbers using this IP core. VHDL codeentity add is port ( in1: IN std_logic_VECTOR(14 downto 0); in2: IN std_logic_VECTOR(14 downto 0); clk: IN std_logic; enable : IN std_logic; result : OUT std_logic_VECTOR(15 downto 0));end entity;architecture Behavioral of add iscomponent adder_core port ( a: IN std_logic_VECTOR(14 downto 0); b: IN std_logic_VECTOR(14 downto 0); clk: IN std_logic; ce: IN std_logic; s: OUT std_logic_VECTOR(15 downto 0));end component; 12Copyright 2006 Biz/ed 13. tutorial : adder_core port map (a => in1,b => in2,clk => clk,ce => enable,s => result);end Behavioral;13 Copyright 2006 Biz/ed 14. tutorial Step Simulating IP CoreClick the device icon Design Utilities clickon compile HDL Simulation libraries.For simulation on Modelsim you shouldgenerate some libraries for the ip core.14 Copyright 2006 Biz/ed 15.[ISIM] ISE Simulator Copyright 2006 Biz/ed 16. tutorial Simulator 16Copyright 2006 Biz/ed 17. tutorial Simulator 17Copyright 2006 Biz/ed 18. tutorial Simulator 18Copyright 2006 Biz/ed 19. tutorial Simulator 19Copyright 2006 Biz/ed 20. tutorial Simulator 20Copyright 2006 Biz/ed 21. tutorial ISIM tutorial from Xilinx 21Copyright 2006 Biz/ed 22. TemplatesCopyright 2006 Biz/ed 23. tutorial Templates The ISE Language Templates provide predefined pieces of code and code syntax for use in your source files. These templates enable easy insertion of pre-built text structures into your VHDL file. Select Edit > Language Templates, or click the Language Templates toolbar button shown .23 Copyright 2006 Biz/ed 24. tutorial TemplatesClick the plus (+) icon to expand the folders until you find thetemplate you want to use.Select the template to display it in the right pane.Insert the code in your source file. 24Copyright 2006 Biz/ed 25. tutorial Templates you can create your own custom templates as follows. 1-Select the User Templates folder. 2-Right Click : New Folder Type a name for your folder. 3-Right Click : New Template. Type a name for your template.25 Copyright 2006 Biz/ed 26. tutorial Templates 4-Add your code to the right pane of the Language Templates window. 5-Right Click on the template name : Save Template. 6-Note To remove a template, select the template, and click the Delete toolbar button . 26Copyright 2006 Biz/ed 27. tutorial You Next Session 27Copyright 2006 Biz/ed

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