22
May 2, 2012 1 Uri Tal, CEO GPU-Accelerated Simulations

Rocketick accelerated verilog simulations

Tags:

Embed Size (px)

DESCRIPTION

 

Citation preview

Page 1: Rocketick accelerated verilog simulations

May 2, 2012 1

Uri Tal, CEO

GPU-Accelerated Simulations

Page 2: Rocketick accelerated verilog simulations

May 2, 2012 2

Long verification process In 66% of designs, verification takes >50% of the design cycle In ~40% of projects, simulation regression runtime is longer than 1

day

Large design/SoC simulation challenge >40% of designs are larger than 10M gates Difficult to simulate the entire design/SoC

Excessive computing resources Required 10’s or 100’s GBytes of memory Needs most advanced CPUs

The User ChallengeVerification Bottleneck

Effort spent on verification was increased by >58% in last 4 years

Source: 2010 Wilson Research Group and Mentor Graphics Functional Verification Study

Page 3: Rocketick accelerated verilog simulations

May 2, 2012 3

Exploding Cost of Verification

$.0B$1.0B$2.0B$3.0B$4.0B$5.0B$6.0B$7.0B$8.0B

2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011

Engineering Cost

Compute Farm

Source: Synopsys

Page 4: Rocketick accelerated verilog simulations

May 2, 2012 4

Simulation

Emulation/Acceleration

Formal Verification

Others

Functional Verification Solutions

Slide :4

Page 5: Rocketick accelerated verilog simulations

May 2, 2012 5

Simulators using CPUs

Event driven single queue of events

Memory access patterns cache miss

Multi-core CPUs: Only one order of magnitude Communication latency Limited bandwidth

Page 6: Rocketick accelerated verilog simulations

May 2, 2012 6

HW Solutions

Hardware accelerators and emulators are not simulators

Suitable for system-level debug Are very expensive – HW cost, custom design Require significant effort for bring up Are limited in capacity (large designs require several boxes)

They lack: Support for non-synthesizable code 4-state-logic Full debug visibility

Page 7: Rocketick accelerated verilog simulations

May 2, 2012 7

Simulations are Single-Threaded

Page 8: Rocketick accelerated verilog simulations

May 2, 2012 8

The Cache becomes Useless

Page 9: Rocketick accelerated verilog simulations

May 2, 2012 9

CPU Low Utilization

Thread #1 ALU Memory Load ALU Memory Load

Single thread + No “cache hit” Low CPU Utilization

Page 10: Rocketick accelerated verilog simulations

May 2, 2012 10

A Brute-Force Approach

Page 11: Rocketick accelerated verilog simulations

May 2, 2012 11

GPU Computing

Source: NVIDIA

Page 12: Rocketick accelerated verilog simulations

May 2, 2012 12

146X

Medical Imaging

U of Utah

36X

Molecular Dynamics

U of Illinois, Urbana

50X

Matlab ComputingAccelerEyes

100X

AstrophysicsRIKEN

149X

Financial simulation

Oxford

GPU Computing – cont’

Source: NVIDIA

Page 13: Rocketick accelerated verilog simulations

May 2, 2012 13

The Power of GPU

20032004

20052006

20072008

20092010

Peak Single Precision Performance GFlops/sec

Tesla 8-series

Tesla 10-series

Nehalem3 GHz

Tesla 20-series

Source: NVIDIA

Page 14: Rocketick accelerated verilog simulations

May 2, 2012 14

GPU 100% Utilization

Thread #1 ALU Memory Load ALU Memory Load

Thread #2 ALU Memory Load ALU Memory Load

Thread #3 ALU Memory Load ALU Memory Load

Thread #4 ALU Memory Load ALU Memory Load

Thread #5 ALU Memory Load ALU Memory Load

Pipelining multiple threads can increase utilization to 100%

Page 15: Rocketick accelerated verilog simulations

May 2, 2012 15

Logic Simulations - Challenge

– Billions of computing elements

– Short/simple calculations

– Many dependencies

– How to SIMD?

Page 16: Rocketick accelerated verilog simulations

May 2, 2012 16

Breaking the Dependency Barrier

Page 17: Rocketick accelerated verilog simulations

May 2, 2012 17

Compilation Stages

Analyze

•Parse source files•RTL/Static Elaboration

Compile

•Create optimal dependency graphs•Calculate optimal GPU invocation schemes

•Generate skeleton (ske.v)

Assembly

•Calculate optimal memory allocation for variables•Generate final recipes for the GPU virtual machine

Page 18: Rocketick accelerated verilog simulations

May 2, 2012 18

Distributed Compilation

Linking Phase

Compilation Phase

Splitting Phase

Splitter

Split 0

Link

Split1

Split2 Link

.

Split-n

Link

Page 19: Rocketick accelerated verilog simulations

May 2, 2012 19

Co-Simulation Approach

Page 20: Rocketick accelerated verilog simulations

May 2, 2012 20

RocketSim™ OverviewSummary Highly-cost-effective simulation offload-engine, based on GPUs

10x acceleration factor compared to Cadence ncsim & Synopsys vcs

Acceleration increases with every new GPU generation

Works seamlessly with every existing simulator (Cadence, Synopsys, …)

Zero ramp-up time

Supports extremely huge designs (Giga-gates)

Short compilation time (minutes)

Full visibility

Page 21: Rocketick accelerated verilog simulations

May 2, 2012 21

“With RocketSim, simulation time was reduced dramatically from weeks to days, with a tenfold increase in speed and five-fold decrease in server RAM requirements. This, together with support of 4-state and capacity of more than 1G gates, give us a superb tool to simulate our next generation GPU designs.”

- Dan Smith, Director of Engineering, NVIDIA

"Rocketick's RocketSim™ simulation accelerator solved verification bottleneck of our SwitchX® switch silicon IC project by running 37 days’ worth of simulation over a single weekend without changes in our standard verification environment and scripts. In addition, reducing memory consumption from 192GB to less than 8GB allowed full chip simulation of SwitchX®, which was previously impossible using standard simulators."

- Eitan Zahavi, Senior Director of Engineering, Mellanox

Customers testimonials

Page 22: Rocketick accelerated verilog simulations

May 2, 2012 22

Thank you for your time

For more information:www.rocketick.com


Verilog Fundamentals · 2016. 8. 30. · verilog fundamentals hdls history how fpga & verilog are related coding in verilog

Verilog Fundamentals · 2016. 8. 30. · verilog fundamentals hdls history how fpga & verilog are related coding in verilog

Documents
Verilog – Sequential Logic - Worcester Polytechnic Instituteusers.wpi.edu/~rjduck/Verilog for synthesis - sequential logic rev... · Verilog – Sequential Logic Verilog for Synthesis

Verilog – Sequential Logic - Worcester Polytechnic Instituteusers.wpi.edu/~rjduck/Verilog for synthesis - sequential logic rev... · Verilog – Sequential Logic Verilog for Synthesis

Documents
Debugging Numerical Simulations on Accelerated Architectures - TotalView for OpenPOWER, CUDA and OpenMP

Debugging Numerical Simulations on Accelerated Architectures - TotalView for OpenPOWER, CUDA and OpenMP

Technology
Behavioral Modeling using Verilog-A Notes/VerilogA Modeling.pdf · Verilog-AMS Verilog-AMS is an extension of Verilog-A to include digital Verilog co-simulation functionality Works

Behavioral Modeling using Verilog-A Notes/VerilogA Modeling.pdf · Verilog-AMS Verilog-AMS is an extension of Verilog-A to include digital Verilog co-simulation functionality Works

Documents
Final Report V2 - DTICproposal we described ideas to develop pure MD simulations and accelerated MD simulations that enable the simulation of 1D hypersonic flow features (such as shock

Final Report V2 - DTICproposal we described ideas to develop pure MD simulations and accelerated MD simulations that enable the simulation of 1D hypersonic flow features (such as shock

Documents
Verilog-A Language Reference Manualecee.colorado.edu/~ecen5837/software/verilog-a-anguage_reference... · Verilog-A Language Reference Manual Analog Extensions to Verilog HDL Version

Verilog-A Language Reference Manualecee.colorado.edu/~ecen5837/software/verilog-a-anguage_reference... · Verilog-A Language Reference Manual Analog Extensions to Verilog HDL Version

Documents
High-level description of Verilog Verilog For Computer Designpages.cs.wisc.edu/~karu/courses/cs552/spring2017//handouts/verilog... · Verilog For Computer Design ... specific gates,

High-level description of Verilog Verilog For Computer Designpages.cs.wisc.edu/~karu/courses/cs552/spring2017//handouts/verilog... · Verilog For Computer Design ... specific gates,

Documents
VERILOG - RWTH Aachen Universityhpac.cs.umu.se/teaching/sem-hpsc-14/presentations/Verilog slides.pdf · What is Verilog ? Verilog is a hardware description language(HDL) Verilog is

VERILOG - RWTH Aachen Universityhpac.cs.umu.se/teaching/sem-hpsc-14/presentations/Verilog slides.pdf · What is Verilog ? Verilog is a hardware description language(HDL) Verilog is

Documents
GPU-accelerated CFD Simulations for Turbomachinery …...Aissa M. , Verstraete ,T., and Vuik, c.. " Toward a GPU-aware comparison of explicit and implicit CFD simulations on structured

GPU-accelerated CFD Simulations for Turbomachinery …...Aissa M. , Verstraete ,T., and Vuik, c.. " Toward a GPU-aware comparison of explicit and implicit CFD simulations on structured

Documents
Accelerated reactive transport simulations in heterogeneous ...Accelerated reactive transport simulations in heterogeneous porous medium using Reaktoro and Firedrake Svetlana Kyasa*

Accelerated reactive transport simulations in heterogeneous ...Accelerated reactive transport simulations in heterogeneous porous medium using Reaktoro and Firedrake Svetlana Kyasa*

Documents
GPU accelerated OpenFOAM simulations with PETSc4FOAM

GPU accelerated OpenFOAM simulations with PETSc4FOAM

Documents
Cosmological Simulations on Large, Accelerated Supercomputers Adrian Pope.pdf · Cosmological Simulations on Large, Accelerated Supercomputers Adrian Pope (LANL) ICCS Workshop 27

Cosmological Simulations on Large, Accelerated Supercomputers Adrian Pope.pdf · Cosmological Simulations on Large, Accelerated Supercomputers Adrian Pope (LANL) ICCS Workshop 27

Documents
A Verilog Primer - inst.eecs.berkeley.eduinst.eecs.berkeley.edu/~eecs151/fa19/files/verilog/Verilog_Primer_Slides.pdf · Verilog Modules I Modules are the building blocks of Verilog

A Verilog Primer - inst.eecs.berkeley.eduinst.eecs.berkeley.edu/~eecs151/fa19/files/verilog/Verilog_Primer_Slides.pdf · Verilog Modules I Modules are the building blocks of Verilog

Documents
VHDL,Verilog and Advanced Verilog

VHDL,Verilog and Advanced Verilog

Documents
05-Verilog Language Concepts - Amazon S3 · PDF file2 CSE 467 Verilog Digital System Design 3 Verilog Language Concepts Module Basics (cont.) Arrays Verilog operators Verilog data

05-Verilog Language Concepts - Amazon S3 · PDF file2 CSE 467 Verilog Digital System Design 3 Verilog Language Concepts Module Basics (cont.) Arrays Verilog operators Verilog data

Documents
Temperature-accelerated dynamics and KMC …helper.ipam.ucla.edu/publications/mdws1/mdws1_10843.pdfTemperature-accelerated dynamics and KMC simulations of metal epitaxial growth! Jacques

Temperature-accelerated dynamics and KMC …helper.ipam.ucla.edu/publications/mdws1/mdws1_10843.pdfTemperature-accelerated dynamics and KMC simulations of metal epitaxial growth! Jacques

Documents
Verilog Introduction for System Verilog - Leading Edge · Verilog Introduction for System Verilog This 1 day course provides an introduction to the Verilog syntax with emphasis on

Verilog Introduction for System Verilog - Leading Edge · Verilog Introduction for System Verilog This 1 day course provides an introduction to the Verilog syntax with emphasis on

Documents
Verilog Hardware Description Language (Verilog HDL) · PDF fileVerilog HDL 2 Edited by Chu Yu Verilog HDL Brief history of Verilog HDL 1985: Verilog language and related simulator

Verilog Hardware Description Language (Verilog HDL) · PDF fileVerilog HDL 2 Edited by Chu Yu Verilog HDL Brief history of Verilog HDL 1985: Verilog language and related simulator

Documents
A Verilog Primer - University of California, Berkeleyinst.eecs.berkeley.edu/.../verilog/Verilog_Primer_Slides.pdfA Verilog Primer An Overview of Verilog for Digital Design and Simulation

A Verilog Primer - University of California, Berkeleyinst.eecs.berkeley.edu/.../verilog/Verilog_Primer_Slides.pdfA Verilog Primer An Overview of Verilog for Digital Design and Simulation

Documents
Simulations reveal increased fluctuations in estrogen … to OHT using Amber14 accelerated with Nvidia GPUs, with each run lasting 240 ns [25,29,30]. Simulations started from crystal

Simulations reveal increased fluctuations in estrogen … to OHT using Amber14 accelerated with Nvidia GPUs, with each run lasting 240 ns [25,29,30]. Simulations started from crystal

Documents
Verilog HDL - 2. Introduce to Verilog HDL

Verilog HDL - 2. Introduce to Verilog HDL

Documents
GPGPU Accelerated Cardiac Arrhythmia Simulations

GPGPU Accelerated Cardiac Arrhythmia Simulations

Documents
Advancing Large Scale Many-Body QMC Simulations on GPU ...scalettar.physics.ucdavis.edu/publications/IEEE26_308_2012.pdfAdvancing Large Scale Many-Body QMC Simulations on GPU Accelerated

Advancing Large Scale Many-Body QMC Simulations on GPU ...scalettar.physics.ucdavis.edu/publications/IEEE26_308_2012.pdfAdvancing Large Scale Many-Body QMC Simulations on GPU Accelerated

Documents
GPU-Accelerated Ab-Initio Simulations of Low …on-demand.gputechconf.com/gtc/2014/presentations/S4756-gpu-sims-ab...GPU-Accelerated Ab-Initio ... basic questions regarding the physics

GPU-Accelerated Ab-Initio Simulations of Low …on-demand.gputechconf.com/gtc/2014/presentations/S4756-gpu-sims-ab...GPU-Accelerated Ab-Initio ... basic questions regarding the physics

Documents
Introduction to Verilog - Oregon State Universityeecs.oregonstate.edu/research/vlsi/teaching/ECE472_FA12/verilog... · Introduction to Verilog ... More recently Verilog is used as

Introduction to Verilog - Oregon State Universityeecs.oregonstate.edu/research/vlsi/teaching/ECE472_FA12/verilog... · Introduction to Verilog ... More recently Verilog is used as

Documents
Verilog Hardware Description Language (Verilog HDL)

Verilog Hardware Description Language (Verilog HDL)

Documents
equations Vibrational relaxation at a metal surface: Electronic …subotnikgroup.chem.upenn.edu/.../gaohan_2d_wodtke_2017.pdf · 2017-12-21 · Accelerated path-integral simulations

equations Vibrational relaxation at a metal surface: Electronic …subotnikgroup.chem.upenn.edu/.../gaohan_2d_wodtke_2017.pdf · 2017-12-21 · Accelerated path-integral simulations

Documents
GPU-Accelerated Analysis of Petascale Molecular Dynamics ... · GPU-Accelerated Analysis of Petascale Molecular Dynamics Simulations John Stone ... • Dynamic load balancing:

GPU-Accelerated Analysis of Petascale Molecular Dynamics ... · GPU-Accelerated Analysis of Petascale Molecular Dynamics Simulations John Stone ... • Dynamic load balancing:

Documents
Verilog Tutorial - Verilog HDL Tutorial with Examples

Verilog Tutorial - Verilog HDL Tutorial with Examples

Education
3D Full Wave EM Simulations Accelerated by GPU Computingon-demand.gputechconf.com/gtc/2010/presentations/S12133-3D-Full... · 3D Full Wave EM Simulations Accelerated by GPU Computing

3D Full Wave EM Simulations Accelerated by GPU Computingon-demand.gputechconf.com/gtc/2010/presentations/S12133-3D-Full... · 3D Full Wave EM Simulations Accelerated by GPU Computing

Documents