MPHS RC Design Flow

POLITECNICO DI MILANO

Marco D. Santambrogio

[email protected]

Metodologie di Progettazine Hardware e

Software

Reconfigurable ComputingReconfigurable Computing- Design Flow- Design Flow - -

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OutlineOutline

Retargetable CompilerBasic IdeaDescription

Delft WorkbenchObjectivesProgramming paradigmWorkflowRetargetable compilerMOLEN architecture

LimboWARE: basic principlesVIRGIL

ObjectivesWorkflowRetargetable compilerYaRA architecture

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Presentation statusPresentation status





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Compiler backgroundCompiler background

Compiler is a quite complex software packageCompilers must be particularly reliableTranslation of source code into machine independent intermediate representation (IR)Design requires separation into multiple phasesCompiler is followed by Assembler, LinkerBackend: mapping machine indepent IR to machine dependent asm + machine dependent optimizations

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Retargetable CompilersRetargetable Compilers

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Retargetable Compilers – Main Retargetable Compilers – Main GoalsGoals

Adapt to new processors having a single tool for an entire class of target machinesSupport for design space exploration by editing the target processor model Tradeoff retargetability/code quality: Realistic retargetable compilers focus on a specific class of processor architectures

Def.: A compiler is called retargetable, if it can be modified to generate assembly code for different architectures, while reusing the largest part of the compiler source code.

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Retargetable Compilers - Retargetable Compilers - degreesdegrees

Parameterizable: Compiler source code is fixed, retargeting mainly by adjusting several parameters

User retargetable: User w/o in-depth compiler knowledge can change the target

Developer retargetable: Compiler developer (or very experienced user) can retarget the compiler with limited effort

Portable: Some source code can be kept, but a lot of code needs to be newly written

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Delft WorkbenchDelft WorkbenchObjectivesObjectives

Main goals:provide a semi-automatic platform for reconfigurable computing. support the entire design process (rather than isolated parts).targets uni-processor architectures with reconfigurable units (the current version exploit a PPC core processor augmented with an FPGA)

These require the development of:programming models (MOLEN)a retargetable compilers for reconfigurable platforms.introduction of hardware software co-design speculations.CAD and design space exploration.

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Delft WorkbenchDelft WorkbenchProgramming ParadigmProgramming Paradigm

The ISA is extended with 8 instructions6 instructions are required for controlling the reconfigurable hardware2 instructions are required for controlling the reconfigurable hardware

This mean that to call a FPGA function the compiler must insert code to:

SET the function“send” input parameters to the FPGAcall the EXECUTE on the FPGA“move” output values back from exchange registers

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Re-

targ

eted

Com

pile

r

BinaryCode SimpleScalar

PerformanceStatistics

FPGA

…

…

Code

int fact(int n){if(n<1) return nelsereturn(n*fact(n-1));}

f(.)

Human Directives

call f(.) HDL

Architecture

REVISE

HDL

C2C

NO

Part I

Part II

Part III

Delft WorkbenchDelft WorkbenchWorkflowWorkflow

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Generating executable code: Once a function f(.) is identified, the code containing the f(.) logic is eliminated from the source code and replaced by an appropriate FPGA call, together with the appropriate instructions for setting up the FPGA and to start its computation.

Delft WorkbenchDelft WorkbenchThe retargetable compilerThe retargetable compiler

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MOLEN ArchitectureMOLEN Architecture

CCU: Custom Configured Unit

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LimboWARE: The ideaLimboWARE: The idea

The basic idea is to postpone the decision of whether executing a task in HW or in SW moving it at run-time

This will be done not for every task, because of code memory overhead, but only where is not possible to take a wise choice at design or compile-time

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LimboWARE: When - WhereLimboWARE: When - Where

Compile-time Unbounded number of executionIf n is a number known only at run-time. The limbo choice is wiser than the corresponding one done at compile time (without this information)

for(i=0; i<n; i++){

function();

}

Execution trace dependent choice between HW and µ-code

Functionality already in HW (past)Functionality that in this branch will be used many times (constrained future)

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LimboWARELimboWAREExecution path dependent choiceExecution path dependent choice

The execution of node 6 depends on the path

If the path is 1-3-5-6 the predicate P is TRUE, is executed in HW and the relative µ-code for the SW execution is skipped, by branching after If the path is 2-4-5-6, the predicate P is FALSE, HW_CALL and JMP are not executed and the µ-code for is executed

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VIRGIL: The objectivesVIRGIL: The objectives

Provide a workbench

Integrating and adapting HW/SW codesign methodology to reconfigurable HW scenario Integration of the DRESD reconfigurable HW architecture (YaRA)Introduction of LimboWare mechanismsDevelopment of a retargetable compiler for reconfigurable hardware

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VIRGIL: Main stepsVIRGIL: Main steps

HW/SW partitioning

LimboWare code analysis

Compile the source code including special LimboWare directives

Synthesis and Mapping of the HDL (generated in the first 2 steps) to the Reconfigurable Hardware

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VIRGIL: WorkflowVIRGIL: Workflow

HLR

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VIRGIL: The CompilerVIRGIL: The Compiler

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VIRGIL: The architectureVIRGIL: The architectureYaRA - FPGA LayersYaRA - FPGA Layers

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VIRGIL: NeedsVIRGIL: Needs

Development of a retargetable compiler for reconfigurable HW integrating LW functionalities.Integrating and tailoring HW/SW codesign methodologies to reconfigurable hw and LW.Identification of LimboWare and critical function detectionWHAT in the code will be translated -> metricsDefinition of metrics of source code for SW/LW partitioning and development of the relative tools.

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QuestionsQuestions

Technology

MPHS RC Design Flow