Microprocessor

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8085

Text of Microprocessor

  • 1. Microprocessor & Microcontroller - IT.E Sem V (Rev) Prof. Nitin Ahire XIE, Mahim

2. Overview of Microprocessor MEMORYMICROPROCESSOR (CPU) INPUT OUTPUT (I/O) DEVICE5-Mar-14Prof.Nitin Ahire2 3. Functional block Diagram INPUT OUTPUT (I/O) DEVICE I/P :Key board, scanner, card reader etc O/P : Display, printer LED etc MEMORY RAM, ROM MICROPROCESSOR Central Processor Unit ( CPU ) include ALU, Timing & control unit for synchronizations 5-Mar-14Prof.Nitin Ahire3 4. Number System Decimal number system (DNS)(10) 0,1,2 ,9,10 Binary number system(2) 0,1,10,11,100 Hexadecimal number system (16) 0,1,2,..,9,A,B,C,D,E,F,10,11 Advantages of Hex No over BCD No system (1111 1111)2 (FF)16 (255)10 5-Mar-14Prof.Nitin Ahire4 5. Review for Logic Devices Tri State Devices : 3 States are logic 1, logic 0 & high impedances state ( Z )Enable Active highEnable Active Low5-Mar-14Prof.Nitin Ahire5 6. Tri-State Buffers An important circuit element that is used extensively in memory. This buffer is a logic circuit that has three states: Logic 0, logic1, and high impedance. When this circuit is in high impedance mode it looks as if it is disconnected from the output completely.The Output is LowThe Output is HighHigh Impedance6 7. The Tri-State Buffer This circuit has two inputs and one output. The first input behaves like the normal input for the circuit. The second input is an enable. If it is set high, the output follows the proper circuit behaviour. If it is set low, the output looks like a wire connected to nothing. InputOutputEnableORInputOutputEnable7 8. Review for Logic Devices Buffer e.g. 74LS244(unidirectionl) & 74LS245(Bidirection) Buffer is a logic CKT that amplifies the current or power It has one I/P line and one O/P line The logic level of O/P is the same as that of the I/P Basically used as to increase the driving capacity of logic CKTsimple buffer 5-Mar-14Active low buffer Prof.Nitin Ahire8 9. D F/F (Latch) QclkI/P I/PD F/F clkQ5-Mar-14O/PProf.Nitin Ahire9 10. Introduction to 8085 CPU built into a single semiconductor chip is called as microprocessor The microprocessor work as a brain of a computer It consist of ALU, registers and control unit The microprocessor are usually characterized by speed, word length (bit), architecture, instruction set Etc 5-Mar-14Prof.Nitin Ahire10 11. 8085 Features 8085 is a 8-bit processor Frequency of operation a) 8085 --- 3Mhz b) 8085-2 --- 5Mhz c) 8085-1 --- 6Mhz 8085 has 16 bit address bus to access memory 8 bit address bus to access I/O location 5-Mar-14Prof.Nitin Ahire11 12. 8085 Features It required only single +5V power supply 8085 has following registers a) 8 bit accumulator b) six 8- bit general purpose registers c) 8-bit flag register d) 16 bit PC and SP It has 5 hardware and 8 software interrupt 8085 required 6 Mhz crystal It can transmit and receive serial data 5-Mar-14Prof.Nitin Ahire12 13. 1 X1 2 X2 3 RESET OUT 4 SOD 5 SID 6 TRAP 7 RST 7.5 8 RST 6.5 9 RST 5.5 10 INTR 11 INTA 12 AD0 13 AD1 14 AD2 15 AD3 16 AD4 17 AD5 18 AD6 19 AD7 20 VSS 5-Mar-148085 PIN DIG40 VCC 39 HOLD 38 HLDA 37 CLOCK (OUT) 36 RESET IN X1 Crystal 6 MHz 35 READY 34IO/M 33 S1 32 RD X2 8085 31 WR (3 MHz ) 30 ALE 29 S0 28 A15 27 A14 26 A13 25 A12 24 A11 PIN DIG 23 A10 8085 22 A9 21 A8 Prof.Nitin Ahire13 14. X1 Serial I/O portsX2 vccSIDCLK CKT & P.S. H.O.A.BA8-A15SOD AD0- AD7TRAP Externally Initiated SignalRST 7.5 RST 6.5 RST 5.5 INTRREADYALE8085 Functional Pin DiagramHOLD5-Mar-14S0 S1Control & Status SignalIO/M RD WRRESET IN External Acknowledge SignalMultiplexed A/D BusINTACLK OUTHLDA Prof.Nitin AhireRESET OUT14 15. INTA RST 7.5 to 5.5TRAPSIDSODINTR P.S +5V GNDSerial I/O ControlInterrupt control8 bit Internal BUS MUXW8 I.R. 8 F/F 5ALU 8Inst. Decoder & M/C EncoderDECODREAccumulator 8 Temp. RegZ8BCDEHL SP 16 PC 16Internal latchCLK OUT RESET IN RESET OUTX1Timing and control unitA/D. Buffer Add. BufferX2 READY WR RD ALE S0 S1Prof.Nitin Ahire HOLD IO/M HLDA 5-Mar-14AD0-AD7 A15-A815 16. INTA RST 7.5 to 5.5TRAPSIDSODINTR P.S +5V GNDSerial I/O ControlInterrupt control8 bit Internal BUS MUX I.R. 8 F/F 5ALU 8Inst. Decoder & M/C EncoderDECODREAccumulator 8 Temp. Reg 8W8 BZ8 CDEHL SP 16 PC 16Internal latchCLK OUT RESET IN RESET OUTX1Timing and control unitA/D. Buffer Add. BufferX2 READY WR RD ALE S0 S1Prof.Nitin Ahire HOLD IO/M HLDA 5-Mar-14AD0-AD7 A15-A816 17. Registers The register contains a set of binary storage cells/Flip Flop 6 general purpose 8 bit Reg. B,C,D,E,H&L (or can be used as pair of 16 bit reg. like BC,DE,HL) W & Z (Temp reg.) 16 bit Reg are PC And SP 8 bit flag register 5-Mar-14Prof.Nitin AhireAFB C D E H L SP PC17 18. Interrupts Hardware interrupt Trap (Non Mask able) (vectored) RST 7.5(Mask able) (vectored) RST 6.5 (Mask able) (vectored) RST 5.5(Mask able) (vectored) INTR (Mask able) (Non vectored) Software interrupt RST 0 to RST 7 All are vectored interrupt 5-Mar-14Prof.Nitin Ahire18 19. Interrupts 8085 has 5 hardware interrupts 8 software interrupts All software interrupt are vectored Out of 5 hardware interrupt 4 are vector and 1 is non vector also 4 are maskable and one is non mask able 5-Mar-14Prof.Nitin Ahire19 20. De multiplexing Of AD0-AD7 ALE LatchAD0-AD7A0-A78085 D0-D7 IO/MA8-A155-Mar-14Prof.Nitin Ahire20 21. De multiplexing Of AD0-AD7 ALE AD0-AD7Latch A0-A78085 IO/MD0-D7 5-Mar-14Prof.Nitin Ahire21 22. Differentiate between IO/M ALE AD0-AD7LatchA0-A7IO device8085 D0-D7 A0-A7 IO/MMemory A8-A155-Mar-14Prof.Nitin Ahire22 23. 5-Mar-14Prof.Nitin Ahire23 24. Flags Register ( 8 bit ) SD7ZD6--ACD5D4 S sign flagPD3D2--D1CD0(for signed number) if D7=1 the number in accumulator will be ve number D7=0 the number in accumulator will be +ve number Z zero flag 5-Mar-14if D6=1The zero flag is set if the result in accumulator is zero Prof.Nitin Ahire24 25. Flags Register ( 8 bit ) SD7ZD6ACD5D4PD3D2CD1D0AC Auxiliary carry in the arithmetic operation, when the carry is generated digit D3 and passed on digit D4 the AC flag is setPparity flag after an arithmetic and logical operation, if the result has even number of ones the flag is set if it has odd numbers of ones, the flag is resetCY Carry flag if an arithmetic operation results in carry, the carry flag is set otherwise it is reset. The carry flag also serves as a barrow flag for subtraction5-Mar-14Prof.Nitin Ahire25 26. Subtraction process in 8085 1 : find 1s complement of the subtrahend 2 : find 2s complement of the subtrahend 3 : Adds 2s complement of the subtrahend to the minuend 4 : complements the CY flag. These steps are invisible to the user, only the result is available to the user. For unsigned number if CY is reset the result is positive and if CY is set the result is negative(2complement) 5-Mar-14Prof.Nitin Ahire26 27. Sign flag (used only for sign No.) Sign flag: This flag is used with signed numbers in the arithmetic operation. With sign number, bit D7 is reserved for indicating the sign and the remaining 7 bit are used to represent the magnitude of a number Sign flag is irrelevant for unsigned number 5-Mar-14Prof.Nitin Ahire27 28. Instruction, Data format and storage Part of instruction each instruction has two parts 1 opcode: one is the task to be perform (operational code) 2 operand: data to be operated on (data) The data can be specified in the various form it may in the memory or I/O or in the instruction it self. 5-Mar-14Prof.Nitin Ahire28 29. Opcode Opcode : operational code Operand : Data Mnemonics : Instructions Memory LocationsOpcode2000 2001 2002 2003 20043E 20 67 12 4F5-Mar-14MnemonicsOperandMVIA,20MVIB,12MOV C, A Prof.Nitin Ahire29 30. DATA BUS Internal Data BUS MEMORY LOCATIONB C(A)D EINST. DECODERH L SP CONTROL LOGICDECODERALU3E 20 67 12 4F2000 2001 2002 2003 2004PC (2000) ADD BUS MERD 3E5-Mar-14Prof.Nitin Ahire30 31. DATA BUS Internal Data BUS MEMORY LOCATIONB C(A)D EINST. DECODER 3EH L SPCONTROL LOGICDECODERALU3E 20 67 12 4F2000 2001 2002 2003 2004PC (2001) ADD BUS MERD 205-Mar-14Prof.Nitin Ahire31 32. DATA BUS Internal Data BUS MEMORY LOCATIONB C(A)D EINST. DECODERH L20SP CONTROL LOGICDECODERALU3E 20 67 12 4F2000 2001 2002 2003 2004PC (2002) ADD BUS MERD 675-Mar-14Prof.Nitin Ahire32 33. DATA BUS Internal Data BUS MEMORY LOCATIONB C(A)D EINST. DECODERH L20SP CONTROL LOGICDECODERALU3E 20 67 12 4F2000 2001 2002 2003 2004PC (2003) ADD BUS MERD 125-Mar-14Prof.Nitin Ahire33 34. DATA BUS Internal Data BUS MEMORY LOCATIONB C(A)D EINST. DECODERH L20SP CONTROL LOGICDECODERALU3E 20 67 12 4F2000 2001 2002 2003 2004PC (2004) ADD BUS MERD 4F5-Mar-14Prof.Nitin Ahire34 35. Instruction classification Instruction is a command to the microprocessor to perform a given task on specified data. The instruction can be classified into following fundamental categories 1 Data transfer 2 Arithmetic & Logical operation 3 Branching operation 4 Machine control operation 5-Mar-14Prof.Nitin Ahire35 36. Instruction classification 1 Data transfer (copy)basically used to copies data from source to destination without modifying the content of the source like, Opcode operand MOV rd, rs MVI r, 8-bit IN 8 bit port add. OUT 8 bit port add. 5-Mar-14Prof.Nitin Ahire36 37. Instruction classification 1 Data transfer (copy) LXI Rp, 16-bit add. MOV R,M MOV M,R LDA 16-bit add. STA 16-bit add. LDAX R* STAX R* LHLD 16-bit add SHLD 16-bit add *R Register pair 5-Mar-14Prof.Nitin Ahire37 38. Instruction classification Arithmetic operation These instruction perform arithmetic operation such as addition subtraction, increment, decrement. ADD R ADI data ADC R ADC M ACI data DAD Rp 5-Mar-14Prof.Nitin Ahire38 39. Instruction classification SUB R SUB M SBB R SBB M SUI Data SBI Data DAA5-Mar-14Prof.Nitin Ahire39 40. Instruction classification INR R DCR R INR M DCR M INX Rp DCX Rp5-Mar-14Prof.Nitin Ahire40 41. Instruction classification Logical instruction. These instruction perform various logical op