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In wireless communications and data acquisition systems, there is more to consider when designing and implementing a complete solution beyond simply physically connecting a high speed analog module to an FPGA platform. Available hardware description language (HDL) components and software are critical to establish an interface, which is necessary for practical system integration. This session starts with a top-level overview of various physical interfaces that are typically used and provides an in-depth focus on high speed serial JESD204B. Prototype HDL used for these types of boards is covered, along with the specific board components and how they are used to interface to high speed ADCs and DACs. Linux device drivers for the HDL components as well as for the ADI components are presented. This includes a short introduction into the Industrial I/O (IIO) framework, the benefits it offers, and how it can be used in end designs.
Citation preview
High Speed Data Connectivity More Than Hardware
Legal Disclaimer
Notice of proprietary information, Disclaimers and Exclusions Of Warranties The ADI Presentation is the property of ADI. All copyright, trademark, and other intellectual property and proprietary rights in the ADI Presentation and in the software, text, graphics, design elements, audio and all other materials originated or used by ADI herein (the "ADI Information") are reserved to ADI and its licensors. The ADI Information may not be reproduced, published, adapted, modified, displayed, distributed or sold in any manner, in any form or media, without the prior written permission of ADI. THE ADI INFORMATION AND THE ADI PRESENTATION ARE PROVIDED "AS IS". WHILE ADI INTENDS THE ADI INFORMATION AND THE ADI PRESENTATION TO BE ACCURATE, NO WARRANTIES OF ANY KIND ARE MADE WITH RESPECT TO THE ADI PRESENTATION AND THE ADI INFORMATION, INCLUDING WITHOUT LIMITATION ANY WARRANTIES OF ACCURACY OR COMPLETENESS. TYPOGRAPHICAL ERRORS AND OTHER INACCURACIES OR MISTAKES ARE POSSIBLE. ADI DOES NOT WARRANT THAT THE ADI INFORMATION AND THE ADI PRESENTATION WILL MEET YOUR REQUIREMENTS, WILL BE ACCURATE, OR WILL BE UNINTERRUPTED OR ERROR FREE. ADI EXPRESSLY EXCLUDES AND DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. ADI SHALL NOT BE RESPONSIBLE FOR ANY DAMAGE OR LOSS OF ANY KIND ARISING OUT OF OR RELATED TO YOUR USE OF THE ADI INFORMATION AND THE ADI PRESENTATION, INCLUDING WITHOUT LIMITATION DATA LOSS OR CORRUPTION, COMPUTER VIRUSES, ERRORS, OMISSIONS, INTERRUPTIONS, DEFECTS OR OTHER FAILURES, REGARDLESS OF WHETHER SUCH LIABILITY IS BASED IN TORT, CONTRACT OR OTHERWISE. USE OF ANY THIRD-PARTY SOFTWARE REFERENCED WILL BE GOVERNED BY THE APPLICABLE LICENSE AGREEMENT, IF ANY, WITH SUCH THIRD PARTY. ©2013 Analog Devices, Inc. All rights reserved.
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Today’s Agenda
High speed converter interface styles and standards
A closer look at the JESD204B converter-to-FPGA serial interface
FPGA converter systems design support offerings Evaluation and reference design boards Software and device drivers HDL interface blocks Online technical support and documentation
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Microcontrollers to FPGAs to ASICs: Trade-Offs
Microcontroller DSP FPGA ASIC
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Development Cost
Potential I/O Performance
Ease of Development
BOM Cost
Potential Signal Processing and Converter Performance
ADC Output Configurations
Parallel CMOS Fdata max = 150 MSPS
DDR LVDS Fdata max = 420 MSPS
Interface available in lower cost FPGAs
Pins = ADC resolution plus DCO
High pin count
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ADC ADC ADC
N
PLL PLL Fdata
Fdata Fdata
Fs Fs Fs
FCLK DCO
DCO
Fdata max = 1 + Gbps
Serial LVDS Fs max = Fdata × # of data
lanes/ADC resolution
On-chip PLL required
Medium to low-end FPGA typically required
Pins = # of data lanes plus Frame CLK and Data CLK
Fdata = 6.25+ Gbps Encoded serial CML Fs max = data packet
length + overhead
On-chip PLL required
GT(x) ports on FPGA required Aria, Kintex platforms, in
addition to high end Virtex and Stratix
Two pins/lane, number of lanes depends on channels, speed, resolution
PARALLEL SERIAL LVDS SerDes/JESD204
Interface Styles and Standards: Control vs. Data High speed converters almost always have a separate control
interface from the data interface Often SPI Occasionally I2C or pin-programmable
Used to access register map of converter Runs much slower than data interface SPI often runs at <40 MHz (5 Mbps)
Lower speed/precision converters may combine data and control Over SPI or I2C
Or, they may not have a control interface at all Pin-programmable No options
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Often requires dedicated software device drivers to set up and control the converter
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Why the Need for a High Speed Converter-to-FPGA Serial Interface? Today’s solution Solution with
JESD204A/JESD204B serial interface
FPGA
34 WIRES
18 WIRES
Tight timing requirements Large number of I/Os
TO ANTENNA 1
34 WIRES
18 WIRES TO
ANTENNA 2
FPGA
TO ANTENNA 1
TO ANTENNA 2
Relaxed timing requirements
with sync control Minimum number of I/Os
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SERIAL PAIRS
1 to 2
SERIAL PAIRS
1 to 2
SERIAL PAIRS
14B ADC 250 MSPS
DUAL 16B DAC DUAL 16B DAC 1.2 GSPS
14B ADC 250 MSPS
DUAL 16B DAC DUAL 16B DAC 1.2 GSPS
14B ADC 250 MSPS
14B ADC 250 MSPS
QUAD 16B DAC 2 GSPS
Why the Need for a High Speed Converter-to-FPGA Serial Interface? Simplification of overall system design Smaller/lower number of trace routes, easier to
route board designs Easier synchronization
Reduction in pin count – both the Tx and Rx side Move from high pin count low speed parallel interfaces
to low pin count high speed serial interfaces Embedded clock incorporated to even further reduce pin count
Reduction in system costs Smaller IC packages and board designs lead to lower cost
Easily scalable to meet future bandwidth requirements As geometries shrink and speed increases, the standard adapts
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What is JESD204?
JESD204, a JEDEC defined standard for high speed, point to point, serial interface, used to interconnect two (or more) devices. ADC to digital receiver. Digital source to DAC. Digital source to digital receiver.
How is it different than previous data converter interfaces? A single primary serial interface can be used to pass all data, clocking, and
framing information. The clock and frame information are embedded in the data stream. No need to worry about set up and hold time between data and clock. One PCB trace (differential) can route all bits.
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FPGA
DAC
DAC
ADC
ADC
Clock
What is the JEDEC Standard 204 (JESD204)?
JESD204 is a standard defining a multigigabit serial data link between converters and a receiver (commonly FPGA or ASIC)
JESD204 (April 2006) – original standard defining one lane, one link Defined transmission of samples across a single serial lane for multiple
converters at speeds up to 3.125 Gbps
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What is the JEDEC Standard 204 (JESD204A)?
JESD204A (April 2008) – first revision expanding standard to multiple links and multiple lanes Revision adds capability for multiple aligned serial lanes for
multiple converters at speeds up to 3.125 Gbps
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What is the JEDEC Standard 204 (JESD204B)?
JESD204B (August 2011) – third version utilizes a device clock and adds measures to ensure deterministic latency Supports multiple aligned serial lanes for multiple converters at speeds
up to 12.5 Gbps
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Multiple Converters
Up to 12.5 Gbps
Multiple Lanes
Key Aspects of JESD204x Standards
8b/10b Embedded Clock DC balanced encoding which
guarantees significant transition frequency for use with clock and data recovery (CDR) designs
Encoding allows both data and control characters – control characters can be used to specify link alignment, maintenance, monitoring, etc.
Detection of single bit error events on the link
Serial Lane Alignment Using special training patterns with control characters, lanes can be aligned across
a “link” Trace-to-trace tolerance may be relaxed, relative to synchronous sampling parallel
LVDS designs
Serial Lane Maintenance/Monitoring Alignment maintained through super-frame structure and use of specific
“characters” to guarantee alignment Link quality monitored at receiver on lane by lane basis Link established and dropped by receiver based on error thresholds
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Key Signals in JESD204A Systems
Frame Clock A clock signal in the system equal to
the frame rate of the data on the link. This is the master timing reference.
SYNC~ A system synchronous, active low signal
from the receiver to the transmitter which denotes the state of synchronization. Synchronous to the frame clock in JESD204A. When SYNC~ is low, the receiver and transmitter are synchronizing. SYNC~ and frame clock should have similar compliance in order to ensure
proper capture/transmission timing (i.e., LVDS, CMOS, CML). SYNC~ signals may be combined if multiple DACs/ADCs are involved.
Lane 0, … , L-1 Differential lanes on the link (typically high speed CML). 8B/10B code groups are transmitted MSB first/LSB last.
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Key Signals in JESD204B Systems
Device Clock A clock signal in the system which is a
harmonic of the frame rate of the data on the link. In JESD204B systems, the frame clock is no longer the master system reference.
SYNC~ Same as JESD204A except synchronous to local multiframe clocks (LMFC) instead
of the frame clock.
Lane 0, … , L-1 Same as JESD204A.
SYSREF (Optional) An optional source-synchronous, high slew rate timing resolution signal responsible
for resetting device clock dividers (including LMFC) to ensure deterministic latency. One shot, “gapped periodic” or periodic. Distributed to both ADCs/DACs and ASIC/FPGA logic devices in the system. When available, SYSREF is the master timing reference in JESD204B systems
since it is responsible for resetting the LMFC references.
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Deterministic Latency in JESD204x
Latency can be defined as deterministic when the time from the input of the JESD204x transmitter to the output of the JESD204x receiver is consistently the same number of clock cycles
In parallel implementations, deterministic latency is rather simple – clocks are carried with the data
In serial implementations, multiple clock domains exist, which can cause nondeterminism
JESD204 and JESD204A do not contain provisions for guaranteeing deterministic latency
JESD204B looks to address this issue by specifying three device subclasses: Device Subclass 0 – no support for deterministic latency Device Subclass 1 – deterministic latency using SYSREF (above 500 MSPS) Device Subclass 2 – deterministic latency using SYNC~ (up to 500 MSPS)
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LVDS vs. CML
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The increased speed of the CML driver leads to a reduction in the number of drivers by enabling more channels per lane.
With JESD204 providing up to an 80% lane reduction, the power increase of JESD204 CML is comparable to an LVDS implementation.
LVDS Max data rate < 3.125 Gbps Low power consumption
CML Max data rate ≤ 12.5 Gbps Higher power consumption
compared to LVDS
High Speed Data Connectivity: Summary
High speed converters may only attach to FPGAs/ASICs
High speed converter interfaces Converters typically feature a control and data path Data path: Require interface logic (HDL) Serial interfaces tend to be more sophisticated and, therefore, require more
know-how and interface logic. Dedicated control interfaces typically 3-wire, 4-wire SPI SPI interface → uses standard IP cores However, often more than 100 registers, with lots of control bits Complexity is with the software and initialization values
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DOCS
HW
HELP
HDL SW Rapid Development
Integration
FPGA Converter Systems Design Support Offerings
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Evaluation and Reference Design
Boards
Software and Device Drivers
HDL Interface Blocks
Online Technical Support and
Documentation
FPGA Design Support
Evaluation and Reference Design Boards
Native FMC Interface Cards
FPGA Mezzanine Card, or FMC, as defined in VITA 57, provides a specification describing an I/O mezzanine module with connection to an FPGA or other device with reconfigurable I/O capability.
Analog Devices converter products can be found on many boards, which use industry standard FMC connectors.
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http://wiki.analog.com/resources/alliances/xilinx
AD-FMCJESDADC1-EBZ
AD-FMCJESDADC1-EBZ 2× dual, 14-bit, 250 MSPS ADC
(AD9250) Clock tree (AD9517) 4 channels total Synchronized sampling across
ADCs Requires HPC-FMC (4 lanes of
GTX) for full performance Can work on LPC (1 lane) with
reduced sample rate, and 1× AD9250
Works with Xilinx® 204B HDL ADI/Xilinx reference design ADI drivers available (Linux and
No-OS)
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AD-FMCJESDADC1-EBZ
Using FPGA Evaluation Boards with ADI Converters Adapter boards exist to allow customers to use some of our
standard evaluation boards with various FPGA evaluation boards Customers are encouraged to use our evaluation platforms first, to become
familiar with the parts and their expected performance Adapter boards provide electrical connections only Reference designs exist (check wiki.analog.com)
High speed ADCs Adapter boards for Xilinx (FMC-HPC) evaluation boards are available SPI is routed through FPGA evaluation board connector FPGA (firmware) controls SPI
ADI part numbers: CVT-ADC-FMC-INTPZ
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FMC-ADC Interposer
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High speed JESD204 and SPI interface
High speed parallel interface (CMOS or LVDS)
AD-DAC-FMC-ADP
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The AD-DAC-FMC-ADP adapter board allows any of Analog Devices' DPG2-compatiable high speed DAC evaluation boards to be used on a Xilinx evaluation board with an FMC connector. The adapter board uses the low pin count (LPC) version of the FMC connector, so it can be used on either LPC or HPC hosts.
http://wiki.analog.com/resources/alliances/xilinx
System Demonstration Platform (SDP) Interposers FMC-SDP Interposer The FMC-SDP interposer
allows any Analog Devices SDP evaluation board or Circuits from the Lab® reference boards to be used on a Xilinx evaluation board with an FMC connector. The interposer uses the low
pin count (LPC) version of the FMC connector, so it can be used on either LPC or HPC hosts. The interposer can only be used with FPGA boards that support 3.3VIO for the FMC connection.
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Precision ADC Pmod Examples
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PmodAD1—Two 12-bit ADC inputs Analog Devices AD7476
PmodAD2 —4 channel, 12-bit ADC
Analog Devices AD7991 Sampling rate: 1 MSPS Resolution: 12-bit No. of channels: 2 Interface: SPI ADC type: SAR
Sampling rate: 1 MSPS Resolution: 12-bit No. of channels: 4 Interface: I2C ADC type: SAR
PmodAD4 —1 channel, 16-bit ADC
Analog Devices AD7980
PmodAD5 —4 channel, 24-bit ADC
Analog Devices AD7193 Sampling rate: 1 MSPS Resolution: 16-bit No. of channels: 1 Interface: SPI ADC type: PulSAR®
Sampling rate: 4.8 kSPS Resolution: 24-bit No. of channels: 4 Interface: SPI ADC type: Σ-Δ
HDL Interface Blocks
FPGA Projects
Analog Devices provided HDL reference designs Native FMC converter cards FMC interposers—converter evaluation board combinations Pmods SDP or Circuits from the Lab® type cards
Each reference design consists of Complete FPGA design project Including HDL and Verilog IP cores for the various components
Documentation on the Wiki No-OS device drivers, setup, and test code Linux device drivers where applicable
Source of all information is the Analog Devices Wiki
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HDL IP Interface Core
What function does it typically provide: Drives converter control signals Samples data Abstracts and mediates data up in the
hierarchy Pre and postprocessing Conversions Format, scale, offset, etc. Sign extention
Extracting, selecting data Interface timing validation PN number checker
Status, error tracking Overrange, DMA status
Allows engineers to insert custom IP, while maintaining the interfaces on both ends
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ADC
N Fdata
Fs
DCO AX
I
AXI L
ite
AXI D
MA
Con
vert
er IP
Cor
e C
usto
m IP
Example HDL Blocks: HDMI Tx/Rx and SPDIF
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This reference design provides the video and audio interface between the FPGA and ADV7511/ADV7611 HDMI Tx/Rx.
HDMI transmitter also found on various Xilinx evaluation boards: ZC702 ZC706 ZedBoard KC705, etc.
Linux DRM, V4L2, ASoC device drivers available.
ADI IP Core Xilinx IP Core
HDL Blocks: AD-FMCJESDADC1-EBZ
JESD204B serial interface
Reference design for: Virtex-7, Kintex-7, Virtex-6 KC705 ZC706 VC707 ML605
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ADI IP Core Xilinx IP Core
Effect of FR4 Channel Loss at 3.25 Gbps
33
At higher line rates, pre-emphasis and equalization techniques are used to compensate channel loss, due to the limited bandwidth of the media.
Equalization works at the receiver end while pre-emphasis on the transmitter side. Selectively boost the high frequency
components in order to compensate the channels high frequency roll off.
Quality of the line cannot be determined by measuring the far-end eye opening at the receiver pins.
Real-time oscilloscopes for multigigabit SerDes measurements cost $$$.
3.25 Gbps – Ideal Source
3.25 Gbps – After 40” FR4 How to verify link reliability?
The Statistical Eye (2D Post Equalization)
The Rx Eye Scan in Xilinx GTH, GTX, and GTP transceivers of 7 series FPGAs provides a mechanism to measure and visualize the receiver eye margin after the equalizer.
Statistical eye scan functionality on per-lane basis is based on comparison between the data sample in the nominal center of the eye and the offset sample captured by an independent and identical circuitry at a programmable horizontal and vertical offset.
Bit error (BER) is defined as a mismatch between these two samples.
Taking BER measurements at all horizontal and vertical offsets allows drawing a 2D eye diagram while enabling BER to be measured with high confidence down to 10-15.
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Nominal Sample
Offset Sample
JESD204B High-Speed ADC Demo
35
Analog Devices’ AD-FMCJESDADC1-EBZ 14-bit / 250 MSPS 4-ch ADC
AD9250 High Speed JESD204B Serdes Outputs Data Eye @ 5Gbps
Analog Input (Single-Tone FFT with fIN = 90.1 MHz)
Ethernet data connection to PC for Verification of Analog Signal on VisualAnalog™
Xilinx Kintex-7 FPGA KC705 Eval Kit
Recovered Eye (after EQ/CDR)
Software and Device Drivers
Linux Kernel Basics
Advantages of Linux Broad use as an open source desktop, server, and embedded OS Feature-rich Symmetric multiprocessing Preemptive multitasking Good RT performance Shared libraries Countless device drivers Memory management Support for almost any networking and protocol stack Support for multiple file systems
Linux kernel is a free and open-source software Licensed under the GNU Public License Therefore, easy to extend and modify
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Memory Devices
Applications
CPU
Kernel
Linux Support for Xilinx FPGA Hard and Soft Cores FPGA Hard Core: Zynq Dual core ARM Cortex™-A9 PowerPC (PPC)
Pros Avoids extra co-processor Fast data exchange between FPGA and CPU Less power, board space, and system cost
Cons: May require external memory
FPGA Soft Core: Microblaze
Pros Avoids extra co-processor Fast data exchange between FPGA and CPU A soft core can be customized to meet system
demands
Cons: Requires some extra gates and external
memory May not be as fast as a hard core Power consumption
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Linux is an ideal OS and a significant part of the ecosystem for FPGA hard and soft cores
Linux Driver Model Basics
The Linux driver model breaks all things down into: Buses Devices Classes
A bus can be described as something with devices connected to it.
A device class describes common types of devices, like sound, network, or input devices, sometimes referred as subsystems.
Examples of buses in Linux are: ACPI I2C IDE MDIO bus PCI/Express Platform (MEM mapped) PNP SCSI SERIO SPI USB
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Hardware
I2C
HWMON
SPI
IIO
Linux Driver Model Basics
Each device class defines a set of semantics and a programming interface that devices of that class adhere to.
Device drivers are typically the implementation of that programming interface for a particular device on a particular bus.
Device classes are agnostic with respect to what bus a device resides on.
The unified bus model includes a set of common attributes which all buses carry, and a set of common callbacks, such as ideal device discovery during mandatory bus probing, bus shutdown, bus power management, etc.
Summarize:
The Linux driver model provides a common, uniform data model for describing a bus and the devices that can appear under the bus.
Device drivers are agnostic with respect to what processor platform they run on, in case they are registered with a common bus that the target platform supports.
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IIO—a New Kernel Subsystem for Converters
The Linux industrial I/O subsystem is intended to provide support for devices that, in some sense, are analog-to-digital or digital-to-analog converters Devices that fall into this category are: ADCs DACs Accelerometers, gyros, IMUs Capacitance-to-Digital converters (CDCs) Pressure, temperature, and light sensors, etc.
Can be used on ADCs ranging from a SoC ADC to >100 MSPS industrial ADCs
Mostly focused on user-space abstraction, but also in-kernel API for other drivers exists IIO to Linux input or HWMON subsystem bridges
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IIO Subsystem Overview
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SYSTEM CALL INTERFACE
VIRTUAL FILE SYSTEM (VFS)
APPLICATION
CHARACTER DEVICE DRIVER
HARDWARE
Kernel Area
Application Area
Hardware
SYSFS
DEVICE DRIVER
IIO BUFFER IIO CORE IIO TRIGGER IIO Subsystem
BUS DRIVERS
IIO Device Drivers
AXI ADC Linux Driver
Each and every IIO device, typically a hardware chip, has a device folder under: /sys/bus/iio/devices/iio:deviceX. Where X is the IIO index of the
device. Under every of these directory folders resides a set of files, depending on the characteristics and features of the hardware device in question.
These files are consistently generalized and documented in the IIO ABI documentation. In order to determine which IIO deviceX corresponds to which hardware device, the user can read the name file: /sys/bus/iio/devices/iio:deviceX/
name.
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IIO Devices
Linux—everything is a file IIO control via sysfs IIO data via device nodes /dev/iio:deviceX
Attributes/files: Control converter modes Enable/disable channels Query data format, byte-
order, alignment, index Query and set Sampling frequency Test modes Reference levels etc…
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User Application
int main(…){ fd = open(/dev/iio:…); read(fd, buf, RCNT); … }
Example Device Driver: VGA/PGA Gain Control
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out_voltage1_hardwaregain
/sys/ bus/
iio/ iio:device0/
dev name out_voltage0_hardwaregain
/sys/bus/iio/iio:device0 # cat name ad8366-lpc /sys/bus/iio/iio:device0 # echo 6 > out_voltage1_hardwaregain /sys/bus/iio/iio:device0 # cat out_voltage1_hardwaregain 5.765000 dB
Device attributes Very convenient for configuring and
controlling devices using shell scripts Shell Commands:
AD8366
0.25dB Step Size 600MHz Bandwidth
SPI
AD9517-1 Multi-Output Clock Generator/ Distribution Control
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Outputs individually controllable Enable/disable Set/get frequency
IIO device driver, but also registers with the Linux clock consumer/producer framework
JESD204B Receiver Interface Linux Device Driver
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Ease of use Rx Eye Scan Nondestructive Implemented all in gates No runtime overhead
Direct read access to JESD204 link parameters (ILA)
Interface configuration via device tree
axi_jesd204b_rx4_0: axi-jesd204b-rx4@77a00000 { compatible = "xlnx,axi-jesd204b-rx4-1.00.a"; reg = < 0x77a00000 0x10000 >; jesd,lanesync_en; jesd,scramble_en; jesd,frames-per-multiframe = <32>; jesd,bytes-per-frame = <2>; clocks = <&clk_ad9517 0>; clock-names = "out0"; } ;
Xilinx LogiCORE™ IP JESD204 core
Analog Devices 2D Statistical Eye Scan Application Runs Natively on ZYNQ ZC706
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Graphical front end (GUI) JESD204B receiver interface Linux device driver
Data to VisualAnalog
VisualAnalog™ is a software package that combines a powerful set of simulation, product evaluation, and data analysis tools with a user-friendly graphical interface
Measure and visualize SNR, SFDR, THD, power,
etc.
IIO command client Control Linux IIO device
drivers and capture data via a TCP network connection
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Online Technical Support and Documentation
Analog Devices Wiki
This Wiki provides developers using Analog Devices products with: Software and documentation HDL interface code Software device drivers Reference project examples for
FPGA connectivity
It also contains user guides for some Analog Devices evaluation boards to help developers get up and running fast
http://wiki.analog.com/
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At Analog Devices, we recognize that our products are just one part of the design solution.
We are supporting seamless integration of ecosystems and tools by offering HDL interface code, device drivers, and reference project examples for FPGA connectivity.
This community is for the discussion of these reference designs.
http://ez.analog.com/community/fpga
52
FPGA Reference Designs Support Community
Analog Devices creates and maintains Linux device drivers for various ADI products.
Some software drivers are also available for ADI products that connect to microcontroller platforms without an OS.
The purpose of this community is to provide support for these drivers.
To see the list of available drivers supported, visit the Analog Devices Wiki
http://wiki.analog.com
http://ez.analog.com/community/ linux-device-drivers
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LINUX and Microcontroller Device Drivers Support Community
Design Resources Covered in this Session
Design Tools and Resources:
Ask technical questions and exchange ideas online in our EngineerZone™ Support Community Choose a technology area from the homepage: ez.analog.com
Access the Design Conference community here: www.analog.com/DC13community
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Name Description URL
VisualAnalog http://www.analog.com/visualanalog
Analog Devices Wiki
Software and documentation HDL interface code Software device drivers Reference project examples for FPGA connectivity
http://wiki.analog.com/
[other]
Tweet it out! @ADI_News #ADIDC13
Selection Table of Products Covered Today
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Part number Description AD-FMCJESDADC1-EBZ
FMC-based AD9250 evaluation board
CVT-ADC-FMC-INTPZ FMC to high speed ADC evaluation board adaptor
AD-DAC-FMC-ADP FMC to high speed DAC evaluation board adaptor
SDP-FMC-IB1Z SDP-to-FMC interposer board
Tweet it out! @ADI_News #ADIDC13
Visit the AD9250-FMC JESD204B Demo in the Exhibition Room AD9250-FMC250-EBZ card, connected to Xilinx development system
(ZC706), streaming data to VisualAnalog (over Ethernet), to measure converter performance (SNR, SFDR).
Alternatively data can be visualized on a Linux desktop environment. HDMI monitor, mouse, keyboard connected to the ZC706.
Concurrently measure and visualize the receiver eye margin on all JESD204B lanes.
GO to Xilinx to find out more on LogiCORE™ IP JESD204 core.
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This demo board is available for purchase: http://www.analog.com/DC13-hardware
What We Covered
Overview high speed converter interface styles and standards
Detailed look at the JESD204B interface standard
Analog Devices FPGA design support offerings
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