3D-DRESD ASIDA

POLITECNICO DI MILANO

Fabio Arlati – [email protected]

Francesco Caponio – [email protected]

Audio Signal Improvement on D740 Architecture

- Seconda Edizione della 3-Giorni DRESD -

24 Luglio 200724 Luglio 2007

Hotel Villa GinaHotel Villa Gina

GoglioGoglio

OutlineOutline

EnvironmentHardware

Diopsis 740 ArchitectureJTST Board Architecture

Spectral SubtractionSimple Microphone PreamplifierImplementationPossible Improvements

Direction Of ArrivalOur Microphone Array PreamplifierFuture Vision : SS + DOA

2

OutlineOutline

EnvironmentHardware




3

EnvironmentEnvironment

Annoying Elements:Background NoiseElectronic Devices InterferencesMicrophone SensitivitySource distance

How to solve that?

4

OutlineOutline

EnvironmentHardware




5

Diopsis 740 ArchitectureDiopsis 740 Architecture

Dual Core Architecture

Microcontroller: 32-bit RISC ARM7TDMIDSP: 40-bit floating point VLIW DSP, the ATMEL mAgic DSP

Technology: 0.18µ CMOS

ARM-DSP interface based on 1k x 40-bit dual-ported shared memory (PARM)

6

Diopsis 740 ArchitectureDiopsis 740 Architecture

7

Arm7TDMI32kB ARM

MemASB / APB Bridge

mAgic VLIW

DSP core

8kx128 bit

Program

Mem

Shared

Memory

Data Buffer 2 x 2k word

Double Bank, Double Port

ASB

Data / Program Bus Mux

Program Bus

Mux / Demux

Data Bus

Mux / Demux

Data Mem

2 x 6k x 40 bit

Double Bank

Double Port

SPI0

USART0

USART1

TIMER

Watchdog

PIO

PDC

ADDA

Clock Gen

IRQ Ctrl

SPI1

Diopsis 740 Architecture - ARMDiopsis 740 Architecture - ARM

Von Neumann Architecture3-stage pipeline

fetch, decode, execute32-bit Data Bus32-bit Address Bus37 32-bit registers32-bit ARM instruction set

32 kbytes of integrated SRAM

8

Diopsis 740 Architecture – mAgic DSPDiopsis 740 Architecture – mAgic DSP

1.0 GFLOPS @ 100 MHzIEEE-754 40 bit ext. precision Floating Point and 32-bit Integer

10 arithmetic operations per cycle

9

BenchmarkmAgic DSP Core

ADSP-21161

SHARC

TMS320C6711-

100

TMS320C6711-

1501024-point

complex Radix-4 FFT

59 usec 92 usec 144 usec 96 usec

Complex FIR filter (100

coefficients, 100 output samples)

139 usec 206 usec 215 usec 144 usec

Vector addition (100 vector) 0.11 usec 0.108 usec 0.108 usec Not

available

Vector dot product on real

vector(100 vector)

0.11 usec 0.056 usec 0.074 usec 0.050 usec

*

* Taken from ATMEL Diopsis Overview – July 2004

JTST Board ArchitectureJTST Board Architecture

JTST: Jig Test for D740Memories: SSRAM toward mAgic, FLASH and SRAM toward ARM4 Stereo Audio 20 bit CODECsSerial I/O:

1 USB 2.0 Full (12 Mbps) 2 RS232/LVTTL serial ports 2 SPI serial I/O lines

Reset Logic (Power ON, Push Button, WDG)IO connectors (USART, SPI, USB, PIO, AUDIO)25 MHz oscillatorConfiguration DIP SWITCH & Status 7-segment DisplayVoltage Regulators 5V/3.3V & 5V/1.8V

10

CLK

DIV

3.3V

LED

IRQ

BUTTON

PIO CONN

SRAM

ARM DATA L

128kx8

SRAM

ARM DATA H

128kx8

FLASH

ARM PRG

1Mx16

SSRAM

MAGIC

DATA L

128kx36

EXTCLK

CONN

DIP SWITCH

SPI-0 CONN

M-ICE JTAG CONN

Diopsis 740

PIO USARTs

RST

XMAXMD[15:0]

CLKs

CNTRLs

SPIsADDA

ARMD

PLL

ICEARMC

ARMA

XMD[55:40]

XMD[31:16]

XMD[71:56]

XMD[39:32]

XMD[79:72]

SSRAM

MAGIC

DATA H

128kx36SSRAM

MAGIC

DATA E

128kx36

USB

CNTRL

US

BC

ON

N

EX

T P

SU

C

ON

N

CO

DE

C

CO

DE

C

CO

DE

C

CO

DE

C

CLK

DIV

25

MHz

OSC

RS

232

BU

FF

RS

232

BU

FF

USART

0 CONN

USART

1 CONN

7-SEG DISPLAY

GND

GND

RESISTOR NETWORK

RESISTOR NETWORK

6 MHz

D-9 RS232

CONN

D-9 RS232

CONN

RST

BUTTONVREG 5-1.8

SPI-1 CONN

VREG

5-3.3

USB

LED

LED

BUFF

RST

BUFF

ADDA

BUFF

POW-ON RST

AUDIO

OUT

CONN

AUDIO

IN

CONN

AUDIO

OUT

CONN

AUDIO

IN

CONN

AUDIO

OUT

CONN

AUDIO

IN

CONN

AUDIO

OUT

CONN

AUDIO

IN

CONN

RE

SIS

TO

R

NE

TW

OR

K

RE

SIS

TO

R

NE

TW

OR

KR

ES

IST

OR

N

ET

WO

RK

RESISTOR NETWORKRESISTOR NETWORK

JP8 JP9

JP5

JP4

JP11

JP7

JP2

JP3

JP6

JP10

JP1

TP

5

TP2 TP1

TP

4

TP3

TP7

TP8

TP6

TP9

TP10

TP11

11


CLK

DIV

3.3V

LED

IRQ

BUTTON

PIO CONN

SRAM

ARM DATA L

128kx8

SRAM

ARM DATA H

128kx8

FLASH

ARM PRG

1Mx16

SSRAM

MAGIC

DATA L

128kx36

EXTCLK

CONN

DIP SWITCH

SPI-0 CONN

M-ICE JTAG CONN

Diopsis 740

PIO USARTs

RST

XMAXMD[15:0]

CLKs

CNTRLs

SPIsADDA

ARMD

PLL

ICEARMC

ARMA

XMD[55:40]

XMD[31:16]

XMD[71:56]

XMD[39:32]

XMD[79:72]

SSRAM

MAGIC

DATA H

128kx36SSRAM

MAGIC

DATA E

128kx36

USB

CNTRL

US

BC

ON

N

EX

T P

SU

C

ON

N

CO

DE

C

CO

DE

C

CO

DE

C

CO

DE

C

CLK

DIV

25

MHz

OSC

RS

232

BU

FF

RS

232

BU

FF

USART

0 CONN

USART

1 CONN

7-SEG DISPLAY

GND

GND

RESISTOR NETWORK

RESISTOR NETWORK

6 MHz

D-9 RS232

CONN

D-9 RS232

CONN

RST

BUTTONVREG 5-1.8

SPI-1 CONN

VREG

5-3.3

USB

LED

LED

BUFF

RST

BUFF

ADDA

BUFF

POW-ON RST

AUDIO

OUT

CONN

AUDIO

IN

CONN

AUDIO

OUT

CONN

AUDIO

IN

CONN

AUDIO

OUT

CONN

AUDIO

IN

CONN

AUDIO

OUT

CONN

AUDIO

IN

CONN

RE

SIS

TO

R

NE

TW

OR

K

RE

SIS

TO

R

NE

TW

OR

KR

ES

IST

OR

N

ET

WO

RK

RESISTOR NETWORKRESISTOR NETWORK

JP8 JP9

JP5

JP4

JP11

JP7

JP2

JP3

JP6

JP10

JP1

TP

5

TP2 TP1

TP

4

TP3

TP7

TP8

TP6

TP9

TP10

TP11


12

LINE

INLINE

OUTARMSYSTEM

mAgic

SYNC SRAM

mAc DATA/PROG

3 x 128k x 36

1728 kB

PIO

(use

r)

EXT

PSU

(5V)

USART

IF

32

bit

AR

M B

US

AUDIO

CODEC

FLASH

ARM/mAgic - PROG

2MB

SRAM

ARM - DATA

256 kB

Diopsis 740

V REG

5V/1.8V

RESET

LOGIC

3.3V

HW RST

EXT

CLK

3.3V

JTAG

ARM

ICE

ARM

CS0

Pllc

lkin

SPI

IF

2 x 2 x

PIO

(use

r)

25 MHz

OSC

ARM

CS1

ARM

CS2

ARM

CS340 bit mAgic BUS

PIO

(w

d_o

vf)

PIO

(ti

mer

in)

3 6

fpu_halt

fpu_ exc

fpu_ mode

PIO

(ext

irq

)

PIO

(fp

u s

irq

)

7

3

7

PIO

(ti

mer

out)

2

TP

Pllclkout

Plllock

L P

FILTER

Plll

ft

52

TP

WDG

RST1.8V

USB

DEVICE

CONTROLLER

USB

DEVICE

PORT

4 x4 x

•Goodlink

IRQV REG

5V/3.3V

Plle

n

JTST Operating SystemJTST Operating System

eCos (embedded Configurable operating system)Open-sourceHighly configurableApplication-Specific operating systemgdb compatible

RedBootCompactConfigurablePortableTerminal compatible

13

JTST DevelopmentJTST Development

MADE (Multicore Architecture Development Environment)

C language programmingARM and DSP code compiler and linkerCode Upload to the board via serial portCode DebugDiopsis 740 Simulator

14

OutlineOutline

EnvironmentHardware




15

Spectral SubtractionSpectral Subtraction

Hamming Windowing

16

X(f) = Y(f) - N(f) x(t) FFTy(t) = x(t) + n(t) IFFT

* =

Spectral SubtractionSpectral Subtraction

Fourier TransformSubtraction (HP: the noise is static & well known)Inverse Fourier TransformOverlap & Add

17

X(f) = Y(f) - N(f) x(t) FFTy(t) = x(t) + n(t) IFFT

Simple Microphone PreamplifierSimple Microphone Preamplifier

18

•Amplification 35 dB

•Flat frequency response from 20 Hz to 20 kHz

•Quite poor distortion performance

•Less than 10 mA consumption

•Electronics components cheaper

ImplementationImplementation

19

Implementation – DSPImplementation – DSP

20

Possible ImprovementsPossible Improvements

Automatic ThresholdHigher Sampling Frequency

Microphone Array Techniques

21

OutlineOutline

EnvironmentHardware




22

Direction Of ArrivalDirection Of Arrival

23

•Delay & Sum Beamformer (without postfilter)

OR

•DOA: position detection and postfiltering

GSM/SAT Triangulation Audio Triangulation

TriangulationTriangulation

24

Our Microphone Array PreamplifierOur Microphone Array Preamplifier

4 Stereo / 8 Mono Input & Output lines3.5 mm stereo Jack connectorsSeparate volume settings for each channelSingle Power supply

25

Future Vision : SS + DOAFuture Vision : SS + DOA

Known Integration Difficulties:Different frequency settingsLow-PARM Architecture

Possible Solutions:Multiple BoardsPC-Aided Computation

26