Performance-driven Analog Placement Considering Monotonic Current Paths

P. Wu, M. Lin, Y. Chen, B. Chou, T. Chen, T. Ho and B. Liu

Department of CS, NCKU, Tainan, Taiwan

ICCAD 2012

Outline

Introduction A Case Study Generation of Symmetry Islands using Slicing Trees Consideration of Monotonic Current Paths in Slicing

Trees The Proposed Algorithms Experimental Results Conclusions

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Introduction

The performance of analog circuits is very sensitive to the impact of layout-induced parasitics.

As a result, analog devices must be symmetrically and proximally placed for both parasitic matching and parasitic reduction.

The routing-induced parasitics on the current/signal paths usually have the greatest impact on analog circuit performance.

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Introduction

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Introduction

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Outline

Introduction A Case Study Generation of Symmetry Islands using Slicing Trees Consideration of Monotonic Current Paths in Slicing

Trees The Proposed Algorithms Experimental Results Conclusions

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A Case Study

Without considering monotonic current paths

Considering monotonic current paths

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A Case Study

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Outline

Introduction A Case Study Generation of Symmetry Islands using Slicing

Trees Consideration of Monotonic Current Paths in

Slicing Trees The Proposed Algorithms Experimental Results Conclusions

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Generation of Symmetry Islands using Slicing Trees

Slicing Tree

Floorplan Non-skewed slicing tree

Skewed slicing tree

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Symmetry-Island-Feasible Slicing Trees

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Symmetry-Island-Feasible Slicing Trees

To satisfy the feasible condition, the representative module of self-symmetry module must be on the left boundary of the right-half plane.

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Hierarchical Slicing Trees

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Topological Monotonic-Current-Path Constraint

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Geometrical Monotonic-Current-Path Constraint

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Geometrical Monotonic-Current-Path Constraint

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Outline

Introduction A Case Study Generation of Symmetry Islands using Slicing Trees Consideration of Monotonic Current Paths in Slicing

Trees The Proposed Algorithms Experimental Results Conclusions

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The Proposed Algorithms

Use Defer to explore the solution space under symmetry-island and monotonic-current-path consideration.

In the beginning of the algorithm, each symmetry island and non-symmetry module is represented by a leaf node in the hierarchical slicing tree.

Construct an initial hierarchical slicing tree by adjusting the order of the leaf nodes such that the topological current-path constraint is satisfied.

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Flow of DeFer

1. Partitioning

2. Combining

3. Back-Tracing

4. Swapping

5. Compacting

DeFer:Deferred Decision Making Enabled

Fixed-Outline Floorplanner

Dept. of Electrical & Computer Engineering

Iowa State UniversityAmes, IA 50010

Jackey Z. Yan Chris Chu

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1. Partitioning Step

20

100

55 45

35 2322

7 9 10 9 5 8

Recursively bi-partitioning Generate smaller subcircuits

Minimize interconnections among subcircuits

Generate high-level slicing tree structure

Until # of blocks in each subcircuits ≤ maxN

(maxN = 10 by default)

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2. Combining Step

Apply EP

Combine ( ) shape curves recursively 35

100

55 45

20 2322

7 9 10 9 5 8

Bo

tto

m-u

p

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3. Back-Tracing Step

Top

-do

wn

H

W

Pick one candidate

Fixed-outlineregion

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4. Swapping Step

Try to switch two subfloorplans (blocks) to improve WL

Flow:1. Rough Swapping

2. Detailed Swapping

3. Mirroring

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5. Compacting Step

Before

Compact towards the center Improve WL Not restricted to slicing floorplan

After

Multiple Placement Generation

After enumerative packing, fix the geometrical current-path constraint violation by module positioning for each packing solution.

After a point is selected, start the back-tracing step to obtain the corresponding slicing tree and the placement.

It is possible to generate multiple placements by choosing several points in the shape curve of the root node.

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Outline

Introduction A Case Study Generation of Symmetry Islands using Slicing Trees Consideration of Monotonic Current Paths in Slicing

Trees The Proposed Algorithms Experimental Results Conclusions

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Experimental Results

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Experimental Results

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Conclusions

This paper introduced the current-path constraints in analog placement.

They proposed a novel performance-driven analog placement flow based on the deterministic algorithm to explore the solution space under symmetry-island and monotonic-current-path constraints.

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