VLSI Lab manual PDF

VLSI LAB Dept. of ece

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Half adder :

Block Diagram:

a sum

b carry

Truth table:

Circuit diagram :

a b sum carry

0 0

0 1

1 0

1 1

0 0

1 0

1 0

0 1

HALF

ADDER


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AIM:

To design and simulate Half and Full adder using three differentarchitectures namely

i. Dataflowii. Behavioral

iii. Structural

SOFTWARE USED:

1.Xilinx ISE 9.2i

2.Model SIM SE6.5

THEORY:

HALF ADDER:

A combinational circuit that performs the addition of 2 bits is called a halfadder. This circuit accepts two binary inputs and produces two binary outputs.The input variables designate augends and addend bits; the output variablesdesignate sum and carry.

sum= ab.carry = ab.

FULLADDER:

A combinational circuit that performs the addition of 3 bits is called a fulladder. This circuit accepts 3 binary inputs and produces two binary outputs. Thetwo outputs are denoted by sum and carry.

sum= ab ccarry = ab + bc+ca

Ex No:1 1. HALF ADDER AND FULL ADDERDate: 18-12-13


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FULL ADDER :

Block Diagram:

Truth table:

Logic circuit:

a b c sum carry

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0

1

1

0

1

0

0

1

0

0

0

1

0

1

1

1

FULL

ADDER

b

a

c

sum

carry


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Procedure:

Create a new project by using file-new project. Name the new project and choose VHDL module. Choose the architecture and give the entity details. A sample module is generated .Additional required library files are

included. Architecture is automatically generated. Now the coding is done under the architecture part and at last give ‘end

architecture name’. The syntax is checked. Once the syntax is correct simulation is done. Graph is plotted for various combination of input values.

Source code :( HALF ADDER)

Data Flow Model :

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity Half_Adder isport(

a : in STD_LOGIC;b : in STD_LOGIC;sum : out STD_LOGIC;carry : out STD_LOGIC);

end Half_Adder;

architecture Half_Adder_arc of Half_Adder isbegin

sum <= a xor b;carry <= a and b;

end Half_Adder_arc;


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Behavioral Model:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ha behavioral is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

sum : out STD_LOGIC;

carry : out STD_LOGIC);

end ha behavioral;

architecture Behavioral of ha behavioral is

begin

process (a,b)

begin

if a='0' and b='0' then

sum<='0';carry<='0';

elsif a='0' and b='1' then






end if;

end process;

end Behavioral;


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Structural Model :

library IEEE;


entity ha structural is


b : in STD_LOGIC;



end ha structural;

architecture structure of ha structural is

component xor1 is

port(l, m: in std_logic;n:outstd_logic);

end component;

component and1 is

port(x, y: in std_logic;z:outstd_logic);

end component;

begin

x1:xor1 port map(a, b, sum);

x2:and1 port map(a, b, carry);

end structural;

Subroutine Program :

library IEEE;



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entity xor1 is

Port ( x1 : in STD_LOGIC;

y1 : in STD_LOGIC;

w1 : out STD_LOGIC);

end xor1;

architecture dataflow of xor1 is

begin

w1<=x1 xor y1;

end dataflow;

library IEEE;


entity and1 is


y2 : in STD_LOGIC;


end and1;

architecture dataflow of and1 is

begin

w2<=(x2 and y2);

end dataflow;


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Source code :(FULL ADDER)

Data flow :


entity Full_Adder_Design isport(

a : in STD_LOGIC;b : in STD_LOGIC;c : in STD_LOGIC;sum : out STD_LOGIC;carry : out STD_LOGIC);

end Full_Adder_Design;

architecture Full_Adder_Design_arc of Full_Adder_Design isbegin

sum <= a xor b xor c;carry <= (a and b) or

(b and c) or(c and a);

end Full_Adder_Design_arc;

Behavioral Model:

library IEEE;


use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fa is

Port ( a ,b,c : in STD_LOGIC;


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end fa;

architecture behavioral of fa is

begin

process (a,b,c)

begin

if a='0' and b='0' and c='0' then

sum<='0' ; carry<='0';

elsif a='0' and b='0' and c='1' then

sum<='1' ; carry<='0';


sum<='1' ; carry<='0';


sum<='0' ; carry<='1';


sum<='1' ; carry<='0';







end if;


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end process;

end behavioral;

Structural Model :

library IEEE;


entity fa is


b : in STD_LOGIC;

c : in STD_LOGIC;



end fa;

architecture structural of fa is

component xor1 is

port(x1,y1,z1:in std_logic;

w1:out std_logic);

end component;

component and1 is

port(x2,y2:in std_logic; w2:out std_logic);

end component;

component or1 is

port(x3,y3,z3:in std_logic; w3:out std_logic);

end component;


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signalx,y,z:std_logic;

begin

x1:xor1 port map(a,b,c,sum);

x2:and1 port map(a,b,x);

x3:and1 port map(b,c,y);

x4:and1 port map(c,a,z);

x5:or1 port map(x,y,z,carry);

end structural;

Subroutine Program :

library IEEE;


entity xor1 is


y1 : in STD_LOGIC;

z1:instd_logic;


end xor1;

architecture dataflow of xor1 is

begin

w1<=x1 xor y1 xor z1;

end dataflow;

library IEEE;


entity and1 is


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y2 : in STD_LOGIC;


end and1;

architecture dataflow of and1 is

begin

w2<=(x2 and y2);

end dataflow;

library IEEE;


entity or1 is


y3 : in STD_LOGIC;

z3 : in STD_LOGIC;


end or1;

architecture dataflow of or1 is

begin

w3<=x3 or y3 or z3;

end dataflow;


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Output Wave form of Full Adder :

Output Waveform of Half Adder :


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Result:

The design and simulation of the half adder and full adder using dataflow,behavioral, structural modeling has been performed using VHDL codeandsoftware mentioned.


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4*1 Multiplexer :

Block diagram :

Function Table :

F=a s0’s1’+b s0’s1+c s0s1’+d s0s1

Logic Diagram :


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AIM:

To design and simulate Multiplexer and Demultiplexer using threedifferent architectures namely


iii. Structural

SOFTWARE USED:

ISE Design Suite 14.2.

THEORY:

MULTIPLEXER:

It is combinational circuit that selects binary information from one of the manyinputs and directs it to a single output. The selection lines or controlled lines. Itis used as a data selector and parallel to serial convertor. In reference to theblock diagram a two bit binary code on the data select input will also allow thedata on the corresponding data input to pass through the data output.

OUTPUT :(F)=a s0’s1’+b s0’s1+c s0s1’+d s0s1

DEMULTIPLEXER:

This is a circuit that receives data from one line and transmits this informationon one of the 2n possible output lines. It performs reverse operation ofmultiplexer. The data input line goes to all of and gate. The two select linesenable only one gate at a time and the data appearing on the input will passthrough the selected gate.

OUTPUT: Y0=DS0’S1’; Y1=DS0’S1 ;Y2=DS0S1’ ; Y3= DS0S1;

Ex No:22. MULTIPLEXER AND DEMULTIPLEXERDate : 8-1-14


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1*4 Demultiplexer :

Block diagram :

Truth Table :

Y0=DS0’S1’; Y1=DS0’S1 ;Y2=DS0S1’ ; Y3= DS0S1;

Logic Diagram :


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Procedure :




Source code : (Multiplexer)

Data flow model :

library IEEE;


entity mux is


b : in STD_LOGIC;

c : in STD_LOGIC;

d : in STD_LOGIC;

s0 : in STD_LOGIC;

s1 : in STD_LOGIC;

y : out STD_LOGIC);

end mux;

architecture dataflow of mux is


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begin

y<=((a and (not s0) and (not s1)) or

(b and (not s0) and s1) or

(c and s0 and (not s1)) or

(d and s0 and s1));

end dataflow;

Behavioral Model:

library IEEE;


entity mux is


b : in STD_LOGIC;

c : in STD_LOGIC;

d : in STD_LOGIC;

s : in STD_LOGIC_VECTOR(0 to 1);

y : out STD_LOGIC);

end mux;

architecture behavioral of mux is

begin

process(a,b,c,d,s)

begin

case s is

when "00" => y<=a;


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when "01" => y<=b;

when "10"=> y<=c;

when others => y<=d;

end case;

end process;

end behavioral;

Structural Modeling :

library IEEE;use IEEE.std_logic_1164.all;

entity Structural_4x1 isport(s1,s2,d00,d01,d10,d11 : in std_logic;z_out : out std_logic);end Structural_4x1;

architecture arc of Structural_4x1 iscomponent muxport(sx1,sx2,d0,d1 : in std_logic;z : out std_logic);end component;

component or_2port(a,b : in std_logic;c : out std_logic);end component;

signal intr1, intr2, intr3, intr4 : std_logic;beginmux1 : mux port map(s1,s2,d00,d01,intr1);mux2 : mux port map(not s1,s2, d10,d11,intr2);o1 : or_2 port map(intr1, intr2, z_out);end arc;


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Subroutine Program for 4*1 Multiplexer:

library ieee;use ieee.std_logic_1164.all;

entity mux isport(sx1,sx2,d0,d1 :in std_logic;z1,z2: inout std_logic;z: out std_logic);end mux;

architecture arc of mux isbeginz1 <= d0 and (not sx1) and (not sx2);z2 <= (d1 and (not sx1) and sx2);z<= z1 or z2;end arc;

entity or_2 isport(a,b : in bit;c : out bit);end or_2;architecture arc of or_2 isbeginc<=a or b;end arc;

1*4 Demultiplexer :

SourceCode :

Data flow Model :

library IEEE;


entity dmux is



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s0 : in STD_LOGIC;

s1 : in STD_LOGIC;

y : out STD_LOGIC_VECTOR (0 TO 3));

end data;

architecture dataflow of dmux is

begin

y(0)<= a and (not s0) and (not s1);

y(1)<= a and (not s0) and (s1);

y(2)<= a and (s0) and (not s1);

y(3)<= a and (s0) and (s1);

end dataflow;

Behavioral Model :

library IEEE;


entity dmux is

Port ( s0 : in STD_LOGIC;

s1 : in STD_LOGIC;

a : in STD_LOGIC;

y : out STD_LOGIC_VECTOR (0 to 3));

end dmux;

architecture Behavioral of dmux is

begin

process(a,s0,s1)


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begin

if a='1' and s0='0' and s1='0' then

y(0)<='1';y(1)<='0';y(2)<='0';y(3)<='0';

elsif a='1' and s0='0' and s1='1' then

y(0)<='0';y(1)<='1';y(2)<='0';y(3)<='0';


y(0)<='0';y(1)<='0';y(2)<='1';y(3)<='0';


y(0)<='0';y(1)<='0';y(2)<='0';y(3)<='1';

end if;

end process;

end Behavioral;

Structural Modeling:

library IEEE;use IEEE.std_logic_1164.all;

entity Structural_1x4 isport(s1,s2,data_in : in std_logic;d1,d2,d3,d4 : out std_logic);end Structural_1x4;

architecture arc of Structural_1x4 iscomponent dmuxport(sx1,sx2,d : in std_logic;z1,z2 : out std_logic);end component;begin


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dmux1 : dmux port map(s1,s2,data_in,d1,d2);dmux2 : dmux port map(not s1,s2,data_in,d3,d4);end arc;

Subroutine Program for 1*4 Demultiplexer:


entity dmux isport(sx1,sx2,d :in std_logic;z1,z2: out std_logic);end dmux;

architecture arc of dmux isbeginz1 <= d and (not sx1) and (not sx2);z2 <= d and (not sx1) and sx2;end arc;


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Output Waveform of 4*1 Multiplexer :

Output Waveform of 1*4 Demultiplexer :


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Result:

The design and simulation of the multiplexer and demultiplexer usingdataflow, behavioral modeling and Structural modeling has beenperformed using VHDL code and software mentioned.


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AIM:

To design and simulate 3x8 Decoder and 2 Bit Magnitude Comparatorusing three different architectures namely


iii. Structural

SOFTWARE USED:

1.Xilinx ISE 9.2i

2.Model SIM SE6.5

THEORY :

3x8 DECODER

A decoder is a device which does the reverse operation of an encoder, undoingthe encoding so that the original information can be retrieved. The same methodused to encode is usually just reversed in order to decode. It is a combinationalcircuit that converts binary information from n input lines to a maximum of 2n

unique output lines.

A 3 to 8 decoder consists of three inputs and eight outputs.

Application :

A simple CPU with 8 registers may use 3-to-8 logic decoders inside theinstruction decoder to select two source registers of the register file to feed intothe ALU as well as the destination register to accept the output of the ALU. Atypical CPU instruction decoder also includes several other things.

Ex No: 33. 3x8 Decoder and 2 Bit Magnitude ComparatorDate :22-1-14


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3X8 DECODER

Block Diagram :

Truth Table :

F0=X’Y’Z’; F6=XYZ’;

F1=X’Y’Z; F7=XYZ;

F2=X’YZ’;

F3=X’YZ;

F4=XY’Z’;

F5=XY’Z;

Logic Circuit Diagram :

X Y Z F0 F1 F2 F3 F4 F5 F6 F70 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1


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2Bit Magnitude Comparator :

Magnitude comparator is a combinational circuit that compares two numbersand determines their relative magnitude.

For a 2-bit comparator we have four inputs A1A0 and B1B0 and three outputs:

E (is 1 if two numbers are equal)G (is 1 when A > B) andL (is 1 when A < B)

Output Expressions :

f(A>B) = A1B1‘+ (A1 + B1’) A0B0’ = A1B1‘+ A0 B1’B0’+ A1A0B0’

f(A=B)=A1’A0’B1’B0’+A1’A0B1’B0+A1A0’B1B0+ A1A0B1B0= (A1’B1’+A1B1)(A0’B0’+A0B0)

f(A<B)=A1’B1+A0’B0A1’B1’+A0’B0A1B1

= A1’B1+A0’B0(A1’B1’+A1B1)

Procedure:





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2 BIT MAGNITUDE COMPARATORBlock Diagram :

Truth Table :

Logic Circuit Diagram :


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Source Code:(3x8 Decoder:)

Data Flow Model:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity Decoderdataflow isPort ( a : in STD_LOGIC;

b : in STD_LOGIC;c : in STD_LOGIC;d0 : out STD_LOGIC;d1 : out STD_LOGIC;d2 : out STD_LOGIC;d3 : out STD_LOGIC;d4 : out STD_LOGIC;d5 : out STD_LOGIC;d6 : out STD_LOGIC;d7 : out STD_LOGIC);

end Decoderdataflow;

architecture Dataflow ofDecoderdataflow is

begind0<= (not a) and (not b) and (not c);d1<= (not a) and (not b) and c;d2<= (not a) and b and (not c);d3<= (not a) and b and c;d4<= a and (not b) and (not c);d5<= a and (not b) and c;d6<= a and b and (not c);d7<= a and b and c;end Dataflow;

Behavioral Modeling :


entity Decoder isPort ( din : in STD_LOGIC_VECTOR (2 downto 0);

dout : out STD_LOGIC_VECTOR (7 downto 0));end Decoder;


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architecture Behavioral of Decoder is

beginprocess(din)

beginif (din="000") then

dout <= "10000000";elsif (din="001") then






dout <= "00000010";else dout <= "00000001";

end if;end process;

end Behavioral;



entity dec3x8 isport(a,b,c,e:inbit; z0,z1,z2,z3,z4,z5,z6,z7:out bit);end dec3x8;

architecture structural of dec3x8 is

component and4 isport(g,h,i,j:inbit;k:out bit);end component;


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component not1 isport(a:in bit; b:out bit);end component;

signal s1,s2,s3:bit;

beginx1:not1 port map(a,s1);x2:not1 port map(b,s2);x3:not1 port map(c,s3);x4:and4 port map(s1,s2,s3,e,z0);x5:and4 port map(s1,s2,c,e,z1);x6:and4 port map(s1,b,s3,e,z2);x7:and4 port map(s1,b,c,e,z3);x8:and4 port map(a,s2,s3,e,z4);x9:and4 port map(a,s2,c,e,z5);x10:and4 port map(a,b,s3,e,z6);x11:and4 port map(a,b,c,e,z7);

end structural;

SubProgram for not1 :

library IEEE;


entity not1 is


b : out STD_LOGIC);

end not1;

architecture Structural of not1 is

begin

b<=not a;

end Structural;


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SubProgram for and4 :

library IEEE;


entity and4 is

Port ( g : in STD_LOGIC;

h : in STD_LOGIC;

i : in STD_LOGIC;

j : in STD_LOGIC;

k : out STD_LOGIC);

end and4;

architecture Structural of and4 is

begin

k<=g and h and i and j;

end Structural;

Source Code :(2 Bit Magnitude Comparator)

Data Flow Modeling:


entity comparator_2bit isport(

a : in STD_LOGIC_VECTOR(1 downto 0);b : in STD_LOGIC_VECTOR(1 downto 0);equal : out STD_LOGIC;greater : out STD_LOGIC;lower : out STD_LOGIC);


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end comparator_2bit;

architecture Dataflow of comparator_2bit isbeginequal <= '1' when (a=b) else '0';greater <= '1' when (a<b) else '0';lower <= '1' when (a>b) else '0';

end Dataflow;

Behavioral Modeling:

library IEEE;


entity comparator_2bit is

Port ( a : in STD_LOGIC_VECTOR:="00";

b : in STD_LOGIC_VECTOR:="00";

equal : out STD_LOGIC;

greater : out STD_LOGIC;

lesser : out STD_LOGIC);

end comparator_2bit;

architecture Behavioral of comparator_2bit is

begin

process(a,b)

begin

if (a=b)then


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equal<='1';

greater<='0';

lesser<='0';

elsif(a>b)then

equal<='0';

greater<='1';

lesser<='0';

elsif(a<b)then

equal<='0';

greater<='0';

lesser<='1';

end if;

end process;

end Behavioral;


library IEEE;


entity comparator2bit is

Port ( a1 : in STD_LOGIC;

a0 : in STD_LOGIC;


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b1 : in STD_LOGIC;

b0 : in STD_LOGIC;

x : out STD_LOGIC;

y : out STD_LOGIC;

z : out STD_LOGIC);

end comparator2bit;

architecture Structural of comparator2bit is

component and1 is

port(c,d:in std_logic;

e:out std_logic);

end component;

component and6 is

port(f,g,h:in std_logic;

i:out std_logic);

end component;

component or1 is

port(j,k,l:in std_logic;

m:out std_logic);

end component;

component xnor1 is

port(n,o:in std_logic;

p:out std_logic);

end component;


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component not1 is

port(q:in std_logic;

r:out std_logic);

end component;

signal s,t,u,s1,t1,u1,s2,t2,s3,t3,u3,v3:std_logic;

begin

TT1:not1 port map (a1,s3);

TT2:not1 port map (a0,t3);

TT3:not1 port map (b1,u3);

T4:not1 port map (b0,v3);

T5:and1 port map (a1,u3,s);

T6:and6 port map (a0,u3,v3,t);

T7:and6 port map (a0,a1,v3,u);

T8:or1 port map (s,t,u,x);

T9:and1 port map (s3,b1,s1);

T10:and6 port map (b0,s3,t3,t1);

T11:and6 port map (b0,b1,t3,u1);

T12:or1 port map (s1,t1,u1,y);

T13:xnor1 port map (a1,b1,s2);

T14:xnor1 port map (a0,b0,t2);

T15:and1 port map (s2,t2,z);

end Structural;


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Subprogram for not1:


entity not1 isPort ( q : in STD_LOGIC;

r : out STD_LOGIC);end not1;

architecture Structural of not1 isbeginr<=not q;end Structural;

Subprogram for and1:


entity and1 isPort ( c : in STD_LOGIC;

d : in STD_LOGIC;e : out STD_LOGIC);

end and1;

architecture Structural of and1 isbegine<=c and d;end Structural;

Subprogram for and6:


entity and6 isPort ( f : in STD_LOGIC;

g : in STD_LOGIC;h : in STD_LOGIC;i : out STD_LOGIC);

end and6;


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architecture Structural of and6 isbegini<=f and g and h;end Structural;

Subprogram for or1:


entity or1 isPort ( j : in STD_LOGIC;

k : in STD_LOGIC;l : in STD_LOGIC;m : out STD_LOGIC);

end or1;

architecture Structural of or1 isbeginm<=j or k or l;end Structural;

Subprogram for xnor1 :


entity xnor1 isPort ( n : in STD_LOGIC;

o : in STD_LOGIC;p : out STD_LOGIC);

end xnor1;

architecture Structural of xnor1 isbeginp<=n xnor o;end Structural;


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2BIT Magnitude Comparator :

Output:

3x8Decoder:

OUTPUT:


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Result:

The design and simulation of the 3x8 Decoder and 2Bit Magnitude Comparatorusing dataflow,behavioral,structural modeling has been performed using VHDLcode and software mentioned.


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AIM:

To design and simulate Arithmetic and Logic Unit using architecturenamely

i. Behavioral Modeling

SOFTWARE USED:

1.Xilinx ISE 14.7

2.ISIM Simulator

THEORY :

An arithmetic and logic unit (ALU) is a digital circuit thatperforms integer arithmetic and logical operations. The ALU is a fundamentalbuilding block of the central processing unitof a computer, and even thesimplest microprocessors contain one for purposes such as maintaining timers.The processors found inside modern CPUs and graphics processing units(GPUs) accommodate very powerful and very complex ALUs; a singlecomponent may contain a number of ALUs.

Procedure:




Ex No: 4 4. ARITHMETIC AND LOGIC UNITDate: 29-1-14


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ARITHMETIC AND LOGIC UNIT

Block Diagram :


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SOURCE CODE :

library IEEE;




entity aluarith is

Port ( a,b : in INTEGER;

x,y : in STD_LOGIC_VECTOR(7 DOWNTO 0);

x1 : in BIT_VECTOR(7 DOWNTO 0);

asel : in STD_LOGIC_VECTOR(1 DOWNTO 0);

lsel : in STD_LOGIC_VECTOR(2 DOWNTO 0);

l1sel : in STD_LOGIC_VECTOR(2 DOWNTO 0);

aout : out INTEGER;

lout : out STD_LOGIC_VECTOR(7 DOWNTO 0);

l1out : out BIT_VECTOR(7 DOWNTO 0));

end aluarith;

architecture Behavioral of aluarith is

begin

process(a,b,asel)

begin

case asel is

when "00"=> aout<= a+b;


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when "01"=> aout<= a-b;

when "10"=> aout<= a*b;

when "11"=> aout<= a/b;

when others=>aout<= a-b;

end case;

end process;

process(x,y,lsel)

begin

case lsel is

when "000"=> lout <= "00000000";

when "001"=> lout <= x or y ;

when "010"=> lout <= x nor y;

when "011"=> lout <= x xor y;

when "100"=> lout <= x xnor y;

when "101"=> lout <= x nand y;

when "110"=> lout <= x and y;

when "111"=> lout <= not y;

when others=>lout<="--------";

end case;

end process;


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process(x1,l1sel)

begin

case l1sel is

when "000"=> l1out <= "00000000";

when "001"=> l1out <= x1 SLA 2;

when "010"=> l1out <= x1 SRA 2;

when "011"=> l1out <= x1 SLL 2;

when "100"=> l1out <= x1 SRL 2;

when "101"=> l1out <= x1 ROL 2;

when "110"=> l1out <= x1 ROR 2;

when "111"=> l1out <= "00000000";

when others=>l1out<="00000000";

end case;

end process;

end Behavioral;


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OUTPUT WAVEFORM


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Result:

The design and simulation of the Arithmetic and logic unit (ALU) usingbehavioral modeling has been performed using VHDL codeand simulatedthrough software mentioned.


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AIM:

To design and simulate T-FlipFlop using architectures namely

i. Dataflow Modeling.ii. Behavioral Modeling.

iii. Structural Modeling.

SOFTWARE USED:

1.Xilinx ISE 14.7

2.ISIM Simulator.

Theory:

T Flip-Flop:

The T FF is a single input version of the JK FF, where both J and J inputs

are tied together. This FF has the ability to toggle regardless of its present state

when the clock pulse occurs and while the T input is 1.

Characteristic Equation: Qt+1=Qt xor t

Procedure:




Ex No: 5 5.DESIGN AND SIMULATION OF T-FLIPFLOPDate: 5-2-14


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T-FLIPFLOP:

Block Diagram:

Characteristic Table :

Qt+1=Qt xor t

Circuit Diagram :

Q T Q(t+1)

0 0

0 1

1 0

1 1

0

1

1

0


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Source code :

Dataflow Modeling

library IEEE;

Use IEEE.STD_LOGIC_1164.All;

entity tff is

Port (t : in std_logic;

clk : in std_logic;

q : in out std_logic;

qbar : in out std_logic);

end tff;

architecture dataflow of tff is

signal s1,s2:std_ logic;

begin

s1<=t and clk and q;

s2<=t and clk and qbar;

q<=s1 nor qbar;

qbar<=s2 nor q;

end dataflow;

Behavioral Modeling :

library IEEE;



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entity tff is


clk : in std_logic;



end tff;

architecture Behavioral of tff is

begin

Process (t,clk,)

begin

if (clk’event and clk =’1’)then

if(t=’0’)thenq<=q;

qbar<=qbar;elseq<=not q ;qbar<=not qbar;

end if;

elseq<=q;qbar<=qbar;

end if;

end process;

end Behavioral;


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library IEEE;


entity tff is


clk : in std_logic;



end tff;

architecture structural of tff is

signal s1,s2 : std_ logic;

component nor2 is

port (a,b: in std_logic;

c : out std_logic);

end component;

component and3 is

port (a,b,c: in std_logic;

d : out std_logic);

end component;

begin

x1: and3 port map(t,clk,q,s1);


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x2: and3 port map(t,clk,qbar,s2);

x3: nor2 port map(s1,qbar,q);

x4: nor2 port map(s2,q,qbar);

end structural;

Subprogram for nor2 :

library IEEE;




entity nor2 is


b : in STD_LOGIC;

c : out STD_LOGIC);

end nor2;

architecture data_flow of nor2 is

begin

c<=a nor b;

end data_flow;

Subprogram for and3 :


entity and3 is


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Port ( a: in STD_LOGIC;b : in STD_LOGIC;c : in STD_LOGIC;d : out STD_LOGIC);

end and3;

architecture Dataflow of and3 is

begind<=a and b and c;end Dataflow;


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OUTPUT WAVEFORM :


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Result:

The design and simulation of the T-flipflop using dataflow,behavioral,structural modeling has been performed using VHDL codeand softwarementioned.


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AIM:

To design and simulate counters [updown,ring & mod10] using behavioralmodeling in VHDL code.

SOFTWARE USED:

Xilinx ISE 14.7

THEORY:

UPDOWN COUNTER

A counter that can change state in either direction, under the control of an up ordown selector input, is known as an up/down counter. When the selector is inthe up state, the counter increments its value. When the selector is in the downstate, the counter decrements the count.

RING COUNTER

A ring counter is a circular shift register which is initiated such that only one ofits flip-flops is the state one while others are in their zero states.

A ring counter is a Shift Register (a cascade connection of flip-flops) with theoutput of the last one connected to the input of the first, that is, in a ring.Typically, a pattern consisting of a single bit is circulated so the state repeatsevery n clock cycles if n flip-flops are used. It can be used as a cycle counter ofn states.

MOD10 COUNTER

A MOD 10 counter has 10 possible states. In other words, it counts from 0 to 9and rolls over. The decade counter is also known as a mod-counter when itcounts to ten (0, 1, 2, 3, 4, 5, 6, 7, 8, 9). A Mod Counter that counts to 64 stopsat 63 because 0 counts as a valid digit.

Ex No: 6 6.DESIGN AND SIMULATION OF COUNTERSDate: 19-2-14


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UP-DOWN COUNTER:

TRUTH TABLE:

Present State State When Count = 1 State When Count = 00000 0001 11110001 0010 00000010 0011 00010011 0100 00100100 0101 00110101 0110 01000110 0111 01010111 1000 01101000 1001 01111001 1010 10001010 1011 10011011 1100 10101100 1101 10111101 1110 11001110 1111 11011111 0000 1110


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PROCEDURE :

Open a new project from Xilinx ISE9.2i,a project navigation softwaretool.

Select a source file name as VHDL module and define VHDL sourcesrespectively, the input and output ports.

Enter the program and save the file. Check the syntax option from synthesis to know the error. Go for the synthesis XST to view RTL schematic report (new list). Launch Modelsim simulator from design entry utilities and enter the

value of input ports.

SOURCE CODES :

UP DOWN COUNTER(Behavioral)

library IEEE;




entity updowncounter is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

count : in STD_LOGIC;

s : inout STD_LOGIC_VECTOR (3 downto 0));

end updowncounter;

architecture Behavioral of updowncounter is


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RING COUNTER :

Block Diagram :

Truth Table :

Reset Present State Next State1 000 000000010 001 000000100 010 000001000 011 000010000 100 000100000 101 001000000 110 010000000 111 10000000


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begin

process(clk,reset,count)

begin

if reset='1' then s<="0000";

elsif count='1' and rising_edge(clk) then s<=s+1;

elsif count='0' and rising_edge(clk) then s<=s-1;

end if;

end process;

end Behavioral;

RING COUNTER(Behavioral)

library IEEE;




entity ring_ctr is

Port ( clk,reset : in STD_LOGIC;

q : inout STD_LOGIC_VECTOR (0 to 1);

s : out STD_LOGIC_VECTOR (0 to 3));

end ring_ctr;

architecture Behavioral of ring_ctr is

begin


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MOD 10 COUNTER:

Block Diagram :

Truth Table :

Reset Present State Next State1 0000 00010 0001 00100 0010 00110 0011 01000 0100 01010 0101 01100 0110 01110 0111 10000 1000 10010 1001 10100 1010 0000


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process(clk,reset,q)

begin

if reset='1' then q<="00";

elsif rising_edge(clk) then q<=q+1;

end if;

case q is

when "00"=>s<="0001";

when "01"=>s<="0010";

when "10"=>s<="0100";

when others=>s<="1000";

end case;

end process;

end Behavioral;

MOD-10 COUNTER(Behavioral)

library IEEE;




entity mod_ctr is

Port ( clk,reset: in STD_LOGIC;

q : inout STD_LOGIC_VECTOR(3 downto 0));

end mod_ctr;


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architecture Behavioral of mod_ctr is

begin

process(clk,reset)

begin

if reset='1' then q<="0000";

elsif rising_edge(clk) then q<=q+1;

if q="1001" then q<="0000";

end if;

end if;

end process;

end Behavioral;


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OUTPUT WAVEFORMS:

UP-DOWN COUNTER

RING COUNTER :

MODULO-10 COUNTER :


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RESULT :Thus the design and simulation of all the counters using behavioral modeling

are done and the outputs are verified.


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AIM :

To design and simulate a static random access memory using behavioralmodeling in VHDL.

SOFTWARE USED:

Xilinx ISE 14.7i

THEORY:

Static random-access memory (SRAM) is a type of semiconductor memory thatuses bistable latching circuitry to store each bit. The term static differentiates itfrom dynamic RAM (DRAM) which must be periodically refreshed. SRAMexhibits data remanence, but it is still volatile in the conventional sense that datais eventually lost when the memory is not powered.

Procedure :

Open XilinxISE projectnavigatorwindow.

Close allprojects whichareopen.

Create anew project.

Select a project title and check next.

Select newsource and VHDLmodule.

Select sourcename andclick next till finish.

Writethe program with the correspondingmodellingtechnique.

Check the syntaxand correct theerrors.

Simulateitand forceinput values.

Observethewaveforms

Ex No: 7 7.DESIGN AND SIMULATION OF STATIC RAMDate: 5-3-14


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SRAM :

Logic Diagram :


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SRAM :

Logic Diagram :


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SRAM :

Logic Diagram :


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SOURCE CODE:

SRAM(Behavioral modeling)

library IEEE;


use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity sram is

generic(width: integer :=4;

depth:integer:=4;

addr:integer:=2);

Port ( clk : in STD_LOGIC;

en : in STD_LOGIC;

rd : in STD_LOGIC;

wr : in STD_LOGIC;

rdaddr : in STD_LOGIC_VECTOR (addr-1 downto 0);

wraadr : in STD_LOGIC_VECTOR (addr-1 downto 0);

datain : in STD_LOGIC_VECTOR (width-1 downto 0);

dataout : out STD_LOGIC_VECTOR (width-1 downto 0));

end sram;

architecture Behavioral of sram is

type rmtyp is array (0 to depth-1) of std_logic_vector(width-1 downto 0) ;

signal tmpram:rmtyp;


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begin

process(clk,rd)

begin

if(clk' event and clk='1') then

if en='1' then

if rd='1' then

dataout<=tmpram(conv_integer(rdaddr));

else

dataout<=(dataout' range =>'Z');

end if;

end if;

end if;

end process;

process(clk,wr)

begin

if(clk' event and clk='1') then

if en='1' then

if wr='1' then

tmpram(conv_integer(wraadr))<=datain;

end if;

end if;

end if;

end process;

end Behavioral;


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OUTPUT WAVEFORM :


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Result:

Thus the static random access memory was successfullydesigned,simulated and the output was verified .


108 UR11EC098

CIRCUIT DIAGRAM OF CMOS INVERTER:

CODING:(CMOS INVERTER)


109 UR11EC098

AIM:

To design and simulate CMOS inverter, CMOS NAND and CMOS NOR gateusing TANNER EDA.

SOFTWARE USED:

Tanner EDA 7.0

THEORY:

Cmos inverter:

A CMOS inverter contains a PMOS and a NMOS transistor connected at the drainand gate terminals, a supply voltage VDD at the PMOS source terminal, and aground connected at the NMOS source terminal, where VIN is connected to thegate terminals and VOUT is connected to the drain terminals. It is important tonotice that the CMOS does not contain any resistors, which makes it more powerefficient that a regular resistor-MOSFET inverter.As the voltage at the input of theCMOS device varies between 0 and 5 volts, the state of the NMOS and PMOSvaries accordingly. If we model each transistor as a simple switch activated byVIN, the inverter’s operations can be seen very easily.

Cmos NAND logic:

Cmos NAND logic consists of 2 n-MOS in parallel .Transistor sizing is doneaccording to the RC modelling to minimise the delay.If both inputs are highthen n-MOS transistors will conduct but p-MOS transistors will not.Aconductive path is established between the output and GND,making the outputlow,if any of the input is low,one of the n-MOS will not conduct and p-MOSwill and output is pulled to Vdd.

Cmos NOR logic:

CMOS NOR logic consists of two n-MOS transistors in parallel and two

p-MOS transistors in series.If both the inputs are high then n-MOS transistors

will conduct, a conductive path is established between the output and GND,

and output is pulled down to GND. If any of the inputs are low, output is low.If

Ex No: 8 8.DESIGN AND SIMULATION OF CMOS LOGIC GATESDate: 05-3-14


110 UR11EC098

CIRCUIT DIAGRAM FOR CMOS NAND GATE:

CODING:


111 UR11EC098

any of the inputs are low, output is low.If both inputs are low then output ishigh.

PROCEDURE:

1. Open the schematic editor(S-edit) from the tanner EDA tool.2. Get the required components from the symbol browser and design given

circuit using the S-edit.3. Give the external supply from the library to the circuit.4. Write the program in the T-edit and run the simulation and check for errors.5. Remove all the errors and again write the program in the T-edit and run.6. Output waveform is viewed in the waveform viewer.7. Get the net list and verify the output.

NETLIST:(CMOS INVERTER)

TSPICE - Tanner SPICE

Version 7.10

Copyright (c) 1993-2001 Tanner Research, Inc.

Parsing "C:\Users\KARUNYA\Desktop\Module0.sp"

Device and node counts:

MOSFETs - 2 MOSFET geometries - 2

BJTs - 0 JFETs - 0

MESFETs - 0 Diodes - 0

Capacitors - 0 Resistors - 0

Inductors - 0 Mutual inductors - 0

Transmission lines - 0 Coupled transmission lines - 0

Voltage sources - 2 Current sources - 0

VCVS - 0 VCCS - 0


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CIRCUIT DIAGRAM FOR CMOS NOR GATE:

CODING:


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CCVS - 0 CCCS - 0

V-control switch - 0 I-control switch - 0

Macro devices - 0 Functional model instances - 0

Subcircuits - 0 Subcircuit instances - 0

Independent nodes - 1 Boundary nodes - 3

Total nodes - 4

Parsing 0.01 seconds

Setup 0.01 seconds

DC operating point 0.00 seconds

Transient Analysis 0.00 seconds

-----------------------------------------

Total 0.02 seconds

NETLIST:(CMOS NAND )

NETLIST:


Version 7.10




BJTs - 0 JFETs - 0






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OUTPUT: NOT WAVEFORM


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VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 7

Warning T-SPICE : The vrange voltage range limit (5.5) for diode tables has been exceeded.

Warning T-SPICE : The vrange voltage range limit (5.5) for MOSFET tables has beenexceeded.

Warning T-SPICE : The vrange voltage range limit should be set to

at least 7.63709 for best accuracy and performance.


Setup 0.00 seconds



-----------------------------------------

Total 0.01 seconds

NETLIST:(CMOS NOR)

NETLIST:


Version 7.10



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OUTPUT: NAND WAVEFORM


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Parsing "F:\Softwares\Tanner\S-Edit\Module0.sp"



BJTs - 0 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 6


Setup 0.00 seconds



-----------------------------------------

Total 0.00 seconds


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OUTPUT: NOR WAVEFORM


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RESULT:

The design and simulation of a CMOS inverter,CMOS NAND and CMOSNOR logic has been verified using tanner tools.


120 UR11EC098

CMOS HALF ADDER:

LOGIC DIAGRAM:

NETLIST:


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CMOS HALF ADDER:

LOGIC DIAGRAM:

NETLIST:


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CMOS HALF ADDER:

LOGIC DIAGRAM:

NETLIST:


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AIM:

To design and simulate CMOS half-adder and full-adder using tanner EDA.

SOFTWARE USED:

Tanner EDA 7.0

THEORY:

HALF ADDER:

A combinational circuit that performs the addition of 2 bits is called a halfadder. This circuit accepts two binary inputs and produces two binary outputs.The input variables designate augends and addend bits; the output variablesdesignate sum and carry.

The simplified SOP terms are

sum = a’b+ab’carry = ab

FULLADDER:

A combinational circuit that performs the addition of 3 bits is called a fulladder. This circuit accepts 3 binary inputs and produces two binary outputs. Thetwo outputs are denoted by sum and carry.

The simplified SOP terms are

sum= abc+a’b’c+ab’c’+a’bc’carry = ab + bc+ca

PROCEDURE:

1.Open the schematic editor(S-edit) from the tanner EDA tool.2.Get the required components from the symbol browser and design givencircuit using the S-edit.

Ex No: 9 9.DESIGN AND SIMULATION OF CMOS HALF AND FULLADDERSDate: 12-3-14


122 UR11EC098

OUTPUT: CMOS HALF ADDER:


123 UR11EC098

3.Give the external supply from the library to the circuit.4.Write the program in the T-edit and run the simulation and check for errors.5.Remove all the errors and again write the program in the T-edit and run.6.Output waveform is viewed in the waveform viewer.7.Get the net list and verify the output.

CMOS HALF ADDER:

TSPICE CODE:

* Waveform probing commands

.probe

.options probefilename="ADDER.dat"

+ probesdbfile="C:\Users\Lab-4\Desktop\ADDER.sdb"

+ probetopmodule="Module0"

* Main circuit: Module0

M1 Bbar B Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u


M3 Abar A Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M4 Ybar Abar N5 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M5 N5 B Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M6 N2 A Ybar Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M7 Gnd Bbar N2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M8 sum Ybar Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M9 carry Abar Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M10 Gnd Bbar carry Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M11 Bbar B Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M12 N3 Abar Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M13 Abar A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M14 Ybar A N3 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M15 Vdd B N3 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M16 N3 Bbar Ybar Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u


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CMOS FULL ADDER:

LOGIC DIAGRAM:

NETLIST:


124 UR11EC098

CMOS FULL ADDER:

LOGIC DIAGRAM:

NETLIST:


124 UR11EC098

CMOS FULL ADDER:

LOGIC DIAGRAM:

NETLIST:


125 UR11EC098

M17 sum Ybar Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M18 N6 Abar Vdd N7 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M19 carry Bbar N6 N7 PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

v20 Vdd Gnd 5.0

.model pmos pmos

.model nmos nmos

v1 A gnd BIT ({110011})

v2 B gnd BIT ({100001})

.tran 4n 400n

.print A B sum carry

* End of main circuit: Module0

CMOS FULL ADDER:

TSPICE CODE:

* Waveform probing commands

.probe

.options probefilename="full.dat"

+ probesdbfile="C:\Users\karunya\Documents\Tanner\S-Edit\full.sdb"

+ probetopmodule="Module0"

* Main circuit: Module0

M1 S1bar S1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M2 S2 Cbar N9 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M3 N7 C S2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M4 N9 S1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M5 Gnd S1bar N7 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M6 SUM S2 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M7 S1 Abar N5 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u


M9 N3 A S1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u


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OUTPUT: CMOS FULL ADDER:


126 UR11EC098



126 UR11EC098



127 UR11EC098


M11 Gnd Bbar N3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u


M13 Cbar C Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M14 Abar A Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M15 S3 A N2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M16 N4 C Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M17 S3 B N4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M18 N10 A Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M19 S3 C N10 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M20 CARRY S3 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M21 S1bar S1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M22 S2 C N19 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M23 N19 S1bar S2 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M24 N19 Cbar Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M25 Vdd S1 N19 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M26 SUM S2 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u


M28 N1 A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M29 S1 A N6 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M30 N6 Bbar S1 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u


M32 Cbar C Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M33 Abar A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M34 N6 Abar Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u



M37 N1 C N8 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u


128 UR11EC098


129 UR11EC098

M38 N8 B N1 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M39 S3 C N8 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M40 N8 A S3 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M41 CARRY S3 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

v42 Vdd Gnd 5.0

.model pmos pmos

.model nmos nmos

V1 A gnd BIT ({0011})

V2 B gnd BIT ({0101})

V3 C gnd BIT ({0010})

.tran 4p 400n

.print A B C SUM CARRY

* End of main circuit: Module0

RESULT:

The design and simulation of half-adder and full-adder has been verified usingTanner.


130 UR11EC098


131 UR11EC098

AIM:

To design and simulate 2x1 Mux and Transmission gate using Tannersoftware.

SOFTWARE USED:

Tanner EDA 7.0

THEORY:

MULTIPLEXER:

It is combinational circuit that selects binary information from one of the manyinputs and directs it to a single output. The selection lines or controlled lines. Itis used as a data selector and parallel to serial convertor. In reference to theblock diagram a two bit binary code on the data select input will also allow thedata on the corresponding data input to pass through the data output.

TRANSMISSION GATE:

Transmission gates also known as pass gates represents another class oflogic circuits which use TGs as basic building block. It consist of a PMOS andNMOS connected in parallel. Gate voltage applied to these gates iscomplementary of each other(C and Cbar). TGs act as bidirectional switchbetween two nodes A and B controlled by signal C. Gate of NMOS is connectedto C and gate of PMOS is connected to Cbar(invert of C). When control signalC is high i.e. VDD, both transistor are on and provides a low resistance pathbetween A and B. On the other hand , when C is low both transistors are turnedoff and provides high impedance path between A and B.

Ex No: 10 10.DESIGN AND SIMULATION OF CMOS TRANSMISSIONGATE AND MULTIPLEXER USING TGDate: 19-3-14


132 UR11EC098

TRANSMISSION GATE

CIRCUIT DIAGRAM:

CODING:


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PROCEDURE:

1. Open the schematic editor(S-edit) from the tanner EDA tool.2. Get the required components from the symbol browser and design given

circuit using the S-edit.3. Give the external supply from the library to the circuit.4. Write the program in the T-edit and run the simulation and check for errors.5. Remove all the errors and again write the program in the T-edit and run.6. Output waveform is viewed in the waveform viewer.7. Get the net list and verify the output.


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OUTPUT:


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Netlist:(Transmission gate)


Version 7.10


Parsing "C:\Users\KARUNYA\Desktop\Module0.sp"



BJTs - 0 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 6


Setup 0.00 seconds



Total 0.03 seconds


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2X1 MULTIPLEXER

CIRCUIT DIAGRAM :

CODING:


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NETLIST:


Version 7.10



Warning T-SPICE : DC sources have non-unique names. "V1".



BJTs - 0 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 7

*** 1 WARNING MESSAGES GENERATED


Setup 0.00 seconds



Total 0.04 seconds


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OUTPUT:


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RESULT:

The design and simulation of transmission gate multiplexer has beenverified using Tanner tools


140 UR11EC098


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AIM:To design and simulate BICMOS inverter, BICMOS NAND and

BICMOS NOR gate and Boolean expression using Tanner EDA.

SOFTWARE USED:

Tanner EDA 7.0

THEORY:BICMOS on chip is obtained by merging CMOS and BJT devices.An

alternative solution to the problem of driving large capacitive loads can be providedby BICMOS.Taking advantage of the low problem consumption of the CMOS andthe high current driving capability of BJT during transients, the BICMOS cancombine the “best of both worlds”.The BICMOS combination has significantadvantages to offer such as improved switching speed and less sensitivity w.r.t theload capacitance.In general, BICMOS logic circuits are not bipolar intensive i.e mostlogic operations are performed by conventional CMOS sub circuits,while the bipolartransistor are used only when high on chip or off chip drive capability is required.

The most significant drawback of BICMOS circuit lies in the increasedfabrication process complexity,it requires 3-4 masks in addition to the wellestablished CMOS process.

BICMOS INVERTER:It consists of two MOS transistors(inverter part) and two npn BJT which

can drive a large capacitive load.In addition,two n-MOS transistors(Mb1 & Mb2) areusually added to provide the necessary base discharge path.

When the input voltage is very close to zero, the n-MOS transistors Mhand Mb1 are off,whereas p-MOS transistor Mp and thus the n-MOS transistor Mb2are on.Since the base voltage of Q2 is equal to zero the bipolar output pull downtransistor is in cut off mode,consequently, both the BJT Q1 and Q2 are not able toconduct any current at this point.

Ex No: 11 11.DESIGN AND SIMULATION OF BICMOS LOGIC CIRCUITSAND BOOLEAN EXPRESSIONDate: 26-3-14


142 UR11EC098

BOOLEAN CIRCUIT FOR (A+BC+ABC)’:

CODING:


143 UR11EC098

When the input voltage is increased beyond the threshold, the n-MOStransistor Mn starts to conduct a non-zero base currents for Q2.Thus,the BJT Q1 andQ2 enter the forward active region. The base emitter junction voltage of bothtransistors rise very abruptly and cause step down in DC voltage characteristics.Forhigh voltage levels,the drain to source voltage of Mn is zero and no base current canbe supplied to Q2.

BICMOS NOR LOGIC:The base of the bipolar pull up transistor Q1 is being driven by two series

connected p-MOS transistors.Therefore the pull up device can be turned on only ifboth the inputs are logic low.

The base of the bipolar pull down transistor Q2 is being driven by two //lelconnected n-MOS transistors.Therefore, the pull down device can be turned on ifeither one or both of the inputs are high.Also, the base charge of the pull up device isremoved by two minimum sized n-MOS transistors connected in //lel between thebase node and the ground.

BICMOS NAND LOGIC:The base of the bipolar pull up transistor Q1 is being driven by two//lel

connected p-MOS transistors.Here, the pull up device is turned on when either one orboth of the inputs are logic low.The bipolar pull down transistor Q2 on the other handis driven by two series connected n-MOS transistors between output node and thebase.Therefore, the pulldown device can be turned on only if both of the inputs arelogic high.For the removal of the base charge of Q1 during turn off,two seriesconnected n-MOS transistors are used,whereas only one n-MOS transistor is utilisedfor removing the base charge of Q2.

PROCEDURE:1.Open the schematic editor(S-edit) from the tanner EDA tool.

2.Get the required components from the symbol browser and design givencircuit using the S-edit.

3.Give the external supply from the library to the circuit.

4.Write the program in the T-edit and run the simulation and check for errors.

5.Remove all the errors and again write the program in the T-edit and run.

6.Output waveform is viewed in the waveform viewer.

7.Get the net list and verify the output.


144 UR11EC098

BICMOS INVERTER CIRCUIT:

CODING:


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Boolean Expression NETLIST:


Version 7.10




BJTs - 0 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 11


Warning T-SPICE : The vrange voltage range limit (5.5) for MOSFET tables has been exceeded.

Warning T-SPICE : The vrange voltage range limit should be set to at least 1480.5 for best accuracyand performance.


Setup 0.00 seconds



Total 4.27 seconds


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BICMOS NAND CIRCUIT:

CODING:


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INVERTER NETLIST:TSPICE - Tanner SPICE

Version 7.10




BJTs - 2 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 6



Warning T-SPICE : The vrange voltage range limit should be set to at least 25.525 for best accuracyand performance.


Setup 0.00 seconds



Total 0.19 seconds


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BICMOS NOR CIRCUIT:

CODING:


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BICMOS NAND NETLIST:


Version 7.10




BJTs - 2 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 7


Setup 0.00 seconds



-----------------------------------------

Total 5.37 seconds


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Output :(Boolean Expression)

Output: (NOT Gate)


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BICMOS NOR GATE NETLIST:TSPICE - Tanner SPICE

Version 7.10





BJTs - 2 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 7


Setup 0.00 seconds



-----------------------------------------

Total 0.04 seconds


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OUTPUT: (NAND GATE)

Output: (NOR Gate)


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RESULT:The design and simulation of BICMOS inverter, BICMOS NAND,

BICMOS NOR logic and a Boolean Expression has been verified using tannertools.


154 UR11EC098

DYNAMIC LOGIC CIRCUIT:

Coding:


155 UR11EC098

AIM:To design and simulate different CMOS design styles using tanner EDA

for the expression .((A.B)+C)’

SOFTWARE USED: Tanner EDA 7.0

THEORY:

Dynamic logic:In static circuits the output is connected to either GND or VDD via a

low resistance path.» fan-in of n requires 2n (n N-type + n P-type) devices.

Dynamic circuits use temporary storage of signal values on thecapacitance of high impedance nodes.

» requires on n + 2 (n+1 N-type + 1 P-type) transistors.

Conditions on Output:1.Once the output of a dynamic gate is discharged, it cannot be chargedagain until the next precharge operation.2.Inputs to the gate can make at most one transition during evaluation.3.Output can be in the high impedance state during and after evaluation(PDN off), state is stored on CL.

Properties of dynamic gates:1. Overall power dissipation usually higher than static CMOS

» no static current path ever exists between VDD and GND (includingPsc)

» no glitching» higher transition probabilities» extra load on Clk

2.PDN starts to work as soon as the input signals exceed VTn, so VM, VIH

and VIL equal to VTn

» low noise margin (NML)3.Needs a precharge/evaluate clock.

Ex No: 12 12.DESIGN AND SIMULATION OF DIFFERENT CMOS DESIGNSTYLESDate: 2-04-14


156 UR11EC098

DOMINO LOGIC :(circuit)

Coding:


157 UR11EC098

Advantages of dynamic logic: Š smaller area than fully static gates Š smaller parasitic capacitances hence higher speed Š reliable operation if correctly designed.

DOMINO LOGIC: When CLK is low, dynamic node is precharged high and buffer inverter

output is low. Nfets in the next logic block will be off. When CLK goes high, dynamic

node is conditionally discharged and the buffer output will conditionallygo high.

Since discharge can only happen once, buffer output can only makeone low-to-high transition.

When domino gates are cascaded, as each gate “evaluates”, if its outputrises, it will trigger the evaluation of the next stage, and so on…like aline of dominos falling.

Like dominos, once the internal node in a gate “falls”, it stays “fallen”until it is “picked up” by the precharge phase of the next cycle. Thusmany gates may evaluate in one eval cycle.

PSEUDO LOGIC: Uses a p-type as a resistive pullup, n-type network for pulldowns.

Characteristics: Consumes static power. Has much smaller pullup network than static gate. Pulldown time is longer because pullup is fighting.

Producing O/P Voltages: For logic 0 output, pullup and pulldown form a voltage

divider.


158 UR11EC098

PSEUDO LOGIC:

CODING:


159 UR11EC098

Must choose n, p transistor sizes to create effectiveresistances of the required ratio.

Effective resistance of pulldown network must be comptuedin worst case—series n-types means larger transistors.

PROCEDURE:1.Open the schematic editor(S-edit) from the tanner EDA tool.

2.Get the required components from the symbol browser and design givencircuit using the S-edit.

3.Give the external supply from the library to the circuit.

4.Write the program in the T-edit and run the simulation and check for errors.

5.Remove all the errors and again write the program in the T-edit and run.

6.Output waveform is viewed in the waveform viewer.

7.Get the net list and verify the output.


160 UR11EC098

OUTPUT:(Dynamic logic)

OUTPUT:(Domino logic)


161 UR11EC098

DYNAMIC LOGIC :(Netlist)


Version 7.10


Parsing "C:\Users\KARUNYA\Desktop\VLSI 12TH lab\Domino\Module0.sp"



BJTs - 0 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 9


Setup 0.00 seconds



-----------------------------------------

Total 0.02 seconds


162 UR11EC098

OUTPUT:(Pseudo logic)


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Domino logic:(Netlist)


Version 7.10




BJTs - 0 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 11

*** 1 WARNING MESSAGES GENERATED


Setup 0.00 seconds



-----------------------------------------

Total 0.08 seconds


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Pseudo Logic:(Netlist)


Version 7.10





BJTs - 0 JFETs - 0






VCVS - 0 VCCS - 0

CCVS - 0 CCCS - 0





Total nodes - 7



Warning T-SPICE : The vrange voltage range limit should be set to

at least 28.6857 for best accuracy and performance.


Setup 0.00 seconds



Total 0.02 seconds


166 UR11EC098


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Result:The design and simulation of dynamic,domino and Pseudo logics has

been verified using Tanner.

Engineering

VLSI Lab manual PDF