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DEPT OF E C, NIET. VLSI LAB MANUAL 1 DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Laboratory Manual VLSI LAB Prepared by: ASHISH SHARMA ASSTT. PROFESSOR ECE DEPARTMENT NIET,JAIPUR Edition 2011

58950419 Vlsi Lab Manual Final

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Page 1: 58950419 Vlsi Lab Manual Final

DEPT OF E C, NIET. VLSI LAB MANUAL 1

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Laboratory Manual

VLSI LAB

Prepared by: ASHISH SHARMA

ASSTT. PROFESSOR

ECE DEPARTMENT

NIET,JAIPUR

Edition

2011

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DEPT OF E C NIET, VLSI LAB MANUAL 2

EXPERIMENT 1 : STATIC CHARACTERISTICS OF INVERTER IN

SCHEMATIC

AIM :

Design a CMOS inverter in schematic and simulate for Transient Characteristics.

PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the one

pMOS and one nMOS transistor models. Using the wire form the tool bar connect the

transistors as shown in the schematic circuit. Give a Clock as the input and simulate for

the output.

Out1= NOT(a)

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EXPERIMENT 2 : STATIC CHARACTERISTICS OF TWO INPUT NAND

GATE, TWO INPUT NOR GATE, TWO INPUT AND GATE, TWO INPUT OR

GATE IN SCHEMATIC

AIM :

Design a CMOS two input NAND gate, Two input NOR gate, Two input AND gate and

Two input OR gate in schematic and simulate for Transient Characteristics.

PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the required

number of pMOS and one nMOS transistor models. Using the wire form the tool bar

connect the transistors as shown in the schematic circuit. Give a Clock as the input and

simulate for the output.

Two Input NOR gate

F= NOT(A+B)

Two Input NAND gate

OUT1=NOT(IN1 AND IN2)

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Two Input AND gate

OUT=A AND B

Two Input OR gate

OUT= A OR B

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EXPERIMENT 3 : STATIC CHARACTERISTICS OF INVERTER IN LAYOUT

AIM :

Design the layout of a CMOS Inverter and simulate for DC(Transfer) and Transient

characteristics.

PROCEDURE :

Run the VLSI software for layout entry. Paint Ndiffussion with proper design rules.

Paint Nwell. Put Pdiffusion. Draw POLY over the diffusions as shown in the layout

diagram. Put the appropriate diffusion contacts and do connections for VDD and GND.

Connect the output contacts using the metal. Label for input and outputs. Assign

appropriate Clock input and simulate for the output. Click appropriate option for DC

characteristics and observe the DC (Transfer) characteristics.

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EXPERIMENT 4 : TRANSFER AND TRANSIENT CHARACTERISTICS OF

TWO INPUT NAND GATE, TWO INPUT OR GATE, TWO INPUT AND GATE

AND TWO INPUT AND GATE IN LAYOUT

AIM :

Design the layout for two input NANDgate, three input OR gate, two input AND gate

and two input AND gate.and simulatelate for DC(Transfer) and Transient characteristics.

PROCEDURE :

Run the VLSI software for layout entry. Paint Ndiffussion with proper design rules.

Paint Nwell. Put Pdiffusion. Draw POLY over the diffusions as shown in the layout

diagram. Put the appropriate diffusion contacts and do connections for VDD and GND.

Connect the output contacts using the metal. Label for input and outputs. Assign

appropriate Clock input and simulate for the output. Click appropriate option for DC

characteristics and observe the DC (Transfer) characteristics.

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EXPERIMENT 5 : REALISE A 2 INPUT EXOR GATE

AIM : Realise a two input EXOR gate in schematic and draw its layout and simulate

PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the required

number of pMOS and one nMOS transistor models. Using the wire form the tool bar

connect the transistors as shown in the schematic circuit. Give a Clock as the input and

simulate for the output.

Run the VLSI software for layout entry. Paint Ndiffussion with proper design rules.

Paint Nwell. Put Pdiffusion. Draw POLY over the diffusions as shown in the layout

diagram. Put the appropriate diffusion contacts and do connections for VDD and GND.

Connect the output contacts using the metal. Label for input and outputs. Assign

appropriate Clock input and simulate for the output. Click appropriate option for DC

characteristics and observe the DC (Transfer) characteristics.

ANOTOUT (= B + AB)

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EXPERIMENT 6 : REALISE A 1 BIT FULL ADDER IN CMOS SCHEMATIC

AND SIMULTATE. GENERATE LAYOUT USING TOOL OPTION AND

SIMULATE

AIM : TO realise a 1 bit full adder in CMOS schematic and simultate. generate layout

using tool option and simulate

PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the required

number of pMOS and one nMOS transistor models. Using the wire form the tool bar

connect the transistors as shown in the schematic circuit. Give a Clock as the input and

simulate for the output.

CBASUM ⊕⊕= CARRY=AB+BC+CA

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Wave forms of one bit Full adder

Layout of one Bit Full adder

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EXPERIMENT 7: REALISE A BOOLEAN EXPRESSION Y=NOT((A+B)(C+D)E)

IN SCHEMATIC AND DRAW ITS LAYOUT AND SIMULATE

AIM : TO realise a Boolean expression Y=Not((A+B)(C+D)E) in schematic and draw

its layout and simulate.

PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the required

number of pMOS and one nMOS transistor models. Using the wire form the tool bar

connect the transistors as shown in the schematic circuit. Give a Clock as the input and

simulate for the output.

Run the VLSI software for layout entry. Paint Ndiffussion with proper design rules.

Paint Nwell. Put Pdiffusion. Draw POLY over the diffusions as shown in the layout

diagram. Put the appropriate diffusion contacts and do connections for VDD and GND.

Connect the output contacts using the metal. Label for input and outputs. Assign

appropriate Clock input and simulate for the output. Click appropriate option for DC

characteristics and observe the DC (Transfer) characteristics.

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EXPERIMENT 8 : 4 X 1 MUX USING TRANSMISSION GATES

AIM : To Realize a 4 X 1 MUX using transmission gates in schematic and layout and

simulate.

PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the required

number of pMOS and one nMOS transistor models. Using the wire form the tool bar

connect the transistors as shown in the schematic circuit. Give a Clock as the input and

simulate for the output.

Theory : CMOS transmission gate is created by connecting an nFET and pFET in

Parallel as shown. If sel=0 nFET is OFF and pFET is OFF and TG acts as Open switch.

When sel=1 then TG acts as closed switch. It does not have threshold voltage drop

problems. It can be used as for transmitting any voltage (0,Vdd) from left to right and

vice versa..

A 4X1 Multiplexer can be designed using transmission gates as shown in Fig.

below. The schematic works as per the truth table given below:

S1 S0 OUT

0 0 I0

0 1 I1

1 0 I2

1 1 I3

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EXPERIMENT 9: D FLIP FLOP, JK FLIPFLOP AND T FLIP FLOP IN CMOS

SCHEMATIC AND LAYOUT

AIM : To Realsie D FLIPFLOP, JK FLIPFLOP and T FLIPFLOP in CMOS schematic

and layout and simulate

PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the required

number of pMOS and one nMOS transistor models. Using the wire form the tool bar

connect the transistors as shown in the schematic circuit. Give a Clock as the input and

simulate for the output.

Run the VLSI software for layout entry. Paint Ndiffussion with proper design rules.

Paint Nwell. Put Pdiffusion. Draw POLY over the diffusions as shown in the layout

diagram. Put the appropriate diffusion contacts and do connections for VDD and GND.

Connect the output contacts using the metal. Label for input and outputs. Assign

appropriate Clock input and simulate for the output. Click appropriate option for DC

characteristics and observe the DC (Transfer) characteristics.

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For T flip-flop short J and K.

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EXPERIMENT 10: FOUR BIT ASYNCHRONOUS COUNTER USING T

FLIPFLOP AS A CELL IN SCHEMATIC.

AIM : To Realsie a four bit asynchronous counter using T flipflop as a cell in schematic

PROCEDURE :

Run the VLSI software for schematic entry. From the library drag the T flip flop cells and

connect them as shown in schematic. Give a Clock and Input and simulate for the output.

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EXPERIMENT 11: FOUR BIT SYNCHRONOUS COUNTER USING T

FLIPFLOP AS A CELL IN SCHEMATIC.

AIM : To Realsie a four bit synchronous counter using T flipflop as a cell in schematic

PROCEDURE :

Run the VLSI software for schematic entry. From the library drag the T flip flop cells and

connect them as shown in schematic. Give a Clock and Input and simulate for the output.

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EXPERIMENT 12: FOUR BIT SHIFT REGISTER USING D FLIPFLOP AS A

CELL IN SCHEMATIC.

AIM : To Realsie a four bit shift register using D flipflop as a cell in schematic

PROCEDURE :

Run the VLSI software for schematic entry. From the library drag the D flip flop cells

and connect them as shown in schematic. Give a Clock and Input and simulate for the

output.

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EXPERIMENT 13: DESIGN OF SCHMITT TRIGGER

AIM : Design a Schmitt trigger for the ratio (β1/β3)=6) and (β4/β6)=3) in layout.

Calculate UTP and LTP and verify the values by simulation. Assume Vdd=1.2v,

Vtn=0.4vand |Vtp|=0.5v. Show the hysterisis curve.

PROCEDURE : Calculate the required W and L from the given parameters. Draw the

layout as shown in the layout. Give a sine wave signal as input and simulate. Use the tool

option to observe the hysterisis curve.

Theory : The Schematic of Schmitt Trigger is shown below. M1 and M2 are in series and

are driven by in1. When in1=0 Vout =Vdd and M3 is ON which acts as feedback path.

As in1 is increased it keeps M2 off even after M1 is turned on. The UTP is given by

3/1( ββ+= VddUTP Vt,n) /(1+ 3/1 ββ )

3)//(1)/(3/1 LWLW=ββ

Similarly M6 is feedback resistor for pFET group. The LTP is given by

|),|(6/4( pVtVddLTP −= ββ /(1+ 6/4 ββ )

6)//(4)/(6/4 LWLW=ββ

Design example : Let UTP =1.45V and LTP= 1.67 V

UTP: =3/1 ββ ),/()( nVtUTPUTPVdd −− = 2.44

63/1 =ββ and (W/L)1/(W/L)3 = 6

M1 width = 6 x width of M3

LTP: =6/4 ββ )|,|/(( LTPpVtVddLTP −− = 2

46/4 =ββ and (W/L)4/(W/L)6 = 4

M4width = 4 x width of M6

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Hysterisis Characteristics

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