Abstract— In this project we present a method to design a

regulated charge pump used to increase the on chip voltages for

programming. Basically this project has 3 components. They are

Charge Pump, Comparator, Non-Overlapping Clock Generator.

Charge Pump has series of MOSFETs which are used to pump

charge whose working is similar to clampers. Non Overlapping

Clock Generator generates pulses to drive MOSFETs. Purpose of

Non Overlapping clocks is to ensure that charge doesn’t flow

backwards. Voltage divider is used to scale the output voltage and

compare it with a reference using Comparator. Depending up on

the output voltage the Comparator enables or disables Non

Overlapping Clock Generator so the output voltage stays

regulated.

Index Terms— 2-Phase Charge pump – Voltage Divider – Non

Overlapping Clock Generator – Comparator.

I. INTRODUCTION

HARGE Pumps are widely used to generate voltages above

normal supply range. High-voltages are required for

programming and erasing of floating gate in EEPROMs and

operation in a Flash memory. Typically in Industry 16V-18V

are generated using 1.8V supply. In this project we are asked to

generate to generate 12.5V from 5V supply.

This report is organized as follows: Section 2

describes the most important components and blocks that are

used in our design. Section 3 discusses the whole circuit and

how it works. Schematics of our circuit, layouts and simulation

results are being discussed in section 4, and answers to the

questions and conclusions are stated in section 5.

II. MAJOR COMPONENTS USED IN CHARGE PUMP

In this section, we introduce the major components that we

used in our project.

A. Dickson Charge Pump.

In Dickson Charge Pump each diode connected MOSFET

charges it’s capacitor thus providing charges to subsequent

stage in alternate cycle. This increases the output voltage to

N*(VDD-Vth).

Fig. General Schematic for Dickson Charge Pump.

Fig. 1. Schematic for Dickson Charge Pump.

Vth of the MOSFETs will increase because of body effect so

the output voltage will decrease so to meet the specifications

number of stages can be increased. So we had to go with

4(VDD-Vth) which makes N=4. We were careful in choosing

the values of capacitors in this component. It was a trade-off

between output voltage required, layout and delay caused by

the capacitors. We chose this capacitor values to be 250fF to

meet required specifications.

Fig. 2. Layout of Dickson Charge Pump.

Ruthvik Vaila.

School of Electrical and Computer Engineering, Boise State University, Idaho 83706

Email: ruthvik.nitc@gmail.com

Design and Layout of a Regulated Charge

Pump

C

Fig. 3. Extracted View of Dickson Charge Pump.

Fig. 4. Proof of LVS pass.

B. Comparator with Voltage divider.

First of all we need a voltage divider to scale the output

voltage of the pump to compare it with the reference voltage

given here we were given a reference voltage of 1.25V. We

have option to choose between resistive and capacitive voltage

divider. We chose to go ahead with capacitive since resistive

dividers are associated with delays which might affect the

performance of the circuit. Layout area for a resistor will be

very large as we will need resistance in the range of Mega

Ohms to reduce the current drawn. The capacitor values

which we used are 10fF and 90fF. We chose fF because of

less layout area.

Fig. 5. Voltage divider using capacitor.

Fig. Capacitive Voltage Divider.

Fig. 6. Schematic of Comparator.

Fig. 7. Layout of Comparator Circuit.

Fig. 8. Extracted view of layout.

Fig. 9. Proof of LVS.

C. Non Overlapping Clock Generator.

We need an oscillator to generate clock. But as our

intention is to control the output voltage we need a clock with

enable. We can control the clock by using a NAND gate at the

output of the oscillator. We can have NAND gate before the

oscillator but this configuration will induce the delay required

to start the oscillator. So we can have a NAND gate with

enable after the oscillator so that oscillator is always running

and we can simply make or break connection between

oscillator and remaining circuit by using enable. Minimum

frequency for clock was estimated using the formula [1]

∆𝑉 = (𝑖𝐿𝑜𝑎𝑑 ∗ 𝑇𝑐𝑙𝑘)/𝐶𝑙

iLoad is Load Current, Tclk is time period of the clock, Cl is

load capacitance, ∆𝑉 is ripple in output voltage. The initial

estimate gave a value of about 5MHz. This is the minimum

clock speed for the given specifications. If we use this

measurement we will have to use many inverters in ring

oscillator so we scaled it up to 400MHz so that we can use 11

inverters in the ring oscillator which can reduce the layout

space.

Fig. 10. Ring Oscillator with Enable

Now we need a non-overlapping clock generator. We achieved

that by having different delays in two arms of the clock and by

having a feedback like shown in the figure below.

Fig. 11. Non Overlapping Clock generator.

Fig. 12. Layout of Non Inverting Clock Generator.

Fig. 13. Extract of Non Inverting Clock Generator.

Fig. 14. Proof of LVS.

III. FINAL CIRCUIT USING ALL COMPONENTS

Now we can combine all the above discussed individual

sections and create one controlled charge pump.

Fig. 15. Schematic of Final Circuit.

Fig. 16. Layout of final Circuit.

Fig. 17. Extract of final Circuit.

Fig. 18. Proof of final LVS.

Fig. 19. Open Loop Schematic.

IV. SIMULATION RESULTS

Fig. 20. Output of Oscillator with Enable.

Fig. 21. Output of Non Overlapping Clock Generator

Fig. 22. Output of Open Loop Circuit.

Fig. 23. Output of Closed Loop Circuit.

Fig. 23 is the output before tuning the circuit parameters like

capacitance, clock speed. We can see the ripple is almost

750mV which is very high.

Fig. 24. Output after adjusting capacitors and comparator.

Fig. 24 shows the output after tweaking circuit parameters to

bring down the ripple. Ripple is brought down which is well

below the specifications. See Fig. 25.

Fig. 25. Ripple in the output voltage.

A. The Process Corners

Fig. 26. Output Voltages for Process Corners.

B. Supply Voltage Variations

Fig. 27. Output Voltage for Variation in VDD.(0.5 steps)

C. Temperature Corners

Fig. 28. Output Voltage for Temperature Variation.

D. Output Voltage for Load Variations

Fig. 29. Output Voltage for Varying Loads.

E. Efficiency and Current in sub-sections

Fig. 30. Output Voltage and Currents consumed in each of the three sub-

sections

Current consumed by comparator, non-overlapping clock,

Dickson charge pump was around 1.5mA, 3mA, 1mA

respectively. Power consumed is 27.5mW. Efficiency is

0.46%. Fig 31 shows pie diagram for power consumption in

three major components.

Fig. 31. Pie Diagram for Power Consumption.

F. Pad Frame for Final Layout

Fig. 32. Pad Frame for Final Layout.

Pins 1, 3, 4, 6, 7, 10, 12 are not used.

Pin2- Vout.

Pin5- VDD.

Pin8-Vref.

Pin9-Vbiasn.

Pin11- GND.

V. CONCLUSION

Following table summarizes the important design results and

specifications.

TABLE I: Design Overview and Results

Specification Result

Rise Time 7.5us

Efficiency 0.45%

Power Consumption 27mW

Output Voltage 12.485

Ripple 15mV

Current

comparator non ovlp clk charge pump

REFERENCES AND FOOTNOTES

A. References

[1] Dr. Vishal Saxena, Charge pump slides in the www. Lumerink.com/teaching/Digital IC design