RADIATION HARDENING IN

DIGITAL CIRCUITS

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CONTENTS

Purpose

Radiation Hardening

Sources of Radiation

Effects of Radiation on Digital circuits

Radiation hardening by Process

Radiation hardening by Design

Conclusion

References

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Purpose

Radiation immunity required only for

circuits used in Spacecraft, Military and

Nuclear environments

High level of ionizing radiation cause

electrical defects in the CMOS circuits

Due to continuous scaling of the CMOS

technologies, small charge can flip the

voltage levels.

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Radiation Hardening

Radiation: The process in which energy isemitted as particles or waves

RH: Method of designing and testingelectronic components and systems to makethem resistant to damage or malfunctionscaused by radiations

Radiation Sources◦ Cosmic Rays

◦ Sun radiation

◦ Nuclear reactors & Nuclear explosions

◦ Chip Packaging

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Effects of Radiation on Digital circuits

Lattice Displacement effects

Total ionizing dose effects

Charge-Transfer effects: Energetic radiation can transfer

charge within a material and across interfaces as a result

of the kinetic energy transferred to secondary particles.

Linear Enter Transfer(LET): Amount of energy

deposited as it passes through a semiconductor material

It depends on

◦ Type of Radiation

◦ Frequency of operation

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Types of Errors caused by RH

Soft Errors

◦ Temporary errors or

short-time errors

◦ Eg. Single Event

Transient(SET)

Hard Errors

◦ Permanent Errors

◦ Eg. Single Event

Upset(SEU)

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Single Event Effects

• Single-Event Upset(SEU):

o State changes of memory or register bits causedby a single ion interacting with the chip.

o In some sensitive devices, a single ion mayintroduce Multiple-Bit Upset(MBU)

• Single-Event Transient(SET):

o It occurs when the charge collected from anionization event discharges in the form of aspurious signal traveling through the circuit. Infact this is the effect of an electrostatic discharge.

Single-Event Latch-up

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Radiation Hardening by Process

Choice of substrate with wide band gap,

which gives it higher tolerance to deep

level defects

SOI Process

◦ No Latch up

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Radiation Hardening by Design

1. PN Junction Diode based SEU Clamping

Circuits: Widely used

9

G

G

P

in

1V

0V

1.4

V

-0.4V

outP

out

Radiation

Strike

V (out)

time

0

0.2

0.4

0.6

0.8

V (outP)

time

0

0.2

0.4

0.6

0.8

-0.4Shadow

Gate

Clampin

g circuit

Ref: R. Garg, N. Jayakumar, S. P. Khatri, and G. Choi, “A design approach for radiation-hard digital electronics,” in Proceedings, IEEE/ACM Design Automation Conference(DAC), pp. 773–778, July 2006.

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2. Gate Sizing: Used in Memory Devices

Ref: Q. Zhou and K. Mohanram, “Gate sizing to radiation hardened combinationallogic”, IEEE Trans. Computer-Aided Design of Integrated Circuits andSystems, Vol 25, No. 1, pp. 155 – 166, Jan. 2006.

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Triple Modular Redundancy(TMR)

Ref: AlZain, M.A.Soh B, Pardede E, "Evaluation of multi-cloud computing TMR-basedmodel using a cloud simulator", 11th International Conference on Fuzzy Systemsand Knowledge Discovery (FSKD),page(s): 6 – 11, August,2014 .

A

B

C

A B C Y

0 1 0 0

1 1 0 1

Y

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Contd….

Advantages

◦ It can mitigate both

SETs and SEUs

◦ It is robust and reliable

than the actual circuit

Disadvantages

◦ Requires more than 3

times the actual

number of required

transistors

◦ More area and more

power consumption

Other version of could be introducing the delay

at the output

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Error Correcting and Detecting

codes

Parity Method

Checksum

Cyclic Redundancy Check

◦ Used in communications

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Conclusion

Radiation hardening is essential in Digital

circuits

Power, area constrained are the drawbacks

of most RHBD techniques

It's an engineering challenge to develop

space chips that perform many sensitive,

vital functions while being robust enough

to performing under severe conditions.

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References

[1]. Gaillardin M, Girard S, Paillet P, Leray J.L, GoiffonV, Magnan P, Marcandella C,

Martinez M, Raine M, Duhamel O, Richard N, Andrieu F, Barraud S, Faynot O,

"Investigations on the Vulnerability of Advanced CMOS Technologies to MGy Dose

Environments", IEEE Transactions on Nuclear Science, On page(s): 2590 - 2597

Vol: 60, Issue: 4, Aug, 2013.

[2]. Dodd, P.E, Shaneyfelt M.R, Schwank, J.R, Felix J.A, “Current and Future

Challenges in Radiation Effects on CMOS Electronics”, IEEE Transactions On

Nuclear Science, page(s):1747 – 1763,VOL. 57, NO. 4, Aug ,2010.

[3]. J. R. Schwank, V. Ferlet-Cavrois, M. R. Shaneyfelt, P. Paillet and P. E. Dodd,

“Radiation effects in SOI technologies,” IEEE Transactions on Nuclear Science, Vol.

50, No. 3, pp. 522–538, Jun. 2003.

[4]. Q. Zhou and K. Mohanram, “Gate sizing to radiation hardened combinational

logic”, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol

25, No. 1, pp. 155 – 166, Jan. 2006.

[5]. R. Garg, and S. P. Khatri. A Novel, Highly SEU Tolerant Digital Circuit Design

Approach. In IEEE International Conference on Computer Design, 2008, pp 14-20.

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