Oblique Memory Array Design

Oblique Memory Array Design

Presented By :

Sujit Kr. Nayak

29 March 2010 www.ecTech.in

Plan of the Talk…

Introduction

Oblique Memory Array Design Method

Specification Decision

First Column Portraying

Array Completing

Power Net Connecting

Area Calculation Formulae

Comparison with Common Method

Conclusion


This is an efficacious memory array design

method for low temperature poly-silicon

technique (LTPS).

All layout areas are utilized properly, without

wasting any space.

Unlike traditional rectangular arrays, less

space is needed for conducting wire layout.

Introduction


Introduction (contd…)

The LTPS technique is extensively applied in

thin film transistor liquid crystal displays (TFT

LCD).

LTPS allows integration of driving circuits on

glass substrate.

However, sketching complex memory circuits

on glass substrate without excessive metal or

poly layers presents a difficult challenge.


Operations…

Four operations in oblique memory array

design:

• Specifications decision

• First column portraying

• Memory array production

• Power net connection


Oblique Memory Array Design Method

Memory Array

Producing

Specification

Decision

1st column

portraying

Power Net

connection

Design Start Optimal Memory Array

Fig: Flow chart of Oblique Memory Array Design Method


Specifications decision

Design specification is selected.

Example :- Kind of memory cells and their amounts, the number of columns and rows in the memory array.

The direction of memory cell I/O ports is selected, which must be different directions on the two sides of the memory cell.


First column portraying

Fig: First column portraying


First column portraying

Sketch of first column is made.

It is necessary to sketch a vertical reversed

cell, and the I/O ports must turn the direction

defined in the previous step.

The first memory cell is the vertical reverse of

the second one, and is in the same direction

as the third one (i.e. the two directions of

memory cell are separated into odd floor

memory cells and even floor memory cells).


Array Completing

Copy of the first column is pasted side by side

repeatedly until the specified number of columns

is reached.

A connection area lies between every cell of

each column.

The same signal metal pins, such as clock signal

and power pins, are connected with horizontal

connection pins in the gaps between the

memory columns, without the cost of extra

layout space.


Power Net Connecting

Finally, the power metal on the left and right

sides of the memory array are linked to form

a power net.

Now, a regular memory array is obtained,

with its I/O ports map out symmetrically.

The power ring is connected all around each

memory cell and can supply power for each

memory cell.


Fig: Power Net Connection


Area Calculation Formula

)1(. ymyhH powercellarray

xwmgny

nnW celllrlarray .).(2

).(

When evenx

xwmgy

nnW cellrlarray .).(2

1).(

When oddx

For a Memory Array of Size x by y, Height of the Memory Array is

and the width is given by:


Contd…(Area calculation Formula)

Where,

cellh

cellw

powerm

height of each memory cell

width of each memory cell

width of metal layer of power

m width of the connective material

g gap between two connective material

lnrn no. of ports of memory cell on the left and right&


Layout Comparison

Fig: The layout of TSPC circuit (left). The layout after improvement

of oblique memory array design (right).


Comparison with Common MethodTitle Oblique Method Common Method

Area of an 8x8

Array

Less than two times of total

cells area

More than two times of

total cells area

Speed Using TSPC circuit, faster then

static memory cell

Slower using static

memory cell

Effect Area

arte

Regular Array without

Surplus space

Not an regular array,

and wasting some

space

For System

Integration

Suitable for IC on glass

substrate

Not convenient for

design on glass

substrate

Verification Verification of design is

possible by the formula

No standard formula to

check



Conclusion…

This method reduces the layout area by 5%

to 10% without any surplus spaces.

Increases the speed to more than three times

that of static memory cell by using TSPC

circuit.

Because of its regular property, the control

circuits design is more easy.

At any time, the design can be checked

whether it is optimal or not.


References…

Fan Y.C. Fan and Y.C. Chen, “Oblique

Memory Array Design Method” IEEE

Trans. On Magnetics, Vol. 45,No. 5,May

2009.

H.Wang, T. Sun, and Q. Yang, “Minimizing

area cost of on-chip cache memories by

caching address tags,” IEEE Trans.

Computers, Vol. 46,No. 11, Nov. 1997.


Thank You…

Engineering

Oblique Memory Array Design