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Internal microprocessor architecture

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Page 1: Internal microprocessor architecture
Page 2: Internal microprocessor architecture

Group Members

12063122-011 ( M.Noman )

12063122-017 ( Hafiz Hamid )

12063122-029 ( Salah Uddin Ayubi )

12063122-037 ( Mubashar Naeem )

12063122-023 ( Safi ur rehman Tabasum )

University Of Gujrat (Pakistan)

Page 3: Internal microprocessor architecture

Internal microprocessorarchitecture

ON the basis of programing

Page 4: Internal microprocessor architecture

Microprocessor’s typeInternal structure of microprocessor should be known

Single core 1. single task at any time

2.access whole memory at

the same time by any program

Dual core 1.multiple task at any time

2.access specific memory by

any task

Page 5: Internal microprocessor architecture

Programing modelProgram visible : 8086,8088

Registers are used directly

during programing

Program invisible : 80286 and above

1. Registers are not accessible

directly during programing

2. Can be used indirectly

Page 6: Internal microprocessor architecture

Programing modelProgram visible : 8086,8088

Registers are used directly

during programing

Program invisible : 80286 and above

1. Registers are not accessible

directly during programing

2. Can be used indirectly

Page 7: Internal microprocessor architecture
Page 8: Internal microprocessor architecture

Only for 64 bit

Page 9: Internal microprocessor architecture

cont.…. We can’t access these register with the instruction used

to access general purpose register AX,BX etc….

To access the low order byte of R8 use R8B

To access the low order word of R10 use R10W

Page 10: Internal microprocessor architecture

Cont.……

Page 11: Internal microprocessor architecture

Condition flag

Page 12: Internal microprocessor architecture

Special purpose flag The 6 Segment Registers are:

Stack Segment (SS). Pointer to the stack.

Code Segment (CS). Pointer to the code.

Data Segment (DS). Pointer to the data.

Extra Segment (ES). Pointer to extra data ('E' stands for 'Extra').

F Segment (FS). Pointer to more extra data ('F' comes after 'E').

G Segment (GS). Pointer to still more extra data ('G' comes after 'F').

Page 13: Internal microprocessor architecture

Details about registers

Page 14: Internal microprocessor architecture

Remember R_ _ used in 64 bit MP

E_ _ used in 32 bit MP

(E stand for extended)

Register can access as R_ _ , E_ _ , _ _ , _L ,_ H

Page 15: Internal microprocessor architecture

Multipurpose or general purpose register

Page 16: Internal microprocessor architecture

Accumulator (RAX)

Used for I\O operation, rotate, shift, multiplication and division

Page 17: Internal microprocessor architecture

Base index (RBX)

Hold the offset address of a location In a memory system

Also address the memory data

Page 18: Internal microprocessor architecture

Count Register (CX)

Used as default counter for various instruction like repeated string, shift, rotate(CL), loop etc…

Hold the offset address of memory data

Address memory data

Page 19: Internal microprocessor architecture

Data Register (DX) Hold the part of the result from a multiplication or

part of the dividend before division.

Address memory data

Page 20: Internal microprocessor architecture

Stack Pointer : pointing the top of the stack

in stack segment

Base Pointer: contain the offset address within

data segment

Source index : Used as a pointer to a source in

stream operations

Destination index : used as a pointer to

destination in stream

operations

All these register also used for based

indexed, register indirect addressing

Page 21: Internal microprocessor architecture

R8-R15

These register are only found in Pentium 4 and core2 if 64-bit extensions are enables

Used as general purpose register

In most application these registers remain unused

Page 22: Internal microprocessor architecture

Special Purpose Register

Instruction pointer (IP) :

point to the next

instruction in a program located within

the code segment

Stack Pointer :

pointing the top of the stack

in stack segment to store data

Page 23: Internal microprocessor architecture

Flag RegisterDetermine the current state of the process

Modified automatically after M.Operations

Conditional FlagCarry flag:

indication of overflow condition for

unsigned integer and hold carry

Auxiliary flag :

indication the carry/borrow from

lower nibble to high nibble(D3-D4)

Page 24: Internal microprocessor architecture

Parity flag : indication of parity of the result

Zero : set if result is zero

Sign flag: In signed magnitude format, if the

result of the operation is negative,

sign flag is set

Page 25: Internal microprocessor architecture

Control FlagControl the operation of the execution unit

Trap flag : if set, then debugging operationis allow

Interrupt flag: control the operation of interruptrequest.

note : set by instruction STI clear by instruction CLI

Direction flag : used in string operation. if it is set,string byte is accessed from higher memoryaddress to lower memory address

Page 26: Internal microprocessor architecture

Flags for 32,64-bit

IOPL (I\O privilege level) :

used to select the privilege level for I\O

devices.

if the current privilege level is 00 ,I\O

execute without hindrance

if 11 then an interrupt occur and

suspended the execution

Page 27: Internal microprocessor architecture

NT (nested task) :

indicate whether the task is nested with

other or not

RF (resume) :

resume flag is used with debugging to

control the resumption of execution after

the next instruction

Page 28: Internal microprocessor architecture

VM (virtual mode) :

This allow the system program to execute

multiple DOS operation

AC (alignment check) :

if the word or double word

Is addressed on a non-word or

non-double word boundary

VIF (virtual interrupt flag) :

copy the interrupt flag bit

(in Pentium 4)

Page 29: Internal microprocessor architecture

VIP (virtual interrupt pending) :

Give the information about virtual mode

interrupt. Set if interrupt is pending

ID (identification) :

The ID flag indicate that Pentium 4 micro-

processor support the CPUID or not.

The CPUID instruction provides the system

with information about microprocessor such

as its version number and manufacturer

Page 30: Internal microprocessor architecture

Segment Register

CS (code segment) :

area of memory that hold the code

(executable program) used by MP

Have the starting address of the memory

that hold code

CS:IP used to access the whole 64k

memory of code segment

Page 31: Internal microprocessor architecture

SS (stack segment) : area of memory used for the stack stack is used to store data memory 64k can be access by SS:SPDS (data segment) : area of memory that hold all data

refer by general purpose register(AX, BX etc. )

64k memory Accessed by using DS and offset address register

Page 32: Internal microprocessor architecture

ES (extra segment) :

additional data segment that is used by

some of the string instructions to hold

destination data

FS and GS :

supplemental register used as most

extra segment in 64-bit MP. Window use

these segments for internal operation. But

no definition for their usage is available

Page 33: Internal microprocessor architecture

REAL MODE MEMORY ADDRESSING

The only mode available on the 8086-8088.

20 bit address bus 1 MB, 16 bit data bus, 16 bit registers

80286 and above operate in either the real or protected mode.

Real mode operation allows addressing of only the

first 1M byte of memory space—even in Pentium 4

or Core2 microprocessor.

the first 1M byte of memory is called the real memory,

conventional memory, or DOS memory system

Page 34: Internal microprocessor architecture

Segment registers hold the base address of where a particular segment begins in memory. There is the

code segment (CS)

data segment (DS)

stack segment (SS)

extra segment (ES).

Page 35: Internal microprocessor architecture

Segments and Offsets

All real mode memory addresses must consist of a

segment address plus an offset address.

segment address defines the beginning address of any

64K-byte memory segment

offset address selects any location within the

64K byte memory segment

Page 36: Internal microprocessor architecture

Segments and Offsets

16-bit each

Appended 4 bits (0H)Segment Start Addressin Segment Register

0

Then the Effective memory Address (EA) =

20-bit segment start address + 16-bit offset address

Page 37: Internal microprocessor architecture

– this shows a memory

segment beginning at

10000H, ending at

location IFFFFH• 64K bytes in length

– also shows how an offset

address, called a

displacement, of F000H

selects location 1F000H

in the memory

Segments and Offsets

Page 38: Internal microprocessor architecture

Segments and Offsets

Once the starting address is known, the ending

address is found by adding FFFFH.

because a real mode segment of memory is 64K in

length

The offset address is always added to the segment

starting address to locate the data.

[1000:2000H]

a segment address of 1000H; an offset of 2000H

Page 39: Internal microprocessor architecture

Effective Address Calculations

• EA = segment register (SR) x 10H + offset

(a) SR: 1000H

10000 + 0023 = 10023H

(b) SR: AAF0H

AAF00 + 0134 = AB034H

(c) SR: 1200H

12000 + FFF0 = 21FF0H

Page 40: Internal microprocessor architecture
Page 41: Internal microprocessor architecture

Default Segment and Offset Registers

The microprocessor has rules that apply to segments whenever memory is addressed.

These define the segment and offset register combination

[CS:IP]

The code segment register defines the start of the code segment.

The instruction pointer locates the next instruction within the code segment.

Page 42: Internal microprocessor architecture

Default Segment and Offset Registers

Another of the default combinations is the stack.

stack data are referenced through the stack segment at

the memory location addressed by either the stack pointer

(SP) or the base pointer (BP)

a memory segment can touch or overlap if 64K bytes of

memory are not required for a segment

Page 43: Internal microprocessor architecture

– think of segments as

Windows that can be

moved over any area of

memory to access data or

code

– a program can have more

than four or six segments,

• but only access four or six

segments at a time

Default Segment and Offset Registers

00000

Stack

Code

Data

Extra

0FFFF

10000

1FFFF

20000

2FFFF

30000

33FFF

34000

43FFF

44000

48FFF

49000

58FFF

59000

FFFFF

Memory

1 0 0 0 DS

2 0 0 0 CS

3 4 0 0 SS

4 9 0 0 ES

Page 44: Internal microprocessor architecture

Default Segment and Offset Registers

Code should be limited to

only this portion of the

code segment, to avoid

effects of segment

overlap.

Page 45: Internal microprocessor architecture

They can occupy completely separate parts of memory.

Multiple segments could even coincide because there are multiple segment registers, the CPU can keep track of.

A program can use, multiple segments at the same time.

Page 46: Internal microprocessor architecture
Page 47: Internal microprocessor architecture

Default Segment and Offset Registers

Default segment numbers in:

CS for program (code)

SS for stack

DS for data

ES for string (destination) data

Default offset addresses that go with them

Convention Example: EA = CS:[IP]

Segment Startin Segment register

Offset: Literalor in a CPU register

Page 48: Internal microprocessor architecture
Page 49: Internal microprocessor architecture

TPA The Transient Program Area (TPA) holds the DOS

(disk operating system) operating system; other

programs that control the computer system.

TPA is the first available area of memory above

drivers and other TPA programs

Area is indicated by a free-pointer maintained by

DOS

program loading is handled automatically by the

program loader within DOS

Page 50: Internal microprocessor architecture

The TPA also stores any currently active or inactive DOS application programs.

Page 51: Internal microprocessor architecture

Real Mode Addressing Scheme Allows Relocation

A relocatable program is one that can be placed

into any area of memory and executed without

change.

Segment plus offset addressing allows DOS

programs to be relocated in memory.

Page 52: Internal microprocessor architecture

This mainly means using relative offsets for data

accesses and jump instructions. If this is easy/possible is

based on the type of architecture, the size of the address space and the size of the program..

Relocatable data are data that can be placed in any

area of memory and used without any change to the program

Page 53: Internal microprocessor architecture

Real Mode Addressing Scheme Allows

Relocation

Because memory is addressed within a segment

by an offset address, the memory segment can be

moved to any place in the memory system without

changing any of the offset addresses.

.

Page 54: Internal microprocessor architecture

Only the contents of the segment register must be

changed to address the program

in the new area of memory.

Windows programs are written assuming that the first 2G

of memory are available for code and data.

Page 55: Internal microprocessor architecture