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Microprocessor Architectur Nikita Gupta Department of Computer Engineering 1 UNIT I-Lecture-2 8086

Microprocessor Architecture

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Intel 8086 (For computer Science Students)

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  • Microprocessor ArchitectureNikita GuptaDepartment of Computer Engineering

    *UNIT I-Lecture-2 8086

  • The block diagram of a microprocessor-based computer system.*

  • Organization of a Microprocessor based system*

  • Central Processing Unit*Its job is to control the operations of the computer, i.e.

    It consist of ALU,CU and Registers

  • Binary DigitsBits: 0 or 1Byte: group of 8bitsword: number of bits the microprocessor recognizes and processes at a time. The word length ranges from 4 bits to 64 bits.nibble: represents a group of 4 bits*

  • BusesA bus is a common group of wires that interconnect components in a computer system.The buses that interconnect the sections of a computer system transfer address, data, and control information between the microprocessor and its memory and I/O systems.In the microprocessor based computer system, three buses exist for this transfer of information: address, data, and control.*

  • The block diagram of a computer system showing the address, data, andcontrol bus structure.*

  • The Intel family of microprocessor bus and memory sizes*

  • The Programming Model*

  • Features of 8086It is a 16-bit p.8086 has a 20 bit address bus can access up to 220 memory locations (1 MB) .It has 16 bit address lines to access I/O devices hence it can support up to 64K I/O ports.It provides 14, 16 -bit registers.It has multiplexed address and data bus AD0- AD15 and A16 A19.It requires single phase clock with 33% duty cycle to provide internal timing.8086 is designed to operate in two modes, Minimum and Maximum.Minimum Mode: A system with only 1 processor i.e. 8086.Maximum Mode: A system with 8086 and other processors like 8087-(Math Co-processor), 8089-(IO processor) or multiple 8086 processors.*

  • Features of 8086It uses a two stage pipelining i.e. Fetch Stage and Execution Stage. It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up instruction execution.8086 uses memory banksThe entire data is not stored sequentially in a single memory of 1 MB but the memory is divided into two banks of 512 KB eachLower bank (or even bank because it stores the data bytes at even location 2,4,6 and so on) and higher bank(or odd bank because it stores the data bytes at odd location 1,3,5 and so on)The benefit of this is that 16-bit data can be accessed in a single access even though the memory chip can store only 8-bit at a locationIt uses memory segmentationIt requires +5V power supply.It has 256 vectored interrupts.A 40 pin dual in line package*

  • 8086 Memory BanksOne memory bank contains all the bytes which have even addresses such as 00000h, 00002h, and 00004h etc. the data lines of this bank is connected to the lower 8 bit data lines i.e. from D0 to D7 of 8086.The other memory bank contains all bytes which have odd addresses such as 00001h, 00003h and 00005h etc. the data lines of this bank is connected to the upper 8 bit data lines i.e. from D8 to D15 of 8086. *

  • Pipelined architecture of the 8086 microprocessors*

  • Architecture of 80868086 has two blocks The Bus Interfacing Unit (BIU) and The Execution Unit (EU).The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue.EU executes instructions from the instruction system byte queue.Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance.BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.*

  • Internal Architecture of 8086*

  • Bus Interface UnitIt provides a full 16 bit bidirectional data bus and 20 bit address bus.The bus interface unit is responsible for performing all external bus operations.Specifically it has the following functions:Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction.These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle.

    *

  • Bus Interface Unit (Cont..)After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output.The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory.These intervals of no bus activity, which may occur between bus cycles are known as Idle state.If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle.The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. This address is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write.*

  • Execution UnitThe Execution unit is responsible for decoding and executing all instructions.The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write cycles to memory or I/O and perform the operation specified by the instruction on the operands.During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction.If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue.When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions.Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue*

  • 8086 Register*

  • General Purpose Registers

    Normally used for storing temporary results Each of the registers is 16 bits wide (AX, BX, CX, DX)Can be accessed as either 16 or 8 bits AX, AH, AL

    *AX - the AccumulatorBX - the Base RegisterCX - the Count RegisterDX - the Data Register

  • General Purpose RegistersAX Accumulator Register Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language CodeMust be used in multiplication and division operationsMust also be used in I/O operationsBXBase RegisterAlso serves as an address register

    *

  • General Purpose RegistersCXCount registerUsed as a loop counterUsed in shift and rotate operationsDXData registerUsed in multiplication and divisionAlso used in I/O operations

    *

  • Pointer and Index Registers

    All 16 bits wide, L/H bytes are not accessibleUsed as memory pointersExample: MOV AH, [SI]Move the byte stored in memory location whose address is contained in register SI to register AHIP is not under direct control of the programmer

    *

  • Pointer and Index RegistersStack Pointer (SP) is a 16-bit register pointing to program stack.Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing. The BP register (Base Pointer) is similar to the BX register. You'll generally use this register to access parameters and local variables in a procedure.Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions.Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions.The SI and DI registers (Source Index and Destination Index ) have some special purposes as well. You may use these registers as pointers (much like the BX register) to indirectly access memory. You'll also use these registers with the 8086 string instructions when processing character strings.*

  • Flag Register*CarryParityAuxiliary CarryZeroOverflowDirectionInterrupt enableTrapSign6 are status flags3 are control flag

  • Flag RegisterActive FlagThere are 9 active flags out of 16, in the 8086 flag register. The remaining are undefined flags.Control FlagThe Trap flagSetting TF puts the processor into single step mode for debugging. In single stepping, microprocessor executes a instruction and enters into single step ISR.After that user can check registers or memory contents, if found ok, he/she will proceed further, else necessary action will be taken. This utility is to debug the program.TF=1 (Trap on), TF=0 (Trap off)*

  • Flag RegisterThe Interrupt FlagSetting this bit enables maskable interrupts.IF=1 (Interrupt enable), IF=0(Interrupt disable)The Direction FlagThis bit is specifically for string instructions. In string instruction we use SI and DI registers as offset registers to point source area and destination area respectively.If set (DF=1) then string manipulation instructions will auto-decrement index registers i.e. process string from high addresses to low addresses, or from right to left. If cleared (DF=0) then the index registers will be auto-incremented, i.e. process string from low addresses to high addresses, or from left to right.*

  • Flag RegisterConditional (status) FlagsSix flags out of nine active flags indicate status of the result produced after the execution of an instruction. Such flags are called as the conditional flags.Parity Flag (PF) This flag is normally used to check for data transmission error.This flag is set if parity (the number of "1" bits) in the low-order byte of the result is even.Zero Flag (ZF) This flag is set if the result is zero.Sign Flag (SF)This flag is set if the most significant bit of the result is set.SF=1 (negative), SF=0 (positive)*

  • Flag RegisterThe Auxiliary Carry Flag (AF) This flag set if there was a carry from or borrow to bits 0-3 in the AL register.The Carry Flag (CF) This flag is set if there was a carry from or borrow to the most significant bit during last result calculation.The Overflow Flag (OF)This flag is set if the result is too large positive number, or is too small negative number to fit into destination operand.*

  • 8086 Programmers Model*ESCSSSDSIPAHBHCHDHALBLCLDLSPBPSIDIFLAGSAXBXCXDXExtra SegmentCode SegmentStack SegmentData SegmentInstruction PointerAccumulatorBase RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index RegisterBIU registers(20 bit adder)EU registers

  • Memory SegmentationThe total memory size is divided into segments of various sizes.A segment is just an area in memory.The process of dividing memory this way is called Segmentation.*

  • Memory SegmentationIn memory, data is stored as bytes.Each byte has a specific address.Intel 8086 has 20 lines address bus.With 20 address lines, the memory that can be addressed is bytes. 220 = 1,048,576 bytes (1 MB).8086 can access memory with address ranging from 00000 H to FFFFF H.*

  • Memory SegmentationIn 8086, memory has four different types of segments.These are:Code SegmentData SegmentStack SegmentExtra Segment*

  • Memory Segmentation*

    IP

    AX

    DX

    CX

    BX

    SP

    DI

    SI

    BP

    SR

    CS

    ES

    SS

    DS

    AH

    BH

    CH

    DH

    AL

    BL

    CL

    DL

    External memory address space

    Code segment(64Kbytes)

    Data segment(64kbytes)

    Stack segment(64kbytes)

    Extra segment(64kbytes)

    0000016

    FFFFF16

    8088/8086 MPU

  • Memory Segmentation*In non overlapping schemeThe complete1Mbytes memory may be divided into 16 segments, particular of 64Kbytes size. The addresses of the segments can be assigned as 0000H to F000H respectively. The offset address values are from 0000H to FFFFH so that the physical addresses range from 00000H to FFFFFH. In overlapping schemeImagine a segment begins at a specific address and its maximum size may be 64Kbytes. But, if another segment begins before these 64Kbytes locations of the first segment, the 2 segments are said to be overlapping segments. The region of memory from the start of the second segment to the possible end of the first segment is known as overlapped segment area.

  • Memory Segmentation*

  • Segment RegisterEach of these segments are addressed by an address stored in corresponding segment register.These registers are 16-bit in size.Each register stores the base address (starting address) of the corresponding segment.Because the segment registers cannot store 20 bits, they only store the upper 16 bits.*

  • Segment Register*

  • Segment Register*How is a 20-bit address obtained if there are only 16-bit registers?The answer lies in the next few slides.The 20-bit address of a byte is called its Physical Address.But, it is specified as a Logical Address.Logical address is in the form of:Base Address : OffsetOffset is the displacement of the memory location from the starting location of the segment.

  • ExampleThe value of Data Segment Register (DS) is 2222 H.To convert this 16-bit address into 20-bit, the BIU appends 0H to the LSBs of the address.After appending, the starting address of the Data Segment becomes 22220H.If the data at any location has a logical address specified as:2222 H : 0016 HThen, the number 0016 H is the offset.2222 H is the value of DS.*

  • Example (cont..)To calculate the effective address of the memory, BIU uses the following formula:Effective Address = Starting Address of Segment + OffsetTo find the starting address of the segment, BIU appends the contents of Segment Register with 0H.Then, it adds offset to it.Therefore:EA = 22220 H + 0016 H ------------ 22236 H*

  • Example (cont..)*

  • Memory Address Generation*

  • Max. Size of SegmentAll offsets are limited to 16-bits.It means that the maximum size possible for segment is 216 = 65,535 bytes (64 KB).The offset of the first location within the segment is 0000 H.The offset of the last location in the segment is FFFF H.*

  • Where to Look for the Offset*

  • Generating memory addressA segment base and an offset describe a logical addressBoth segment base and offset are 16-bit quantities (since all registers are 16 bits long)However, the physical address used to access memory is 20 bitsGeneration of physical address involves combining a 16-bit offset (either in IP, BX, SI, DI, BP or SP) and a 16-bit segment base value in one of the segment registers (CS, SS, DS or ES) In fetching an instruction, the segment base value is always the code segment (CS) register, the offset value is always the instruction pointerThus, the physical address of next instruction is CS:IP

    *

  • Generating memory addressIn accessing a data in the memory, the segment value is typically in the data segment (DS) and the offset value is given by source index register (SI) for reading, and destination index register (DI) for writingThe physical address is therefore DS:SI (read) or DS:DI (writing)Segment-override prefix can be used to change the segment from which the variable is accessed; for e.g. change the default segment to extra segment (ES)To access data in the stack (temporary storage area in memory), the physical address is formed by combining the values in stack register (SS) with stack pointer (SP), which is SS:SP*

  • Generating memory address*

    0

    Segment register

    Offset value

    :

    CS, SS, DS, ES

    IP, SP, SI, DI, BX

    Segment register

    Shift left by 1 digit

    Offset value

    +

    Physical address

    20-bit physical address

    Added with shifted segment

  • Generating memory address*E.g. Find the physical address of the data at logical address DS:BX, as well as the physical addresses of the lowest byte and the highest byte of the active data segment.

    Physical address of DS:BX -> 01230H + 4567H = 05797HPhysical address of lowest and highest bytes: 01230H, 1122FH

    Text

    4567H

    0123H

    8088/8086

    Memory

    DS:0000H

    DS:FFFFH

    Active data segment

    Lowest address

    Highest address

    DS:BX

    BX

    DS

  • Example: Program SegmentCode segmentThe logical address of an instruction always consists of a CS (code segment) and an IP (instruction pointer), shown in CS:IP format.*

  • Example: Program SegmentCode segmentExample 1-1If CS = 24F6H and IP = 634AH, show:(a)The logical address(b)The offset addressAnd calculate:(c) The physical address(d) The lower range(e) The upper range of the code segmentSolution:(a)24F6:634A (b) 634A(c) 2B2AA (24F60 + 634A) (d) 24F60 (24F60 + 0000)(e) 34F5F (24F60 + FFFF)*

  • Example: Program SegmentLogical address and physical address in the data segmentThe physical address for data is calculated using the same rules as for the code segment.Example 1-2Assume the DS is 5000 and offset is 1950. Calculate the physical address of the byte.*

  • Example: Program SegmentLogical address and physical address in the data segmentExample 1-3If DS = 7EA2H and the offset is 438EH,(a)Calculate the physical address. (b) Calculate the lower range.(c) Calculate the upper range of the data segment. (d) Show the logical address. Solution:(a)83DAE (7EA20 + 438E) (b) 7EA20 (7EA20+0000)(c) 8FA1F (7EA20 + FFFF) (d) 7EA2:438E*

  • Example: Program SegmentExample 1-4Assume that the DS register is 578C. To access a given byte of data at physical memory location 67F66, does the data segment cover the range where the data is located? If not, what changes need to be made?Solution: No, since the range is 578C0 to 678BF, location 67F66 is not included in this range. To access that byte, DS must be changed so that its range will include that byte.*

  • QuestionThe contents of the following registers are:CS = 1111 HDS = 3333 HSS = 2526 HIP = 1232 HSP = 1100 HDI = 0020 HCalculate the corresponding physical addresses for the address bytes in CS, DS and SS.*

  • Solution1. CS = 1111 HThe base address of the code segment is 11110 H.Effective address of memory is given by 11110H + 1232H = 12342H.2. DS = 3333 HThe base address of the data segment is 33330 H.Effective address of memory is given by 33330H + 0020H = 33350H.3. SS = 2526 HThe base address of the stack segment is 25260 H.Effective address of memory is given by 25260H + 1100H = 26350H.*

  • Advantages of SegmentationAllow the memory capacity to be 1Mb even though the addresses associated with the individual instructions are only 16 bits wide.Facilitate the use of separate memory areas for the program, its data and the stack.Permit a program and/or its data to be put into different areas of memory each time the program is executed.Multitasking becomes easy.*

  • The StackThe stack is used for temporary storage of information such as data or addresses.When a CALL is executed, the 8086 automatically PUSHes the current value of CS and IP onto the stack.Other registers can also be pushedBefore return from the subroutine, POP instructions can be used to pop values back from the stack into the corresponding registers.

    *

  • The Stack*

  • Example for PUSH*

  • Example for POP*

  • Addressing ModesThe CPU can access operands (data) in various ways, called addressing modes. The number of addressing modes is determined when microprocessor is designed and cannot be changed. The 80x86 provides a total of seven distinct addressing modes:1. Register2. Immediate3. Direct4. Register indirect5. Based relative6. Indexed relative7. Based indexed relative*

  • Addressing ModesRegister addressing modeThe register addressing mode involves the use of registers to hold the data to be manipulated. Memory is not accessed when this addressing mode is executed; therefore, it is relatively fast. MOV BX, DXMOV ES, AXADD AL, BHIt should be noted that the source and destination registers must match in size.*

  • Addressing ModesImmediate addressing modeIn the immediate addressing mode, the source operand is a constant. Immediate addressing mode can be used to load information into any of the registers except the segment registers and flag registers. Examples:MOV AX, 2550H ;move 2550H into AXMOV CX, 625 ;load the decimal value 625 into CXMOV BL, 40H ;load 40H into BLTo move information to the segment registers, the data must first be moved to a general-purpose register and then to the segment register. Example:MOV AX, 2550HMOV DS, AXIn other words, the following would produce an error:MOV DS, 0123H ;illegal!!!*

  • Addressing ModesDirect addressing modeThis address is the offset address and one can calculate the physical address by shifting left the DS register and adding it to the offset as follows:MOV DL, [2400] ;move contents of DS:2400H into DLExample 1-15Find the physical address of the memory location and its contents after the execution of the following, assuming that DS = 1512H.MOV AL, 99HMOV [3518H], ALSolution:First AL is initialized to 99H, then in line two, the contents of AL are moved to logical address DS:3518Hwhich is 1512:3518. Shifting DS left and adding it to the offset gives the physical address of 18638H (15120H + 3518H = 18638H).That means after the execution of the second instruction, the memory location with address 18638H will contain the value 99H.*

  • Addressing ModesRegister indirect addressing modeThe registers used for this purpose are SI, DI, and BX. If these registers are used as pointers, that is, if they hold the offset of the memory location, they must be combined with DS in order to generate the 20-bit physical address. MOV AL, [BX] ;moves into AL the contents of the memory location;pointedto by DS:BXMOV CL, [SI] ;move contents of DS:SI into CLMOV [DI], AH ;move contents of AH into DS:DIExample 1-16Assume that DS = 1120, SI = 2498, and AX = 17FE. Show the contents of memory locations after the execution ofMOV [SI], AXSolution:The contents of AX are moved into memory locations with logical address DS:SI and DS:SI+1. Low address 13698H contain FE, and high address 13699H contains 17H.*

  • Addressing ModesBased relative addressing modeIn the based relative addressing mode, base registers are BX and BP. The default segments are DS for BX and SS for BP. For example:MOV CX, [BX]+10 ;move DS:BX+10 and DS:BX+10+1 into CX ;PA = DS (shifted left) + BX + 10Alternative codings are MOV CX, [BX+10] or MOV CX, 10[BX]In the case of the BP register,MOV AL, [BP]+5 ;PA = SS(shifted left) + BP + 5Again, alternative codings areMOV AL, [BP+5] or MOV AL, 5[BP] *

  • Addressing ModesIndexed relative addressing modeThe indexed relative addressing mode works the same as the based relative addressing mode, except that registers DI and SI hold the offset address. Examples:MOV DX, [SI]+5 ;PA = DS (shifted left) + SI + 5MOV CL, [DI]+20 ;PA = DS (shifted left) + DI +20Example 1-17Assume that DS = 4500, SS = 2000, BX = 2100, SI = 1486, DI = 8500, BP = 7814, and AX = 2512. Show the exact physical memory location where AX is stored in each of the following. All values are in hex.(a)MOV [BX]+20, AX (b) MOV [SI]+10, AX(c) MOV [DI]+4, AX (d) MOV [BP]+12, AXSolution:(a)DS:BX+20 location 47120 = (12) and 47121 = (25)(b)DS:SI+10location 46496 = (12) and 46497 = (25)(c)DS:DI+4location 4D504 = (12) and 4D505 = (25)(d)SS:BP+12location 27826 = (12) and 27827 = (25) *

  • Addressing ModesBased indexed addressing modeBy combining based and indexed addressing modes, a new addressing mode is derived called the based indexed addressing mode.MOV CL, [BX][DI]+8 ;PA = DS (shifted left) + BX + DI+ 8MOV CH, [BX][SI]+20 ;PA = DS (shifted left) + BX + SI + 20MOV AH, [BP][DI]+12 ;PA = SS(shifted left) + BP + DI + 12MOV AH, [BP][SI]+29 ;PA = SS(shifted left) + BP + SI + 29The coding of the instructions above can vary; for example, the last example could have been writtenMOV AH, [BP+SI+29]Or MOV AH, [SI+BP+29] Note thatMOV AX, [SI][DI]+displacementis illegal. *

  • Addressing Modes*

  • INTEL 8086 - Pin Diagram*

  • *INTEL 8086 - Pin DetailsGroundClockDuty cycle: 33%Power Supply5V 10%ResetRegisters, seg regs, flagsCS: FFFFH, IP: 0000H If high for minimum 4 clks

  • INTEL 8086 - Pin DetailsMicroprocessor & MicrocontrollerAddress/Data Bus:Contains address bits A15-A0 when ALE is 1 & data bits D15 D0 when ALE is 0.Address Latch Enable:When high, multiplexed address/data bus contains address information.

  • INTEL 8086 - Pin DetailsINTERRUPTNon - maskable interruptInterrupt requestInterrupt acknowledge

  • INTEL 8086 - Pin DetailsDirect Memory AccessHold acknowledgeHold

  • INTEL 8086 - Pin DetailsAddress/Status BusAddress bits A19 A16 & Status bits S6 S3

  • INTEL 8086 - Pin DetailsBus High Enable/S7Enables most significant data bits D15 D8 during read or write operation.S7: Always 1.BHE#, A0:

    0,0: Whole word (16-bits)

    0,1: High byte to/from odd address

    1,0: Low byte to/from even address

    1,1: No selection

  • INTEL 8086 - Pin DetailsMin/Max modeMinimum Mode: +5VMaximum Mode: 0VMinimum Mode PinsMaximum Mode Pins

  • Minimum Mode- Pin Details

  • Maximum Mode- Pin DetailsStatus Signal

    Inputs to 8288 to generate eliminated signals due to max mode.S2 S1 S0 000: INTA001: read I/O port010: write I/O port011: halt100: code access101: read memory110: write memory111: none -passive

  • Maximum Mode- Pin DetailsDMA Request/GrantLock OutputLock OutputUsed to lock peripherals off the systemActivated by using the LOCK: prefix on any instruction

  • Maximum Mode- Pin DetailsQueue StatusUsed by numeric coprocessor (8087)QS1 QS000: Queue is idle01: First byte of opcode10: Queue is empty11: Subsequent byte of opcode

  • Suggested ReadingsChapter 1 to Chapter3, Advanced Microprocessors and peripherals, AK Ray and KM Bhurchandi*

    *