Intel® 80386 Microprocessor:FLAG REGISTER AND DEBUG AND CONTROL REGISTER

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Intel® 80386 Microprocessor• The 80386 processor dramatically extended the 8086 register set. • In addition to all the registers on the 80286 (and therefore, the 8086),

the 80386 added several new registers and extended the definition of the existing registers.

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Intel® 80386 Microprocessor:Flag Register

•Flag Register of 80386: The Flag register of 80386 is a 32 bit register. Out of the 32 bits, Intel has reserved bits D18 to D31, D5 and D3, while D1 is always set at 1.Two extra new flags are added to the 80286 flag to derive the flag register of 80386. They are VM and RF flags.

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Intel® 80386 Microprocessor:Flag Register • C (Carry) –It holds the carry after calculations.• P (Parity) –Parity is a logic 0 for odd parity and a logic 1 for even

parity. Parity is a count of ones in a number expressed as even or odd.• A (Auxiliary carry) –Carry occurs bits positions 3 and 5 of the

results. • Z (Zero) – The zero flag shows that the result of an arithmetic or

logical operation is zero. When Z = 1, the result is zero. When Z = 0, the result was non-zero.• T (Trap) – Enables trapping through an on-chip debugging facility.

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Intel® 80386 Microprocessor:Flag Register (CONT’D) • S (Sign) – The sign flag holds the arithmetic sign after an

arithmetic or a logical operation. If S =1 the sign bit is set and the result is negative. If S = 0, the sign bit is not set and the result is positive.• I (Interrupt) – The interrupt flag controls the operations of the

INTR(Interrupt request) input pint. If I =1, the INTR pin is enabled; if I =0, the INTR pin is disabled.• VM (virtual mode) – If this flag set, the 80386 enters the virtual

mode within the protected mode. In this mode, if any privileged instruction is executed, an exception 13 is generated.

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Intel® 80386 Microprocessor:Flag Register (CONT’D)

• 9. RF(resume) – The resume flag is used with debugging to control the resumption of execution after the next instruction.

• 10. NT (nested task) – The nested task flag is used to indicate that the current task is nested within another task in protected mode operation. This flag is set when the task nested by software.

• 11. IOPL (I/O Privilege level) – IOPL is used in protected mode operation to select the privilege level for I/O devices. IF the current privilege level is higher or more trusted than the IOPL, I/O executed without hindrance. If the IOPL is lower than the current privilege level, an interrupt occurs.

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• VM - Virtual Mode Flag : If this flag is set, the 80386 enters the virtual 8086 mode within the protection mode. This is to be set only when the 80386 is in protected mode. In this mode, if any privileged instruction is executed an exception 13 is generated. This bit can be set using IRET instruction or any task switch operation only in the protected mode.

•RF- Resume Flag : This flag is used with the debug register breakpoints. It is checked at the starting of every instruction cycle and if it is set, any debug fault is ignored during the instruction cycle. The RF is automatically reset after successful execution of every instruction, except for IRET and POPF instructions.

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Debug Registers

Debug Address Registers (DR0-DR3)• Each of these registers contains the linear address associated with

one of four breakpoint conditions.• The debug address registers are effective whether or not paging is

enabled.• The addresses in these registers are linear addresses. If paging is

enabled, the linear addresses are translated into physical addresses by the processor's paging mechanism.• If paging is not enabled, these linear addresses are the same as

physical addresses.

Debug Control Register (DR7)• For each address in registers DR0-DR3, the corresponding fields R/W0 through

R/W3 specify the type of action that should cause a breakpoint. The processor interprets these bits as follows:

00 ── Break on instruction execution only01 ── Break on data writes only10 ── undefined11 ── Break on data reads or writes but not instruction fetches

Debug Control Register (DR7)• Fields LEN0 through LEN3 specify the length of data item to be monitored. A

length of 1, 2, or 4 bytes may be specified. The values of the length fields are interpreted as follows:

00 ── one-byte length01 ── two-byte length10 ── undefined11 ── four-byte length• If RWn is 00 (instruction execution), then LENn should also be 00. Any other

length is undefined.

Debug Control Register (DR7)The low-order eight bits of DR7 (L0 through L3 and G0 through G3) selectively enable the four address breakpoint conditions. There are two levels of enabling:• The local (L0 through L3) and global (G0 through G3) levels. The local enable bits

are automatically reset by the processor at every task switch to avoid unwanted breakpoint conditions in the new task.• The global enable bits are not reset by a task switch; therefore, they can be used

for conditions that are global to all tasks.The LE and GE bits control the "exact data breakpoint match" feature of the processor. If either LE or GE is set, the processor slows execution so that data breakpoints are reported on the instruction that causes them. It is recommended that one of these bits be set whenever data breakpoints are armed. The processor clears LE at a task switch but does not clear GE.

Debug Control Register (DR6)• When the processor detects an enabled debug exception, it sets the low-order

bits of this register (B0 thru B3) before entering the debug exception handler. • Bn is set if the condition described by DRn, LENn, and R/Wn occurs. The BT bit is

associated with the T-bit (debug trap bit) of the TSS. The processor sets the BT bit before entering the debug handler if a task switch has occurred and the T-bit of the new TSS is set. There is no corresponding bit in DR7 that enables and disables this trap; the T-bit of the TSS is the sole enabling bit. The BS bit is associated with the TF (trap flag) bit of the EFLAGS register. The BS bit is set if the debug handler is entered due to the occurrence of a single-step exception. • The single-step trap is the highest-priority debug exception; therefore, when BS is

set, any of the other debug status bits may also be set. The BD bit is set if the next instruction will read or write one of the eight debug registers and ICE-386 is also using the debug registers at the same time.

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Control Registers

• A Control register is a processor register which controls the general behavior of a CPU. Common tasks performed by control registers include interrupt control , switching the addressing mode and paging control.• The protected mode includes the 4 system control registers, identified as CR0 to

CR3. • These all are 32 bit registers.

• CR2 :- The control register CR2 is used to store the 32-bit linear address at which the previous page fault was detected(PFLA).• CS3 :- Used when virtual addressing is enabled, hence when the PG bit is set in CR0. CR3 enables the processor to translate linear addresses into physical addresses by locating the page directory and page tables for the current task. Typically, the upper 20 bits of CR3 become the page directory base register (PDBR), which stores the physical address of the first page directory entry

Control Registers•CR0 :- Register CR0 contains a number of special control bits that are defined as follow ….1) PG (pagging) :- if PG is set ,it enables paging and use the CR3 register, else

disable paging.2) ET (Extension Type):- On the 80386 , it allowed to specify whether the external

math coprocessor was an 80287 or 80387. if ET=0 than it is 80287, else 80387.

3) TS (Task Switch) :- The processor sets TS with every task switch and tests TS when interpreting coprocessor instructions.

4) EM(Emulation) :- EM indicates whether coprocessor functions are to be emulated.

5) MP(Monitor) :- MP controls the function of the WAIT instruction, which is used to coordinate a coprocessor.

6) PE(Protected Mode Enables):-If 1,System is in protected mode, else system is in real mode.

References

• Intel386™ EX Embedded Microprocessor Datasheet.• The INTEL Microprocessors:

8086/8088, 80186/80188, 80286, 80386, 80486, Pentium, Pentium Pro Processor, Barry B. Brey.• INTEL 80386 PROGRAMMER'S

REFERENCE MANUAL, 1986, MIT Press

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