80386 Microprocessor · 2018. 9. 10. · T (Trap) – The trap flag enables trapping through an on-chip debugging facility. When this is set to 1 the microprocessor interrupts operation

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80386 Microprocessor

Prof. Ms.Aaradhana Deshmukh

DAY 6 Aaradhana Deshmukh, SKNCOE,

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2 Aaradhana Deshmukh, SKNCOE,

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EAX AH AX AL ACCUMULATOR

EBX BH BX BL BASE INDEX

ECX CH CX CL COUNT

EDX DH DX DL DATA

ESP SP STACK POINTER

EBP BP BASE POINTER

EDI DI DESTINATION INDEX

ESI SI SOURCE INDEX

32 BIT

NAMES 16 bit

names

8 bit

names

Aaradhana Deshmukh, SKNCOE,

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EIP IP ACCUMULATOR

EFLAGS FLAGS FLAGS

CS CODE

DS DATA

ES EXTRA

SS STACK

FS

GS

• The shaded boxes exist only from 80386 through P4

• FS and GS registers have no special names. Aaradhana Deshmukh, SKNCOE,

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Programming Model

The architecture of the earlier 8086 through 80286 are fully

upward compatible to the 80386 through P4.

Registers EAX, EBX, ECX, EDX, EBP, EDI and ESI are

regarded as general purpose or multi purpose registers.

Multi-purpose registers hold various data sizes ( bytes, words

, or double words) and are used for almost any purpose , as

dictated by program.


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Multipurpose Registers

EAX (ACCUMULATOR) – The accumulator is used for

instructions such as multiplication, division and some of the

adjustment instructions. In 80386 and above, the EAX register

may also hold the offset address of a location in memory

system.

EBX (BASE INDEX) – This can hold the offset address of a

location in the memory system in all version of the

microprocessor. It the 80386 and above EBX also can address

memory data.


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ECX (count) – This acts as a counter for various instructions.

As we will see later in 80386 and above, the ECX register also

can hold the offset address of memory data. Instruction use

use a count are the repeated string instructions (

REP/REPE/REPNE) and shift rotate and LOOP/LOOPD

instructions. The shift and rotate instructions use CL as the

count, the repeated string instruction use CX, and the

LOOP/LOOPD instructions use either CS or ECX.


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EDX (data) – EDX is a general-purpose registers that holds a

part of the result for mutilation or part of the dividend before a

division. In the 80386 and above this register can also address

memory data.

EBP(Base Pointer) – EBP points to a memory location in all

version of the microprocessor for memory data transfers. This

register is addressed as either BP or EBP.

EDI (Destination index) – EDI often addresses string

destination data for the string instruction. It also functions as

either a 32-bit (EDI) or 16-bit (DI) general-purpose register. Aaradhana Deshmukh, SKNCOE,

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ESI (Source index) – ESI can either be used as ESI or SI. It

is often used to the address source string data for the string

instructions. Like EDI ESI also functions as a general-purpose

registers.


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Special – Purpose Registers EIP (Instruction Pointer) – EIP addresses the next instruction in

a section of memory defined as a code segment. This register is IP

(16bit) when microprocessor operates in the real mode and EIP (32

bits) when 80386 and above operate in protected mode.

Although 8086, 8088 and 80286 do contain EIP but only 80286

and above operate in protected mode.

The Instruction pointer, which points to the next instruction in a

program, is used by the microprocessor to find the next sequential

instruction in a program located within the code segment. The

instruction pointer can be modified with a jump or a call

instruction.


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Special – Purpose Registers ESP (Stack Pointer) – ESP addresses an area of memory called

the stack. The stack memory is a data LIFO data structure. The

register is referred to as SP if used in 16 bit mode and ESP if

referred to as a 32 bit register.

EFLAGS – Indicates the condition of the microprocessor and

controls its operations. Flag registers are also upward compatible

since the 8086-80268 have 16bit registers and the 80386 and

above have EGLAF register (32 bits)


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Flags

31.

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22

2

1

20 19 18 17 16 15 14 13 12 1

1

1

0

9 8 7 6 5 4 3 2 1 0

I

D

V

I

P

V

I

F

A

C

V

M

R

F

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T

IO

P1

IO

P0

O D I T S Z A P C

808680888018680188

80286

80386/8986DX

80486SX

PENTIUMPENTIUM 4


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FLAGS The flags:

• C

• P

• A

• Z

• S

• O

Change after many arithmetic and logic operations

These are known as Conditional Flags. Aaradhana Deshmukh, SKNCOE,

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Flags

C (Carry) –It holds the carry after addition or the borrow

after subtraction. The carry flag also indicates error

conditions, as dictated by some programs and procedures.

P (Parity) –Parity is a logic 0 for odd parity and a logic 1 for

even parity. Parity is a count of ones in a number expressed as

even or odd. Today this is seldom used, initially implemented

to check data during communication. Today this is mostly

done through external hardware rather than the P.


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Flags

A (Auxiliary carry) –The auxiliary carry holds the carry

(half-carry) after addition or the borrow after subtraction

between bits positions 3 and 5 of the results. This highly

specialized flag is use during BCD operations.

Z (Zero) – The zero flag shows that the result of an arithmetic

or logical operation is zero. When Z = 1, the result is zero.

When Z = 0, the result was non-zero.

S (Sign) – The sign flag holds the arithmetic sign after an

arithmetic or a logical operation. If S =1 the sign bit is set and

the result is negative. If S = 0, the sign bit is not set and the

result is positive. Aaradhana Deshmukh, SKNCOE,

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Flags T (Trap) – The trap flag enables trapping through an on-chip

debugging facility. When this is set to 1 the microprocessor

interrupts operation based on values set in the debugging

register and the control registers.

I (Interrupt) – The interrupt flag controls the operations of

the INTR(Interrupt request) input pint. If I =1, the INTR pin is

enabled; if I =0, the INTR pin is disabled. The state of the I

flag bit is controlled by the STI (set I flag) and CLI (Clear I

flag) instructions.


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Flag D (Direction) – The direction flag selects either the increment

or decrement mode for DI and/or SI registers during string

instructions. If D=1 the registers are automatically

decremented; if D =0 the registers are automatically

incremented. The D flag is set with the STD( set direction)

and cleared with the CLD(clear direction) instruction.

O (overflow) – Overflow occurs when signed numbers are

added or subtracted. An overflow indicates that the result has

exceeded the capacity of the machine. For example if a 7FH

(+127) is added using a 8 bit addition to a 01H ( +1) the result

is 80H(-128). The result represents an overflow condition

indicated by the overflow flag for the signed addition. Aaradhana Deshmukh, SKNCOE,

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Flags IOPL (I/O Privilege level) – IOPL is used in protected mode

operation to select the privilege level for I./O devices. IF the

current privilege level is higher or more trusted than the IOPL,

I/O executed without hindrance. If the IOPL is lover than the

current privilege level, an interrupt occurs, causing execution

to suspend. Note that an IPOL is 00 is the highest or more

trusted; if IOPL is 11, it’s the lowest or least trusted.

NT (nested task) – The nested task flag is used to indicated

that the current task is nested within another task in protected

mode operation. This flag is when the task I nested by

software.


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Flags RF(resume) – The resume flag is used with debugging to

control the resumption of execution after the next instruction.

VM (virtual mode) – The VM flag bit selects virtual mode

operation in a protected mode system. A virtual mode system

allows multiple DOS memory partitions that are 1M byte in

length to coexist in the memory system. Essentially, this

allows the system program to execute multiple DOS

programs.


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Flags AC (alignment check) – This flag is activates if a word or a

double work is addressed on a non-word or non-double word

boundary. Only the 80486SX microprocessor contains the

alignment check bit that is primarily used by its companion

numeric coprocessor, the 80487SX, for synchronization.

VIF (Virtual Interrupt flag) – The VIF is a copy of the

interrupt flag bit available to the Pentium – P4 microprocessor.

This is used in multitasking environments to provide the

operating system with virtual interrupt flags and interrupt

pending information.


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Flags ID (identification) – The ID flag indicated that the Pentium-

P4 microprocessors support CPUID instruction. The CPU ID

instruction provides the systems with information about the

Pentium microprocessor, about as its version number and the

manufacturer.


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Segment Register • CS (Code) – The code segment is a section of memory that

holds the code used by the microprocessor.

• The code segment registers defines the starting address

of the section of memory holding code.

• In read mode operation, it defines the start of the 64K-byte

section of the memory in protected mode, it selects a

description that describes the starting address and length of

a section of memory holding code.

• The code segment is limited to 64K bytes in the 8088-

80268 and 4 GB in the 80386 and above when these

microprocessors operate in the protected mode. Aaradhana Deshmukh, SKNCOE,

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DS (Data) – The data section contains most data used by a

program. Data are accessed in the data segment by an

offset address of the contests of other registers that hold

the offset address.

ES (extra) – The extra segment is used to hold information

about string transfer and manipulation

SS (Stack) – The stack segment defines the area of memory

used for the stack. The stack entry point is determined by

the stack segment and stack pointer registers. The BP

registers also addresses data within the stack segment.

FS and GS – These are supplement segment registers

available in the 80386 and above microprocessors to allow

two additional memory segments for access by programs.


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Real Mode Memory Addressing 80286 and above operate in either the read or protected mode.

Only the 8086 and 8088 operate exclusively in the real mode.

Real mode operation allows the microprocessor to address

only the first 1Mbyte of memory space called either real

memory or conventional memory.

Even if P4 is running in real mode it can address only 1Mbyte.

This real mode feature is partially responsible for the success

of the Intel family of microprocessors.

Code written for 80868088 is upward compatible and will

work on 80286 and others without any upgrades. Aaradhana Deshmukh, SKNCOE,

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Segment and Offsets Combination of a segment address and an offset address

access a memory location in the real mode.

The segment address located within one segment register

defines the beginning address of any 64K-byte memory

segment.

The offset address is also held in a register and selects any

location within the 64K byte memory segment.


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FFFFF

1FFFF

1F000

10000

00000

1000

Segment Register

Offset = F000

Offset is also sometimes referred to as

displacement Aaradhana Deshmukh, SKNCOE,

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The segment register in the previous example contained

1000H yet it addresses a segment starting at location 10000H.

In real mode ever value in the segment register is appended

with a 0H on its rightmost end.

Because of the append, real mode segments can begin only at

16-byte boundary in the memory system.This 16-byte

boundary is called a paragraph.

Also because we know hat in real mode segment of memory is

60K in length, the ending address is found by adding FFFFH.


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What is the ending address of the segment, whose address is

defined as 3000H in the segment register?

A segment with segment address of 1000H and offset address

of 2000H may also be written as 1000:2000.

What is the actual memory location for 1200:300?

In 80286 (with special circuitry) and the 80386 through P4 an

extra 64K minus 16 bytes is addressable when the segment

address is FFFFH and the HIMEM>SYS driver is installed in

the system. This extra area 0FFFF0H – 10FFEFH is referred

to as high memory.


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Some addressing modes combine more than one register and

an offset value to form an offset address.

Find the actual memory location being pointed to if the

segment address is given as 4000H and the two offset

registers hold offset values F000H and 3000H.


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Default Segment and Offset Registers

There are some default segment and settings that are used.

For example CS:IP or CS:EIP is used to find the location of

the instruction the microprocessor fetches to be executed next.

If code segment register contains the value 1400H and EIP

contains 00001200H. What is the actual physical location of

the next instruction.?


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Default Segment and Offset Registers

Another default combination is implemented by the Stack.

Stack uses the SS (Stack Segment) to give the base address

and then the offset is defined by the SP (Stack pointer) or

BP(Base Pointer)

Stack uses the SS (Stack Segment) to give the base address

and then the offset is defined by the SP (Stack pointer) or

BP(Base Pointer)

NOTE: In real mode only rightmost 16 bits of the extended

register address a location within the memory segment.

Placing a number larger than FFFFH into an offset register

while in real mode causes the system to halt and indicate an

addressing error. Aaradhana Deshmukh, SKNCOE,

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Segmentation Remember that 8086-80286 microprocessors allow four

memory segments and 80386 and above allow six memory

segments.

Memory segments can touch or even overlap if 64K bytes of

memory are not required for a segment.

Think of a segment as a windows that can be moved over any

area of the memory to access data or code within that area.


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GENERAL SEGMENTATION EXAMPLE: PAGE 60

OVERLAPPING EXAMPLE PAGE 61

Segment and offset addressing scheme seems complicated. But, it

has its advantages.

What could be its advantage ?


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Relocate-able programs:

A program that can be places into any area of memory and

executed without changing.

Relocate-able data:

Data that can be moved to any part of the memory and can still be

used without making changes to the program that use such data.

This is ideal for use in general-purpose computer system in which

not all machines contain the same memory areas.

The structure of the personal computer memory structure is

different form machine to machine requiring relocate able software

and data.


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Intel 32-bit processors

• They include 80386 and 80486.

• First they introduced 80386DX, 80386SX and

80386SL.

• It was compatible with 8088/8086/80286

• 80386DX(DX refers to floating point

capability)

• 80386SX(SX refers to 16-bit data bus)

– It offers 24 bit address bus(16MB physical m/m)

• 80386SL(offered several power management

options and sleep modes to conserve battery

power for laptops) Aaradhana Deshmukh, SKNCOE,

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Intel 32-bit processor - 80486

• 80486DX – Improved with memory cache and

math coprocessor

• 80486SX – Does not have math coprocessor

• Clock doubler/tribler were also released (75%

faster than the comparable non-doubled

processor)

– DX2-66 33MHz

– DX2-50 25MHz

– DX4-100 25MHz

– DX4-75 25MHz


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80386DX


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Features of 80386DX

• It supports 8/16/32 bit data operands

• It has 32-bit internal registers

• It supports 32-bit data bus and 32-bit non-

multiplexed address bus

• It supports

– Physical Address of 4GB

– Virtual Address of 64TB

– Maximum Segment size of 4GB


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Features of 80386DX • It operates in 3 different modes

– Real

– Protected

– Virtual 8086

• MMU provides virtual memory, paging and 4

levels of protection

• Clock Frequency : 20,25 and 33MHz

• It has 132 pin package


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Architecture of 80386

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Three Sections:

Bus Interface

units

Central

Processing Unit

Memory

Management

Unit


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• The internal architecture of 80386 is

divided into three sections:

1. Central Processing Unit

2. Memory Management Unit

3. Bus Interface unit


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Central Processing Unit


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• The CPU is further divided into:

– Instruction Unit

– Execution Unit

• Instruction Unit:

– It decodes the opcode bytes received from the

16-byte instruction queue and arranges them

into a 3-decoded instruction queue.

– After decoding it is passed to control section

for deriving necessary control signals 47 Aaradhana Deshmukh, SKNCOE,

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Central Processing Unit • Execution Unit:

– It has 8 general purpose and 8 special purpose

registers which either handles data or addresses

– The 64-bit barrel shifter increases the speed of all

shift, rotate, multiply and divide operations

– The multiply/divide logic implements the bit-shift-

rotate algorithms to complete the operations in

minimum time(Even 32bit multiplication is done

in 1µs)


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• Element of the EU

– Arithmetic/logic unit (ALU)

• Performs the operation identified by ADD, SUB, AND, etc.

– Flags register

• Holds status and control information

– General-purpose registers

• Holds address or data information

– Control ROM

• Contains microcode sequences that define operations

performed by machine instructions

– Special multiply, shift, and barrel shift hardware

• Accelerate multiply, divide, and rotate operations


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Memory Management Unit


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Memory Management Unit

• MMU consists of a segmentation unit and

paging unit

• Segmentation Unit:

– It allows the use of two address components -

segment and offset – for relocability and

sharing of data

– It allows a maximum segment size of 4GB

– It provides a 4-level protection mechanism for

protecting and isolating system’s code and data

from those of application program 51 Aaradhana Deshmukh, SKNCOE,

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Memory Management Unit – The limit and attribute PLA checks segment limits

and attributes at segment level to avoid invalid

accesses to code and data in memory segment.

• Paging Unit

– It organizes physical memory in terms of pages of

4KB size

– It works under the control of segmentation unit

– It converts linear addresses into physical addresses

– The control and attribute PLA checks privileges at

page level.


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Bus Interface Unit

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• It has a prioritizer to resolve

the priority of various bus

requests. This controls the

access of the bus

• The address driver drives

the bus enable and address

signals A2 – A31.

• The pipeline/bus size unit

handles the control signals

for pipelining and dynamic

bus sizing units


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Bus Interface Unit

• The data buffers interface the internal data

bus with system bus


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NEXT : Signal Interface of 80386DX


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Three Sections:

Bus Interface

units

Central

Processing Unit

Memory

Management

Unit


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Is this enough for today ?


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Documents

80386 Microprocessor · 2018. 9. 10. · T (Trap) – The trap flag enables trapping through an on-chip debugging facility. When this is set to 1 the microprocessor interrupts operation