Digital design chap 6

DIGITAL ELECTRONICSCHAPTER 6

DEE 204

CONVERSATION BETWEEN ANALOG AND SYSTEM FUNCTION OF AD AND DA

CONVERTERS

Principle of operation of a A-D and D-A converter

Principle of operation of a single and dual ramp

A continuously balanced and successive approximation A-D converter


CONVERTERSPrinciple of operation of a A-D and D-A

converterBasic on digital signal processingDigital signal processing:

- converts signals that naturally occur in analogue form to digital form using digital techniques to enhance and modify analogue signal data for applications


CONVERTERSPrinciple of operation

of a A-D & D-A converter

Basic on digital signal processing

Digital signal processing: - First translates

continuously varying analogue signal into series of discrete levels resembling a staircase as shown


CONVERTERSPrinciple of operation of

a A-D & D-A converterBasic on digital signal

processingDigital signal processing: - Changing the analogue

signal to staircase form by a sample and hold circuit


CONVERTERSPrinciple of operation of a A-D & D-A converterBasic on digital signal processingDigital signal processing: - The stairstep approximation is quantized into binary

codes by a circuit called analogue-to-digital converter (ADC)

- Binary coded form is then fed into DSP, signal converted back into original analogue signal by digital-to-analogue converter (DAC)


CONVERTERSPrinciple of operation of a A-D & D-A converterBasic on digital signal processingDigital signal processing: - The basic block diagram of a typical digital signal

processing system is shown


CONVERTERSPrinciple of operation of a A-D converterSampling and filtering- The process of taking sufficient number of

discrete values at points on a waveform- Converts an analogue signal into a series of

impulses- Must be passed through a low-pass filter (anti-

aliasing filter to eliminate harmonic frequencies above Nyquist frequency)


CONVERTERS

Principle of operation of a A-D converterSampling and filtering: Nyquist frequency

Or in other words, the highest analogue frequency should be less than half the sampling frequency

frequencyNyquist is

2

max

max

a

asample

f

ff


CONVERTERS

Principle of operation of a A-D converter

Sample and hold:- The sampled level must

be held constant until the next sample occurs

- Results in a stairstep waveform


CONVERTERSPrinciple of

operation of a A-D converter

Quantization:- Process of

converting an analogue value to a code

- Each sampled value of the analogue signal is converted to a binary code


CONVERTERS

Principle of operation of a D-A converter (DAC)- Could be either parallel transfer or series transfer

of data- Parallel transfer: 4-bit codes are coupled out in

sequence as they are processed by digital processor and accepted by DAC at the same time

- Series transfer: 4-bit codes are sent out one bit at a time, following the other in sequence, accepted by DAC in sequence


CONVERTERSPrinciple of operation of a D-A converterBasic diagram of digital-to-analogue conversion is shown



operation of a single ramp

- Consist of ramp generator and BCD or binary counter

- A single slope ADC is shown


CONVERTERSPrinciple of operation of a

single ramp- At first reset signal is provided to ramp

generators- Counter reset to 0- Analogue input voltage is applied to

positive terminal of comparator- Comparator output goes HIGH, enabling

AND gate and ramp starts until exceeds input voltage

- Comparator goes LOW, disables AND gate, resets counter and ramp generator


CONVERTERS

Principle of operation of a single ramp

- e.g. for the ramp given the ramp is generated at 1V/ms

- The ramp is given as:

timeramp total theis and

x

V at voltage timeramp theis where

21

1

21

1

tt

t

V

V

tt

t

in

X

VX

t1

Vin

t1+t2


CONVERTERS

• Principle of operation of a single rampExample:A single ramp ADC is fed with Vin = 5V and

gives a ramp for 1.2ms. At 0.7ms, determine the output voltage of the ramp and the pulses produced if the frequency is 3MHz.


CONVERTERS• Principle of operation of a single rampSolution:

210037.0

9.252.1

7.0

;7.0

5,2.1

1

1

21

MHzmsftN

VVms

msV

mst

VVmstt

x

in



operation of a dual ramp

- A dual slope ADC is shown

- Consist of integrator (ramp generator), comparator, binary counter, output latch and reference voltage


CONVERTERSPrinciple of operation of a dual ramp- Assuming the counter is reset and

output at integrator is ‘0’- Positive input voltage applied,

assuming Vin is constant, capacitor charges linearly

- Counter reaches specified count and resets, switches to negative reference voltage, capacitor charges negative voltage, discharges linearly

- As capacitor discharges, counter advances from RESET state


CONVERTERSPrinciple of operation

of a dual ramp

1223

23

12

giving Thus,

1

asgiven is slope decreasing for theequation The

1

asgiven is slope rising for theequation The

3

2

2

1

ttVttV

ttRC

VdtV

RCV

ttRC

VdtV

RCV

inref

reft

t

refr

int

t

inr

Vr

t1 t2 t3


CONVERTERS

• Principle of operation of a dual rampExample:A dual slope ADC has a 100kΩ resistor and 1µF

capacitor. If the input voltage is 2V, calculate the output voltage after 1s. If a 5V reference voltage is fed to the integrator, determine the time range from t2 to t3


CONVERTERS• Principle of operation of a dual rampSolution:

stt

ttVsV

ttVttV

VV

VsFk

VV

ttRC

VV

sttFCkRVV

refin

ref

r

inramp

in

4.0

512

;5

2011100

2

;1,1,100,2

23

23

2312

12

12


CONVERTERSA continuously balanced

and successive approximation A-D converter

- A successive approximation ADC block diagram is shown

- Consisting DAC, successive approximation register, and comparator


CONVERTERSA continuously balanced and successive approximation A-

D converter- For a 4-bit successive approximation ADC as shown,

input bits are enabled one at a time, starting with the most significant bit (MSB)

- Comparator produces LOW when input signal voltage is lower than DAC output, register will RESET the bit

- Comparator produces HIGH when input signal voltage is higher than DAC output, register retains bit

- System does this from the MSB to the LSB, and once all done, conversion cycle is complete


CONVERTERSA continuously balanced and successive approximation

A-D converter

Output of DAC is 8V, greater than 5.1V input, output is LOW, MSB in SAR is reset

Output of DAC is 4V, less than 5.1V input, output is HIGH, bit is retained in SAR


CONVERTERSA continuously balanced and successive approximation

A-D converter

Output of DAC is 6V, greater than5.1V input, output is LOW, bit is reset to ‘0’

Output of DAC is 5V, binary code in register is 0101, approximate to 5.1V

Engineering

Digital design chap 6