Design of Optimized FIR Filter Using FCSD Representation

Neha Goel Ashutosh Nandi

Dept. of Electronics and Comm. Engg. National Institute of Technology Kurukshetra, India [email protected], [email protected]

Design of Optimized FIR Filter Using FCSD Representation

Keywords— FIR Filter, CSA, Barrel shifter, FCSD.

Abstract—This paper presents the design and implementation

of an eight order efficient FIR filter for wireless communication

system. In this work, factored canonical signed digit

representation (FCSD) is used for representing the filter

coefficients in order to reduce the design complexity, area and

delay of the FIR filter. Complexity of the system has been

reduced by replacing binary coefficients with FCSD

representation. Further area and delay has been improved by

replacing multiplication operation with add and shift method

where carry save adder (CSA) is used for addition of two

numbers and barrel shifter is used for shifting the data words.

Representation of coefficient in the FCSD format along with

fastest adder and shifter improves the performance of the system.

FIR filter has been designed using an equiripple method in

MATLAB and further synthesized on Spartan 3E XC3S500E

target FPGA device. Simulation results show that optimized

FCSD based FIR filter offers a less number of slices, look up

tables (LUTs) and flip-flops as compared to CSD and

conventional FCSD based FIR filter, in addition to enhanced

performance.

I. INTRODUCTION

Digital FIR filter is one of the essential components in

Digital Signal Processing (DSP) and communication

system. With an explosive growth in mobile

computing and multimedia applications, demand for low

power and high speed DSP system has seen a tremendous

growth [1]. Digital filters are used to modify the attributes of

signal by removing noise from the original signal and

shape the spectral characteristics of the resulting signal

[2]. Digital filters are very superior in level of performance as

they are highly stable, accurate and versatile as compared

to analog filter [3]. Moreover, Portable applications

require digital filter which operates at high data rate and low

power consumption as high power consumption reduces

battery lifetime, affecting device reliability and increasing

cool cost [4]. Due to this reason, the requirement of a digital

filter with optimized area, power and

delay is a challenging task. DSP applications require a large order FIR filter. However,

the complexity increases with increase in filter order because of

requirements of larger mathematical computations [5].

Therefore, real time implementation of this filter with precise value is posing as a serious challenge. In order to achieve efficient digital filter, order of FIR filter must be as small as possible. This paper focuses mainly on the FIR filter due to its absolute stability and linear phase response [6]. On the basis of hardware implementation, digital filter can be classified into two categories: multipliers based and memory based [7].

The main components of digital filter consist of registers to

save the samples of signals, adders to carry out sum operations

and multiplier for multiplication of the filter coefficients with

signal samples [8]. Despite the fact that designing of digital

filter seems simple, but the design bottleneck is its multiplier

block for speed, area and power consumption [9]. Complexity

is mainly dominated by coefficient multiplication operation

[10,11]. In order to reduce complexity, the filter

coefficients are represented in FCSD representation which

requires the least number of adders [12]. The filter can

be further optimized by using CSA and a barrel shifter

to achieve the operation of multiplication [13].

The rest of the paper is organized as follows: an overview of

FIR filter is given in section II. Section III consists of modules

for FIR filter. Section IV describes the proposed work for

filter optimization. In section V, simulation results

are discussed. Finally, section VI concludes the paper

by summarizing the main contributes.

Multipliers based design includes multiple constant multiplication (MCM) with add and shift operations.MCM based FIR filter uses transposed structure which increases the speed of the system.The area can be further saved by optimizing

coefficient with quantization technique. Memory based

design are divided into two approaches: distributed

arithmetic (DA) and Look Up table (LUT) method. The

DA based approach computes the inner product by

accumulating bit level partial results in the FIR

filter. The LUT based approach stores odd multiple

of input signal in ROM to realize constant

multiplications in MCM [7].

II. FIR FILTER

FIR filter is also known as non-recursive digital filters as they don’t have feedback [6]. Output of the FIR filter can be described by the following difference equation

FIR filters are digital filter with finite impulse response

which involves convolution operation given by equation [2]:

Y[n] = X[n]*H [n] (1)

3 NITTTR, Chandigarh EDIT-2015

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

Fig.1. Transposed form of FIR filter

Digital filter can be designed by calculating the filter

coefficient on the basis of filter order, sampling frequency,

pass band and stop band frequencies etc.[5]. Generally, power

consumption and the amount of computation are directly

proportional to filter order. Filter coefficient can be found with

the MATLAB FDA tool. Further, the filter can be designed by

different method including window functions, frequency

sampling and equiripple method [9]. Table I lists the

parameters of the low pass FIR filter and the corresponding

magnitude response is shown in Fig. 2.

TABLE I. FIR Filter Design Parameter

Filter Parameter Value

Design method Equiripple

Order 8

Density factor 20

Sampling frequency FS = 48000 Hz

Passband frequency Fpass = 9600Hz

Stopband frequency Fstop = 12000Hz

Passband weight Wpass = 1

Stopband weight Wstop = 1

The calculated coefficients of the proposed FIR filter are [9,

16, 17, 32, 33, 32, 17, 16, 9]. Coefficients are symmetric in

nature which further reduces area and power consumption [5].

Order for FIR filter is N while the length of the filter is N+1

which is similar to the number of the filter coefficients [10].

As the filter order increases, complexity of the system

increases by consuming more amount of time for signal

processing.

Where N and Hk represents the length and coefficients of the

FIR filter respectively [10].Basically FIR filter consists of two

structures, i.e., direct form and transposed form. In direct

form, signal samples are multiplied by filter coefficients and

combined together in adder block [7]. A modification over

direct form is transposed structure as shown in fig 1. In

transposed form, the same input signal is multiplied by several

coefficients. In the present work, transposed form is used

which reduces area and delay as compared to direct form [6].

(2)

k

K knxHnYN

)()(0

1

Fig.2. Lowpass FIR filter magnitude response

Three modules are needed for implementation of optimized

FIR filter, i.e., delay, addition and multiplication. Barrel

shifter is used to provide shift operation and CSA is used to

carry out a sum operation. The modules used for

implementation are:

Barrel shifter is an integral component in several

computing devices which is mainly used for shifting and

rotating multiple bits in a single clock. It can be designed with

the help of combinational logic circuits such as logic gates,

multiplexers and decoders. However, the MUX based barrel

shifter provides less delay and power when compared to other

circuits [13]. Therefore, in the present work, BS is designed

using multiplexers architecture. Shifting a data word by a

specific amount of shift is performed in one clock cycle.

Sequences of multiplexers are used to implement the barrel

shifter and the output of one mux is connected to the input of

the next mux that depends on the shift distance [7]. The data

word can be shifted up to 8 bits either in left or right direction. If the input pin is zero, then the observed output remains same, i.e., without applying shifting operation. On the other hand,


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B. Barrel Shiifter

CSA is mainly used for fast arithmetic in a DSP system for

addition of three or more binary numbers. In CSA, there is no

propagation delay as compared to the ripple carry adder and

carry look ahead adder [4]. For sufficient large value of n, it

provides results very quickly and relatively occupies less area

in comparison to normal adders. CSA includes full adders but

the carry output is taken out from each bit to form second

result vector instead of passing it to the next most significant

bit [8]. It consists of three numbers (x, y, z) as the input which

is added together and provides sum (s) and carry (c) as an

output. Hence, this adder is called as 3:2 compressor, where

the operation is performed in one time unit duration. In carry

save operation, the carry is passed until last step whereas

ordinary addition is done in the last step only. When CSA is

implemented on FPGA, then two LUTs are required for

generation of carry and sum bit where as single LUT is

required for the carry propagation adder [11]. Fig.3 represents

CSA that consists of 17 half adders and 15 full adders.

A. Carry Save Adder

III. MODULES FOR FIR FILTER

Fig.3. Block diagram for 16-bit Carry Save Adder

C. Conventional FCSD

Factored Canonical Signed Digit representation is a slight

modification over CSD. It replaces multiplier operation with

add and shift operations on the basis of prime factors of the

coefficients [9]. A combination of effective factorization and

CSD representation of filter coefficient leads to a reduction in

the number of adders which further hardware cost. It provides

a relatively greater reduction in filter area, but at the cost of

decreased clock speed [9].Increase in delay is the major

drawback of this algorithm. The Factored CSD algorithm

provides a trade-off between calculated complexity and

convergence [12]. Following example compares CSD and

FCSD algorithm.

y = 217*x

= (11011001)*x % 217 in binary form

= (1001’001’1’1’) *x % 217 in signed digit

= (256- 32-4-2-1) * x

= (x << 8) –(x << 5) – (x << 2) – (x << 1) – x

Cost of CSD = 4 adders

y = 217*x

= (7*31)* x

= (x << 3– x) *(x << 5 – x)

Cost of FCSD = 2 adders

It is concluded that, the number of adders has been reduced by

using FCSD instead of CSD technique. Therefore, we have

used FCSD formulation for reducing filter complexity.

IV. PROPOSED WORK FOR OPTIMIZED FIR FILTER

FIR filter based on FCSD technique is proposed that use carry

save adder and barrel shifter for addition and shifting

operations. FCSD technique used for coefficient

V. SIMULATION RESULTS

This section presents the simulation results of the proposed

FIR filter. A Low pass FIR Filter is designed using equiripple

method in MATLAB FDA tool box for calculation of

coefficients. The filter can be designed in two structures, i.e.

direct form and transposed form. We have used transposed

form structure which reduces the implementation cost in terms

of area and delay. FIR filter architecture has been designed

and implemented on Xilinx Spartan3E XC3S500E using

VHDL. This results in realizing an FIR filter which can be

operated at maximum frequency of 238.322 MHz by

consuming 79 slices. The characteristics of proposed FPGA

based FIR filter are summarized in table II along with the

comparison of the proposed filter with CSD and FCSD

technique.

TABLE II: Performance Comparison between different approaches

Parameter CSD FCSD Proposed

work

No. of slices 808 789 79

No. of flip-flops 510 512 126

No. of 4 input

LUT’s

1349 1290 146

Frequency (MHz) 43.814 44.911 238.322

Min. Period (ns) 22.824 22.266 4.196

As shown in table II, Number of slices has been reduced

from 789 to 79 in FCSD technique by consuming 126

numbers of flipflops. Proposed FCSD based FIR filter

occupies 146 number of look up tables as compared to FCSD

technique. In comparison to FCSD, this result shows the

enhanced performance in terms of speed and area due to

efficient utilization of embedded multiplier and LUTs inside

the device. Fig. 4 compares the proposed FCSD technique

with CSD and FCSD method in the form of bar graph. The

proposed work offers very less number of slices, LUTs and

flipflops as compared to other two techniques generated by

MATLAB. Simulation results shows that proposed filter

consumes 89.98% less number of slices, 88.682% less number

of LUTs and 75.39 % less number of flipflops as compared to

FCSD technique to provide cost effective filter. Time delay of

if the input is non zero, then output is shifted in either

specified direction. After shifting operation, all the partial

products (PP) are added together to achieve multiplication

operation. Thus, Performance of FIR filter is improved by use

of barrel shifter in terms of area and delay [13].

representation reduces the area of the filter as compared to the

CSD technique, but with the disadvantage of increased delay.

This propagation delay can be improved by using CSA and a

barrel shifter. For multiplication of filter coefficients with the

input signal add and shift method is used. Therefore, the

multiplier consists of one adder unit (CSA) and one shifter

unit (barrel shifter). The filter is processed step by step in

which coefficients are first factored and subsequently

represented in CSD format. CSA is used, when the input

signal is multiplied with filter coefficients and added together

in the last step. Optimization of FIR Filter considering area

and delay constraints has been achieved using FCSD

representation, CSA and barrel shifter. These combinations of

FCSD technique with CSA and BS can target significant

reduction in circuit complexity, area and delay.


5 NITTTR, Chandigarh EDIT-2015

the proposed filter has been improved considerably which in

turn increases the operational speed of the system. This

reduction in design complexity, area and delay of proposed

FCSD based filter can be viewed as a possible alternative for

circuit designer.

Fig.4. Bar graph representing CSD, FCSD and proposed work comparison

VI. CONCLUSION

The proposed FIR filter has been designed for 8 tap using

FCSD representation of filter coefficients. An optimized FIR

filter has been designed using barrel shifter and CSA in

VHDL which is further simulated on Xilinx Spartan3E based

XC3S500E target FPGA device. The results show that

optimized FCSD based FIR filter can be operated at a

maximum frequency of 238.322 MHz by consuming 79 slices,

126 flip-flops and 146 LUTs. Simulation results shows that

optimized filter occupies 89.98% less number of slices,

88.682% less number of LUTs and 75.39 % less number of

flipflops as compared to FCSD technique. Delay of the

optimized FIR filter has been reduced by 18.071 ns. It is

concluded that, use of FCSD representation in FIR filters

along with fastest adder and shifter can target significant

reduction in design complexity, area and delay when

compared to other approaches.

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400

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slices flip-flops LUT’s Frequency

(MHz)

CSD FCSD Proposed work


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