CSLA and WTM using GDI Technique

Guided By: Presented By:Mr. Sandeep Srivastav Dinesh kr Yadav

Nishant Yadav

Carry Select Adder (CSLA) is a fast adder which is

used in the data processing processors for performing fast

arithmetic operations.

The carry-select adder generally consists of two ripple

carry adders and multiplexers .

One RCA performs addition by assuming the input

carry is 0 and other RCA performs addition by assuming

the input carry is 1.

MUX select the output according to the carry from

previous stage

4-BIT CARRY SELECT ADDER(CSLA)

• Consider the Following Example

101 101 110

110 111 001

101

+110

101

+111

110

+001

111 0

000 1

100 0

101 1

1 011 0

1 100 1

1 100 100 111

Paper Name Publisher Description

Implementation and

comparision of effective

area architecture of CSA.

R. Priya and J. Senthil Kumar “2013 IEEE International Conference onemerging trends on computing ,communication and nanotechnology(ICECCN2013).

This is the main paper in which

conventional CSLA has been

implemented

Low Power Digital designusing modified GDImethod.

Padmanabhan Balasubramanian and Johince John,2006, IEEE.

This technique allows reducing

power consumption, propagation

delay, and area of digital circuits

GDI Technique : A

Power-Efficient Method

for Digital Circuits .

Kunal & Nidhi Kedia Department

of Electronics &

Telecommunication Engineering,

Synergy Institute of Engineering &

Technology, Dhenkanal, Odisha

This paper describes the design and

implementation of various digital

circuit using GDI technique

Mentor graphics Pyxis Schematic.

Technology Used 0.18 um

It consist of :-

Ripple Carry Adder

Multiplexer (4T)

Ripple Carry Adder is designed by

Full Adder(12T) connected in series.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 0 0 0 1 1 1 0 1 0 1 0 0 1 0 A

1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 B

1 0 1 1 1 0 0 0 1 1 1 1 1 0 0 1 0 Sum

1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 A

1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 B

1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 Sum

1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 A

0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 B

1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Sum

1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 A

0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 B

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Sum

INPUT AND ITS CORRESPONDING OUTPUT OF THE 16-BIT

CSLA

S0 0110

S1 1001

S2 0111

S3 0001

S4 1101

S5 1101

S6 1101

S7 1101

S8 1101

S9 0101

S10 0101

S11 0101

S12 1101

S13 1101

S14 1101

S15 0001

C_OUT 1110

OUTPUT COMBINATION OF THE 16-BIT CSLA

8 Transistor Full adder circuit is used.

MUX of 2 transistor is used.

The MUX and FA circuit is designed by using

GDI(gate diffusion input ) technique.

BASIC FUNCTIONS USING GDI

CELL

COMPARISON OF TRANSISTOR

COUNT OF GDI AND STATIC CMOS

N p G Output

Function

0 1 A A’ INV

0 B A A’B F1

B 1 A A’+B F2

1 B A A+B OR

B 0 A AB AND

C B A A’B+AC MUX

B’ B A A’B+B’A

XOR

B B’ A AB+A’B’

XNOR

fUNCTION

GDI CMOS

INV 2 2

F1 2 6

F2 2 6

OR 2 6

AND 2 6

MUX 2 14

XOR 4 12

XNOR 4 12

NAND 4 4

NOR 4 4

1.The GDI cell contains three inputs :

-G (common gate input of nMOS and pMOS),

-P (input to the source/drain of pMOS), and

-N (input to the source/drain of nMOS).

2. Bulks of both nMOS and pMOS are connected to GND and VDD respectively.

3. Basic GDI Cell

CONVENTIONAL

CSLA

CSLA USING GDI

TECHNIQUE

(WITHOUT BUFFER)

CSLA USING GDI

TECHNIQUE

(WITH BUFFER)

NUMBER OF

TRANSISTO

R

408 186

(54.41 % Saved

186+64=250 (In

worst case)

(38.72 %Saved)

DELAY 430.45 pS 217.35 pS

(49.50% Faster)

318.18 pS

(26.08 % Faster)

POWER 29.82 mW 27.169 mW 28.035 mW

0

100

200

300

400

500

ConventionalCSLA

CSLA Using GDI CSLA using GDIwith buffer

No. of transitors

No. of transitors

0

50

100

150

200

250

300

350

400

450

500

Conventional CSLA CSLA using GDI CSLA using GDI with Buffers

Delay

Delay

0

5

10

15

20

25

30

35


Power

Power

0

2000

4000

6000

8000

10000

12000

14000


PDP

Power

Delay

The Wallace tree has three steps:

o Partial Product Generation.

o Wallace Tree Implementation.

o Addition using RCA.

BLOCK DIAGRAM OF WALLACE TREE

MULTIPLIER

WALLACE TREE MULTIPLIER

SCHEMATIC OF WALLACE TREE MULTIPLIER

USING CMOS

SYMBOL OF WALLACE TREE MULTIPLIER USING

CMOS

A3

=1

A2

=1

A1

=1

A0

=1

B3

=1

B2

=1

B1

=1

B0

=1

1 1 1 1

1 1 1 1

1 1 1 1

1 1 1 1

1 1 1 0 0 0 0 1

P7 P6 P5 P4 P3 P2 P1 P0

A=1111

B=1111 P=11100001

A=1000

B=1000 P=01000000

A=0001

B=0001 P=00000001

O/P WAVEFORM OF WALLACE TREE MULTIPLIER

USING CMOS

CONTD……………..

SCHEMATIC OF WALLACE TREE MULTIPLIER

USING GDI

CONVENTIONAL

WALLACE TREE

MULTIPIER

WALLACE TREE USING

GDI TECHNIQUE

NUMBER OF

TRANSISTOR

352 276

(21.5 % Saved)

DELAY 570.60 pS 1.413 nS (Slower)

POWER 9.89 mW 8.23mW

Arithmetic Logic Unit

High Speed Multiplications

Advanced Microprocessors

1 Design of a Low Power, High Speed, Energy Efficient Full Adder Using Modified GDI and MVT Scheme in 45nm Technology International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)

2 “Low Power Digital design using modified GDI method” PadmanabhanBalasubramanian and Johince John,2006, IEEE.

3 Low-Power and High Speed CPL-CSA Adder “N V Vijaya Krishna Boppana, Saiyu Ren, Henry Chen” Department of

Electrical Engineering, Wright State University, Dayton, Ohio, USA

4 Implementation and comparision of effective area architecture of CSA, R. Priya and J. Senthil Kumar “2013 IEEE International Conference on emerging trends on computing ,communication and nano technology ICECCN2013

“Multipliers using low power adder cells using 180nm Technology” Jyoti

Gupta,Amit Grover, Garish Kumar Wadhwa, 2013 International Symposium

on Computational and Business Intelligence

“Implementation of Low Power 8-Bit Multiplier using Gate Diffusion Input

Logic” B.N. Manjunatha Reddy, H. N. Sheshagiri, Dr.B.R.VijayaKumar,

2014 IEEE 17th International Conference on Computational Science and

Engineering

THANK YOU