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Notes: Verilog Part 3 Prepared By: Jay Baxi

Notes: Verilog Part 3

6 CHAPTER 6

6.1 CONTINUOUS ASSIGNMENT A continuous assignment is the most basic statement in the dataflow modelling. It is used to

drive a value onto a net. The syntax is as given below

countinuous_assign ::= assign [ drive_strength ] [delay3] list of net assignments;

list of net assignments ::= net_assignments { , net_assignments}

net_assignments ::= net_lvalue = expression

The assignment statements begins with keyword assign.

The drive strength and delay are optional.

Things that are to be kept in mind while writing an assign statement are:

The LHS must always be a scalar or a vector net or a concatenation

of both the nets. It cannot be a scalar or a vector register.

Continuous assignments are always active. The value is evaluated as

soon as there are changes in the RHS operand.

The operands on the RHS can be reg or wire.

Delay value are specified in time units

6.1.1 Implicit Continuous Assignment

Instead of declaring a net and then assigning a value to it, Verilog provides a shortcut by

which a value can be placed on the net as soon as the net is declared.

wire out;

assign out = in1 & in2; //regular continuous assignments

//is same as

wire out = in1 & in2; //implicit continuous assignments

6.1.2 Implicit Net Declaration

If a signal name is used to the left of continuous assignment, an implicit net declaration

will be inferred for that signal name.

If the net is connected to the module port, the width of the inferred net will be equal to

the that of the module port.

wire i1,i2;

assign out = i1 & i2;

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6.2 DELAYS

6.2.1 Regular Assignment Delays

The first method is to give the delay value after the keyword assign.

Any change in the value of in1 and/or in2 will result in a delay of 10 time

units in the output.

If in1 and/or in2 change before the 10 time units, the value will not be

taken for the process and will wait for the re-computation.

6.2.2 Implicit Continuous Assignment Delay

An equivalent method is to use an implicit continuous assignment to

specify both a delay and an assignment on the net.

6.2.3 Net Declaration Delay

A delay can be specified on a net without putting a continuous

assignment on the net. If a delay is specified on a net out then any value

change applied to the net out is delayed accordingly.

wire out;

assign #10 out = in1 & in2; //Regular Assignment Delay

wire #10 out = in1 & in2; //Implicit Continuous Assignment Delay

wire #10 out;

assign out = in1 & in2; //Net Declaration Delay

6.3 EXPRESSIONS, OPERATORS AND OPERANDS Expressions are constructs that are formed by combination of operators and operands to

produce a result.

Operands are constructs that assume any of the data types and participate in expressions to

generate desired results.

Operators are the constructs that operate on operands to produce desired result. They can

be unary, binary or ternary operators.

6.4 TYPES OF OPERATORS

6.4.1 Arithmetic Operators

Various Arithmetic operators are *(multiply), /(divide), +(addition), -

(subtraction), %(modulo), **(power)

If any operand bit is “x”, the result of entire expression is “x”.

‘+’ and ‘-‘ can operate as unary operators to indicate the sign of the

given number.

6.4.2 Logical Operators

Logical Operators provided by Verilog are &&(logical AND), ||

(logical OR) and !(logical Negation).

If any one bit of the operand is “x”, the result of the entire

expression is “x”. It is usually treated by simulators as false

condition.

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6.4.3 Relational Operators

The various relational operators are >(greater than), <(less than),

>=(greater than or equal to), <=(less than or equal to).

It returns 1 if the argument is true and 0 if false. However, when

there is one unknown bit, it results in “x”.

6.4.4 Equality Operators

There are four equality operators provided by Verilog.

==(equal to), !=(not equal to), ===(case equality) and !==(case

inequality).

== and != result in unknown in case of “x” and “z’.

=== and !=== check each and every bit including “x” and “z”.

6.4.5 Bitwise Operators

Bitwise operators are ~(negation), &(and), !(or), ^(xor), ~^ or

^~(xnor).

Bitwise operators perform bit by bit operation.

They take a bit from an operand and perform the operation on the

corresponding bit of the other operand.

The operations on “x” and “z” are shown in the truth table below.

6.4.5.1 Bitwise AND

Bitwise AND 0 1 X

0 0 0 0

1 0 1 X

X 0 X x

6.4.5.2 Bitwise OR

Bitwise OR 0 1 X

0 0 1 X

1 1 1 1

X X 1 x

6.4.5.3 Bitwise XOR

Bitwise XOR 0 1 X

0 0 1 X

1 1 0 X

X X X X

6.4.5.4 Bitwise XNOR

Bitwise XNOR 0 1 X

0 1 0 X

1 0 1 X

X X X X

6.4.6 Reduction Operators

Reduction operators are same as the Bitwise operators except the

addition of two new operators ~|(nor) and ~%(nand).

The only difference between the bitwise and the reduction

operators is that the result of reduction operator is just one bit.

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It performs the assigned operation on each of its bits starting from

the leftmost bit and produces the final 1bit result.

6.4.7 Shift Operators

>> (Logical Right): It shifts the number of bits mentioned after the

operator in the right direction, thereby appending the leftmost bits

by 0.

<< (Logical Left): It shifts the number of bits mentioned after the

operator in the left direction, thereby appending the rightmost bits

by 0.

6.4.8 Concatenation Operator

This is used to append multiple operands.

The operand must be sized. Unsized operands are not allowed

because the size is needed for computation of the size of the result.

They are expressed as operands between braces with commas

separating the operands.

Operands can be of any data types.

6.4.9 Replication Operator

Repetitive concatenation of same number can be expressed by using

a replication constant. This specifies how many times to replicate

the number within the brackets. ( { , }).

6.4.10 Conditional Operator

Conditional Operator is a combination of ?:

Condition_expression?(true_expression):(false_expression)

condition_expression is evaluated first, if that is true,

true_expression is the result otherwise the result is the

false_expression.

The precedence of the operators is same as that of these operators in C Language.

6.5 EXAMPLES

6.5.1 Multiplexer using a conditional operator

A Multiplexer using a conditional operator is the simplest and the smallest logic for

designing a multiplexer. The code for the same is given in Multiplexer using conditional

operator.

6.5.2 4-bit Full Adder

The dataflow 4-bit Full Adder using the dataflow operators is given in Full Adder using Data

Flow Operators.

6.5.2.1 Carry Lookahead

The Carry lookahead is given for solution of timing problems for

carry propagation.