Architecture and Comparison of

various Processors Deepak John

SJCET-Pala

80186 The 80186 double the performance of 8086.

80186 = 8086 + several additional chips

i. Clock generator

ii. Two independent high-speed DMA channels

iii. Programmable interrupt controller

iv. Three programmable 16-bit timers

v. Programmable wait state generator

vi. Local bus controller

vii. Programmable memory and peripheral chip-select logic

The total addressable memory size is 1MB.

The instruction set is upward code compatible with the 8086/88 family.

Clock Generator:

on-chip clock generator / crystal oscillator circuit.

a crystal connected at the 80186 X1 X2 pins is divided by 2 internally

Programmable Interrupt Controller:

allows internal and external interrupts and controls up to two external

8259A PICs.

Accepts interrupts only in the master mode.

five dedicated pins for external interrupts. These pins are NMI,INT0,

INT1, INT2/INTA0#, and INT3/NTA#.

NMI is the only non-maskable interrupt.

Timers:

contains three fully programmable 16-bit timers

The timers 0 and 1 programmed to count external events and driven by

either the master clock of the 80186 or by an external clock

timer 2 is internal and clocked by the master clock.

Registers of the 8086/80286

Programmable DMA Unit:

contains two DMA channels,

Each DMA channel contains 20-bit source and destination pointers

used to address the source and destination of the data transferred.

A 16-bit transfer count register is included in each channel, which

contains a number of DMA transfers to be performed.

Data can be transferred either by the byte or by 16-bit words.

contains a 16-bit control register, it specifies information such as data

rate,DMA operation etc:

Programmable chip selection unit:

The chip selection is a built-in programmable memory and I/O

decoder.

It has 6 output lines to select memory, 7 lines to select I/O

Bus Interface Unit

The BIU provides various functions, including generation of the

memory and I/O addresses for the transfer of data between outside the

CPU, and the EU.

The 80186 provides eight addressing modes. These include register,

immediate, direct, register indirect (SI, DI, BX, or BP), based (BX

or BP), indexed (SI or DI),based indexed, and based indexed with

displacement modes.

7 new instructions beyond the 8086.

PUSHA push all registers

POPA pop all registers

INS input a string

OUTS output a string

ENTER block enter

LEAVE block leave

BOUND bounds check

80286 designed for multiuser and multitasking environments.

addresses 16 M Byte of physical memory and 1G Bytes of virtual

memory by using its memory-management system.

Memory management , virtual memory management & protection

abilities.

Like the 80186, the 80286 doesn’t incorporate internal peripherals;

instead it contains a memory management unit (MMU).

The clock is provided by the 82284 clock generator, and the system

control signals are provided by the 82288 system bus controller

operates in both the real and protected modes.

i. In the real mode, the 80286 addresses a 1MByte memory address

space,

ii. In the protected mode, the 80286 addresses a16MByte memory

space.

Register organization of 80286

The 80286 CPU contains almost the same set of registers, as in 8086.

1. Eight 16-bit general purpose registers.

2. Four 16 bit segment registers.

3. Status and control register.

4. Instruction pointer.

Functional Parts

1. Address unit

2. Bus unit

3. Instruction unit

4. Execution unit

Address Unit

Calculate the physical addresses of the instruction and data that the

CPU want to access.

Address lines derived by this unit may be used to address different

peripherals.

Physical address computed by the address unit is handed over to the

BUS unit.

Bus Unit

Transmit the physical address over address bus A0 – A23.

Prefetcher module in the bus unit performs this task of prefetching.

Bus controller controls the prefetcher module. Fetched instructions are arranged in a 6 – byte prefetch queue.

Processor Extension Interface Module–Take care of communication b/w CPU and a coprocessor.

Instruction Unit

Receive arranged instructions from 6 byte prefetch queue.

Instruction decoder decodes the instruction one by one and are

latched onto a decoded instruction queue.

O/p of the decoding circuit drives a control circuit in the Execution

unit.

Execution unit

Control unit is responsible for executing the instructions received

from the decoded instruction queue.

Contains Register Bank.

ALU is the heart of execution unit,After execution ALU sends the

result either over data bus or back to the register bank.

Address unit

is responsible for calculating the physical address of instructions and

data that the CPU wants to access.

address lines derived by this unit may be used to address different

peripherals.

The physical address computed by the address unit is handed over to

the bus unit (BU) of the CPU.

Interrupts of 80286

The Interrupts of 80286 may be divided into

1. Maskable Interrupt INTR

2. Non-Maskable Interrupt NMI

3. Single Step Interrupt(is an internal interrupt that comes into action)

Interrupt Priorities:

New instructions in 80286

CLTS (CLear TaSk) – clears the TS (Task - Switched) flag bit to a

logic 0.

LAR (Load Access Rights) Instruction reads the segment descriptor

and place a copy of the access rights byte into a 16 bit register.

LSL (Load Segment Limit) instruction Loads a user – specified

register with the segment limit.

VERR (VERify for Read access) instruction verifies that a segment

can be read.

VERW (VERify for Write access) instruction is used to verify that a

segment can be written.

ARPL (Adjust Request Privilege Level )instruction is used to test a

selector so that the privilege level of the requested selector is not

violated.

80386 enhanced version of the 80286 microprocessor and includes a

memory-management unit is enhanced to provide memory paging.

has a physical memory size of 4GBytes that can be addressed as a

virtual memory with up to 64TBytes.

allows the memory system to begin fetching the next instruction or

data before the current is completed, This increases access time, thus

reducing the speed of the memory.

memory manager is similar to the 80286,except the physical addresses

generated by the MMU are 32 bits wide instead of 24-bits

includes 32-bit extended registers and a 32-bit address and data bus.

These extended registers include EAX, EBX, ECX, EDX, EBP, ESP,

EDI, ESI, EIP and EFLAGS.

The 80386 has three processing modes:

1. Protected Mode.

2. Real-Address Mode.

3. Virtual 8086 Mode.

Protected mode

is the natural 32-bit environment.

In this mode all instructions and features are available.

Real-Address Mode.

allows the microprocessor to address data in the first 1MByte of

memory

Virtual 8086 Mode.

is a dynamic mode in the sense that the processor can switch

repeatedly and rapidly between V86 mode and protected mode.

Central processing unit

is further divided into Execution unit and Instruction unit

i. Execution unit has 8 General purpose and 8 Special purpose

registers which are either used for handling data or calculating

offset addresses.

ii. Instruction unit decodes the opcode bytes received from the 16-

byte instruction code queue and arranges them in a 3- instruction

decoded instruction queue.

Bus interface unit

is further divided into Prefetch unit and Bus control unit

Bus control unit controls the access of the bus.

The address driver drives the bus enable and address signal A0 – A31.

The prefetch unit performs a mechanism known as an instruction

queue(FIFO).

Memory management unit

consists of a Segmentation unit and a Paging unit.

i. Segmentation unit

allows the use of two address components, viz. segment and

offset for relocability and sharing of code and data.

Segmentation unit allows segments of size 4Gbytes at max.

ii. Paging unit

i. organizes the physical memory in terms of pages of 4kbytes size

each.

ii. Paging unit works under the control of the segmentation unit, i.e.

each segment is further divided into pages.

iii. converts linear addresses into physical addresses.

Register Organisation

80486

One of the most obvious feature included in a 80486 is a built in math

coprocessor allows it to execute math instructions.

8Kbyte code and data cache.

168 pin.

A new feature found in the 80486 in the BIST (built-in self-test) that

tests the microprocessor, coprocessor, and cache at reset time

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Pentium Processor basic features

The Pentium microprocessor is almost identical to the earlier 80386

and 80486 microprocessors.

The main difference is that the Pentium has been modified internally

to contain a dual cache (instruction and data) and a dual integer unit.

operates at a higher clock speed of 66 MHz.

64 – bits wide data bus and contains eight byte-wide memory banks

selected with bank enable signals,

Memory access time, without wait states, is only about 18 ns in the

66 MHz Pentium.

The superscalar structure of the Pentium contains three independent

processing units: a floating point processor and two integer

processing units

A new mode of operation called the System Memory Management

(SMM) mode has been added to the Pentium. It is intended for

high-level system functions such as power management and

security.

The Built-in Self-test (BIST) allows the Pentium to be tested when

power is first applied to the system Allows 4MByte memory pages

instead of the 4KByte pages.

Intel's 5th generation of x86 line of processors.

Binary compatible with older generations of x86 processors.

Branch prediction.

Dual processor support.

Superscalar architecture (2 pipe-lined integer units + 1 pipe-lined

FPU).

FPU performance enhancements.

Separate 16 KB code and 16 KB data cache.

Power management features.

3.3V input/output level and 2.8V core.

New 67 MMX instructions and 4 new 64 bit data types.

The Pentium II brand refers to Intel's sixth-generation micro

architecture .

improved version of the first P6-generation core of the Pentium

Pro, which contained 5.5 million transistors.

Pentium II CPU was packaged in a slot-based module rather than

a CPU socket.

The improved 16-bit performance and MMX support made it a

better choice for consumer-level operating systems, such

as Windows 9x.

All versions of the Pentium II are packaged on

special daughterboard that plugs into a card-edge processor slot on

the motherboard.

The Pentium III brand refers to Intel's 32-bit x86 desktop and

mobile microprocessors based on the sixth-generation Intel

P6 micro architecture .

packaged in SECC 2 package, plugged into Slot 1 connector, used

the same 0.25 micron manufacturing technology.

It had Processor Serial Number, or PSN. Due to privacy concerns

this feature was by default disabled on many motherboards.

based on completely new Net Burst micro-architecture.

One of key features of Pentium 4 processor was Hyper-Pipelined

Technology - 20-stage pipeline, that was two times longer than in

previous generation of Pentium processors.

Trace Execution Cache, Advanced Transfer Cache, Enhanced

Branch prediction, Quad Data Rate bus and Hyper-Threading

technology.

have only one CPU core. Dual-core microprocessors based on Net

Burst micro architecture were branded as Pentium D.

Pentium Pro Processor basic features enhanced version of the Pentium microprocessor that contains not

only the level 1 caches found inside the Pentium, but the level 2

cache of 256 K or 512K found on most main boards.

operates using the same 66 MHz bus speed .

It uses an internal clock generator to multiply the bus speed by

various factors to obtain higher internal execution speeds.

The only significant software difference between the Pentium Pro

and earlier microprocessors is the addition of FCMOV and CMOV

instructions.

The only hardware difference between the Pentium Pro and earlier

microprocessors is the addition of 2M paging and four extra address

lines that allow access to a memory address space of 64G Bytes