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Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis Christian Pilato, Gianluca Palermo, Antonino Tumeo, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi

Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis

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Abstract—In evolutionary high-level synthesis, design solutionshave to be evaluated to extract information about somefigures of merit (such as performance, area, etc.) and to allowthe genetic algorithm to evolve and converge to Pareto-optimalsolutions. Since the execution time of such evaluations increaseswith the complexity of the specification, this could lead tounacceptable execution time of the overall methodology. Thispaper presents a model to exploit fitness inheritance in a multiobjectiveoptimization algorithm (i.e. NSGA-II [1]) by substitutingthe expensive real evaluations with an estimation basedon neighbors in an hypothetical design space. The estimationsare based on a measure of distance between individuals anda weighted average on fitnesses of closer ones. The resultsshows that the Pareto-optimal set obtained by applying theproposed model good approximates the set obtained withoutfitness inheritance and overall execution time is reduced morethan 25% in average.

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Page 1: Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis

Fitness Inheritance in Evolutionary and Multi-Objective High-Level SynthesisChristian Pilato, Gianluca Palermo, Antonino Tumeo, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi

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Pier Luca Lanzi

High Level Synthesis

“High-Level Synthesis means going from an algorithmic level specification of a behaviour of a digital system to a register level structure that implements that behavior”.McFarland, et al., Proc. IEEE, February 1990.

Behavioral specification

Design constraints

ResourceLibrary

Datapath& Controller

ObjectivesScheduling

Allocation Binding

Controller Synthesis

High-Level Synthesis tool

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High Level Synthesis

Operation SchedulingProvides the cycle steps in which operations start their execution

Resource AllocationAssigns operations and values to hardware components, interconnects them

Controller SynthesisProvides the logic to issue datapath operations, based on the control flow

Develop polynomial-time algorithms to optimally solve each task?

We wish! Unfortunately, these problems are NP-complete

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Motivations

All the sub-tasks are NP-complete: no efficient algorithmsInterconnection have to be considered: up to 80% of final areaAll the tasks are closely interdependentMost of the information is available only at the end of the syntesis

GuidelinesHeuristics approaches with feedback informationGenetic algorithms, reducing to single-objective (weighted average) is not efficientNSGA-II

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The Proposed Methodology

Fitness is computed using a full synthesis flow

Individuals encode information to perform an

entire synthesis cycle

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Chromosome encoding

Encodes all the information needed for synthesis computations

Allocation BindingRepresents the mapping between the operations to be performed and the functional unit where it will be executed.Partially controls final area occupationInfluences Scheduling, Register Allocation and Interconnection Allocation

Second part identified the completion algorithmsScheduling (SchedA), Register Allocation (RegA) and Interconnection Optimization (ConnA) ‏

Allocationand binding Completion steps

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Completion Algorithms

Scheduling (SchedA) ‏Integer Linear ProgrammingList Based

Register Allocation (RegA)‏Left-edge algorithmSequential vertex coloringHeuristic clique-covering

Interconnection Optimization (ConnA) ‏Port swapping among inputs of a functional unit (if the operation is commutative) ‏

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Cost function

The fitness function has two components area and time

Time(x)‏Estimation of the worst case execution time of solution xComputed as the longest path in the scheduled CDG+DFG

Area(x)‏Estimation of the area occupied by solution xPreferred an estimation rather than real values because Logic Synthesis performed with FPGA tools is slowComputed using a modified, already existing, area model.*

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Problem independent elements

Initial populationRandomly generatedSeeded by interesting candidates

Ranking and SelectionSolution sorted in different levels according to fitness valuesRanking selection emphasize good solution pointsAccelerated using fast-non-dominated-sort of NSGA-II

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The Genetic Algorithm

Elitist

NSGA-II applies a crowded-comparison operator

Uniform crossover Applied to the 80% of the populationMix solution bindingsMix genes that represent completion algorithms

Mutation Applied to the 10% of the populationEach gene is modified with P=0.01%Alleles are mutated to admissible valuesOperation: new bindingAlgorithm: another algorithm is choosed to perform the corresponding step

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The Goal: Reduce Execution Time!

Even if logic synthesis is not performed, and area of the final circuit is extimated through a model, execution time for each evaluation can reach several seconds

Large examples can take hours to perform the exploration

Use fitness inheritance to reduce the number of evaluations

Substitute evaluations with inherited estimations

Two approachesEstimations based on all the individuals evaluated from the beginning of the algorithm (ancestors) ‏Estimations based only on the individuals evaluated in the latest generation (parents)‏

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Distance metric:

Consider only nearindividuals:

Weighted averageon different objectives:

Delta function

Normalized distance that represents diversity

Analogy with N-dim hypersphere

remembers Physics equations, with where value 1 is considered as infinite distance (individual is too different, so it has no contribution to fitness)

Fitness Inheritance Model

Two types of inheritanceBased on ancestorsBased on parents

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Test Problems & Experimental Settings

Typical high level synthesis benchmarks

2D-DCT, RGB-to-YUV from the JPEG compression algorithmMost computationally intensive phasesRGB to YUV can be unrolled: factor x2 and x4

EWF: fifth order elliptic wave filter

Population size: 1000 individuals, evolving up to max 200 generationsTarget: Xilinx Field Programmable Gate ArraysSearching for the best area-performance trade-offs for the specific device and architecture

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EWF (Pareto)‏

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DCT (Pareto)‏

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RGBtoYUVx4 (Pareto solutions with and without inheritance) ‏

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Overall execution time/chromosome size

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Fitness evaluation time generation by generation (EWF)‏

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Fitness evaluation time generation by generation (RGBtoYUVx4)‏

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Inheritance benefits

Number of fitness function evaluations (p=0,557)‏

Execution time for fitness and overall execution

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Conclusions

High level synthesis based on NSGA-II and fitness inheritance

The use of fitness inheritance No substantial decrease in the overall quality25% reduction of the execution time

Future workPopulation sizingScalability