VERILOG HDL
1 ENGN3213: Digital Systems and Microprocessors L#5-6
Some Reference Material (mostly advanced)
\vspace{10mm}http://engnet.anu.edu.au/DEcourses/engn3213/Documen ts/VERILOG/
➤ VerilogIntro SASAKI.pdf - Very simple introduction which emphasises the ground rulesfor good coding style
➤ coding and synthesis with verilog OREGAN.pdf - explains ways to build somecommon circuits
2 ENGN3213: Digital Systems and Microprocessors L#5-6
Ways to represent hardware
➤ Schematics
➤ Use Hardware Description Language
3 ENGN3213: Digital Systems and Microprocessors L#5-6
What are Hardware Description Languages (HDLs)?
➤ Textual representation of a logic design but has various levels ofabstraction
➤ Not programming languages YOU MUST THINK DIFFERENTLY
➤ Similar development chain➤ Compiler → assembly code → binary machine code➤ Synthesis tool: HDL source → gate-level specification → hardware
4 ENGN3213: Digital Systems and Microprocessors L#5-6
Why use HDLs?
➤ Easier to make system abstractions (VIZ the combinational andsequential logic abstractions)
➤ Easy to write and edit
➤ Compact
➤ Don’t have to follow wires on a schematic
➤ Easy to analyse
➤ Why not to use an HDL
➤ To avoid understanding the hardware
➤ A schematic can be a complex work of art
5 ENGN3213: Digital Systems and Microprocessors L#5-6
HDL HIstory
➤ 1970s: First HDLs➤ Late 1970s: VHDL
➤ VHDL = VHSIC HDL = Very High Speed Integrated Circuit HDL➤ VHDL inspired by programming languages of the day (Ada)
➤ 1980s:➤ Verilog first introduced➤ Verilog inspired by the C programming language➤ VHDL standardized
➤ 1990-2000s:➤ Verilog standardized (Verilog-1995 standard)➤ Continued evolution (Verilog-2001 standard)➤ ICARUS Verilog needs plenty of Verilog-2001 compliance - work in
6 ENGN3213: Digital Systems and Microprocessors L#5-6
About Verilog...
➤ A surprisingly big language
➤ lots of features for simulation and synthesis of hardware.
➤ We are going to learn a focussed subset of VERILOG
➤ Focus on synthesisable constructs
➤ Initially restrict some features just because they are not necessary
➤ If you haven’t seen it in lectures, ask me before you use it
7 ENGN3213: Digital Systems and Microprocessors L#5-6
Why an HDL is not a Programming Language
➤ In a program, we start at the beginning (e.g. ’main’), and we proceedsequentially through the code as directed
➤ The program represents an algorithm, a step-by-step sequence of actionsto solve some problem
...for (i = 0; i<10; i=i+1) {
if (newPattern == oldPattern[i]) match = i;}
...
➤ Hardware is all active at once; there is no starting point
...always @(X) Y = X;always @(Y) Z = Y;
...
8 ENGN3213: Digital Systems and Microprocessors L#5-6
A Block Schematic
9 ENGN3213: Digital Systems and Microprocessors L#5-6
Verilog Program Structure
10 ENGN3213: Digital Systems and Microprocessors L#5-6
What do you really have to know to understand and use VERILOG?
➤ VERILOG can be for SYNTHESIS or for SIMULATION: you must lear nto distinguish them
➤ SYNTHESISABLE VERILOG runs CONCURRENTLY in hardware
➤ VERILOG has some basic properties:
1. COMBINATIONAL vs SEQUENTIAL
2. WIRES vs REGS (not important but basic)
11 ENGN3213: Digital Systems and Microprocessors L#5-6
What are the usual problems of VERILOG that you need to look ou t for?
➤ You are breaking with the COMBINATIONAL / SEQUENTIAL paradi gm
➤ Your code is poorly synthesisable: Two ways:
1. You are using simulation-only constructs in your code forsynthesis.
2. YOUR CODE IS FOR SYNTHESIS BUT TRANSLATES BADLY INTOHARDWARE - THE USUAL PROBLEM
12 ENGN3213: Digital Systems and Microprocessors L#5-6
WIRES and REGS
➤ Variables in VERILOG are either WIRES or REGS➤ Neither of these is like a variable in C➤ WIRES
➤ A WIRE is a through-connection within or to a module. The input andoutput ports are WIREs. ASSIGNS assign to WIRES
➤ REGS➤ The combinational and sequential paradigms in terms of ALWAYS
blocks imply a persistance to the variables they assign to➤ Example: the variables on the left hand sign of statements in side
ALWAYS blocks are REGS➤ REGS have persistance and store VALUES from one event to the
next➤ REGS are not registers in the electronic sense
13 ENGN3213: Digital Systems and Microprocessors L#5-6
WIRES and REGS
ComponentValue: V = 8’h1a
WIRE
REG: V = 8’h1a
WIREModule
Circuit Schematic VERILOG
14 ENGN3213: Digital Systems and Microprocessors L#5-6
Modelling sequential and combinational circuits
15 ENGN3213: Digital Systems and Microprocessors L#5-6
VERILOG by example: MULTIPLEXER (combinational)
module mux(sel, a, b, c);input a;input b;input sel;output c;reg c;always@(a or b or sel)
if (sel == 1’b1)c = a;
elsec = b;
// c = sel ? a : b;
endmodule
a
b
c
Sel
16 ENGN3213: Digital Systems and Microprocessors L#5-6
VERILOG by example: D-type Flip Flop (sequential)
module dff(clk, d, q);input clk;input d;output q;reg q;always@(posedge clk)
q <= d;endmodule
d q
clk
17 ENGN3213: Digital Systems and Microprocessors L#5-6
ASSIGNS... an alternative construct for treating SIMPLE combinational circuits
module inv(a, y);input [3:0] a;output [3:0] y;assign y = ˜a;
endmodule
module and8(a, y);input [7:0] a;output y;assign y = &a;
endmodule;
18 ENGN3213: Digital Systems and Microprocessors L#5-6
Tristate Buffers
➤ Tristate buffers are multiplexers that have the possibility of producing anopen circuit output
Bus
tristate tristate tristate
open circuit
19 ENGN3213: Digital Systems and Microprocessors L#5-6
Tristate Buffers
module tristate(a, en, y);input [3:0] a;input en;output [3:0] y;assign y = en ? a : 4’bz;
endmodule
module mux2(d0, d1, s, y);input [3:0] d0, d1;input s;output [3:0] y;tristate t0(d0, ˜s, y); //Instantiation -> hierarchicaltristate t1(d1, s, y); //Instantiation -> hierarchical
endmodule
20 ENGN3213: Digital Systems and Microprocessors L#5-6
Combinational logic// -----------------------------// Using a regwire a,b;reg c;always @ (a or b)
c = a & b;
// -----------------------------// Using a wirewire a,b,c;assign c = a & b;
// -----------------------------// using a built in primitive (without instance name)reg a,b;wire c;and(c,a,b); // output is always first in the list
// -----------------------------// using a built in primitive (with instance name)reg a,b;wire c;and u1(c,a,b); // output is always first in the list
21 ENGN3213: Digital Systems and Microprocessors L#5-6
Top module: Ledflasher
module ledflash(clk,LEDS);
input clk;output [7:0] LEDS;reg [23:0] counter;reg [7:0] LEDS;
//A counter...always @(posedge clk) counter<=counter+24’b1;
always @(posedge clk) beginif(counter[23]) LEDS[0] <= 1; else LEDS[0] <= 0;if(counter[22]) LEDS[1] <= 1; else LEDS[1] <= 0;if(counter[21]) LEDS[2] <= 1; else LEDS[2] <= 0;if(counter[20]) LEDS[3] <= 1; else LEDS[3] <= 0;if(counter[19]) LEDS[4] <= 1; else LEDS[4] <= 0;if(counter[18]) LEDS[5] <= 1; else LEDS[5] <= 0;if(counter[17]) LEDS[6] <= 1; else LEDS[6] <= 0;if(counter[16]) LEDS[7] <= 1; else LEDS[7] <= 0;
end
endmodule
22 ENGN3213: Digital Systems and Microprocessors L#5-6
Top module: UCF file
NET "clk" LOC = "C9" ;NET "LEDS[0]" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DR IVE = 8 ;NET "LEDS[1]" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DR IVE = 8 ;NET "LEDS[2]" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DR IVE = 8 ;NET "LEDS[3]" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DR IVE = 8 ;NET "LEDS[4]" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DR IVE = 8 ;NET "LEDS[5]" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DR IVE = 8 ;NET "LEDS[6]" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRI VE = 8 ;NET "LEDS[7]" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRI VE = 8 ;
23 ENGN3213: Digital Systems and Microprocessors L#5-6
Example: Counter
module cntr_3bit( clk, rst, count);
input clk;input rst;
wire rst;
parameter zero = 4’b0000;parameter one = 4’b0001;
output [3:0] count;reg [3:0] count;
always @(posedge clk or rst) begin
if (rst) begincount <= zero;
end else begincount <= count + one;
end
end
endmodule
24 ENGN3213: Digital Systems and Microprocessors L#5-6
Example: Counter: test benchmodule TB_cntr_3bit;reg clk;reg rst;wire [3:0] cnt;
cntr_3bit c3b(clk, rst, cnt);initial beginclk = 0;rst = 1;#1rst = 0;$display("\t\t time \t clk \t rst \t count");forever #2 clk = ˜clk;endinitial begin
$dumpfile("cntr_3bit.vcd");$dumpvars;
endinitial begin: stopat#100; $finish;endalways @(posedge clk) begin$display("%d\t %b \t %b \t %b",$time,clk, rst, cnt);endendmodule
25 ENGN3213: Digital Systems and Microprocessors L#5-6
Example: Counter[ggb112@localhost counter]$ more cmp.shiverilog cntr_3bit.v TB_cntr_3bit.v./a.outgtkwave cntr_3bit.vcd______________________________________[ggb112@BushLAN0 lecture5_and_6_VERILOG]$ sh cmp.shVCD info: dumpfile cntr_3bit.vcd opened for output.
time clk rst count3 1 0 00017 1 0 0010
11 1 0 001115 1 0 010019 1 0 010123 1 0 011027 1 0 011131 1 0 100035 1 0 100139 1 0 101043 1 0 101147 1 0 110051 1 0 110155 1 0 111059 1 0 1111
26 ENGN3213: Digital Systems and Microprocessors L#5-6
Example: Counter
27 ENGN3213: Digital Systems and Microprocessors L#5-6
Design technique 1: Combinational Datapath
➤ Outputs determined instantaneously from the inputs➤ Fastest response time large area consumption➤ e.g LUTs
28 ENGN3213: Digital Systems and Microprocessors L#5-6
Design technique 2: Bit Serial Datapath
➤ Output bitstream produced synchronously with serial input bit streams.➤ Low silicon area consumption➤ E.g. Anlogue time serial systems - filters (convolution)
Clk
ProcessorInput data stream Output data stream
29 ENGN3213: Digital Systems and Microprocessors L#5-6
Block Schematic - 4-bit adder
X[3]
Y[3]
Z[3]
Cin
Cout
X[2]
Y[2] Cin
Cout
Z[2]
X[1]
Y[1] Cin
Cout
Z[1]
X[0]
Y[0] Cin
Cout
Z[0]
Z[4]
Co
C1
C2
30 ENGN3213: Digital Systems and Microprocessors L#5-6
Top module - 4-bit adder
module add4(X, Y, Z);
input [3:0] X;input [3:0] Y;output [4:0] Z;
wire Co, C1, C2;
add1 a1(X[0], Y[0], 1’b0, Z[0], Co);add1 a2(X[1], Y[1], Co, Z[1], C1);add1 a3(X[2], Y[2], C1, Z[2], C2);add1 a4(X[3], Y[3], C2, Z[3], Z[4]);
endmodule
31 ENGN3213: Digital Systems and Microprocessors L#5-6
1 bit full adder
module add1(X, Y, Cin, Z, Cout);
input X;input Y;input Cin;
output Z;output Cout;
reg Z;reg Cout;
always @(X, Y, Cin) beginZ = ???;
Cout = ???:endendmodule
32 ENGN3213: Digital Systems and Microprocessors L#5-6
Four bit adder - output
33 ENGN3213: Digital Systems and Microprocessors L#5-6
Block Schematic - bit serial adder
Carry logicCout
Cin
X
Y
Z
Delay
1-bit
Clk
Rst
D Flip Flop
34 ENGN3213: Digital Systems and Microprocessors L#5-6
bit serial addermodule bs_adder( clk, rst, X, Y, Z);input clk;input rst;input X;input Y;
wire rst;reg Cin;wire Cout;output Z;reg Z;
assign Cout = ???;always @(posedge clk or rst) begin
if (rst) beginZ <= 1’b0;Cin <= 1’b0;
end else beginZ <= ???;Cin <= Cout;
endend
endmodule
35 ENGN3213: Digital Systems and Microprocessors L#5-6
bit serial adder - output
36 ENGN3213: Digital Systems and Microprocessors L#5-6
Pitfalls of Treating Verilog like a Programming Language
➤ If you program sequentially, the synthesiser may add a lot of hardware totry to do what you say
➤ If you program in parallel (multiple ’always’ blocks), you can getnon-deterministic execution - Which ’always’ happens first?
if(x == 1) out = 0;if(y == 1) out = 1;// else out retains previous state? R-S latc h!
➤ You don’t realize how much hardware you’re specifying e.g. x = x + 1 can be a LOT ofhardware
➤ Slight changes may suddenly make your code ’blow up’. A chip that previously fitsuddenly is too large or slow
37 ENGN3213: Digital Systems and Microprocessors L#5-6
Structural vs Behavioral HDL Constructs
➤ Structural constructs specify actual hardware structures➤ Low-level, direct correspondence to hardware➤ Primitive gates (e.g., and, or, not)➤ Hierarchical structures via modules
➤ Behavioural constructs specify an operation on bits➤ High-level, more abstract➤ Specified via equations, e.g.
out = (a&b)|c
➤ Not all behavioural constructs are synthesisable➤ We’ve already talked about the pitfalls of trying to ’program’➤ But even some combinational logic won’t synthesise well
➤ out = a%b //modulo operation-what does this synthesise to?
➤ The following are discouraged for synthesis:+... − ... ∗ ......%... < ... <= ... < ... <= ... << ... >>
38 ENGN3213: Digital Systems and Microprocessors L#5-6