SMARC Design Guide 2.0 Page 2 of 119 Mar 23, 2017 ©SGeT e.V.
© Copyright 2017, SGeT Standardization Group for Embedded Technology e.V. Note that some content of this SGeT document may be legally protected by patent rights not held by SGeT. SGeT is not obligated to identify the parts of this specification that require licensing or other legitimization. The contents of this SGeT document are advisory only. Users of SGeT documents are responsible for protecting themselves against liability for infringement of patents. All content and information within this document are subject to change without prior notice. SGeT provides no warranty with regard to this SGeT document or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. SGeT assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and this SGeT document. In no event shall SGeT be liable for any incidental, consequential, special, or exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this SGeT document or any other information contained herein or the use thereof.
SMARC Design Guide 2.0 Page 3 of 119 Mar 23, 2017 ©SGeT e.V.
REVISION HISTORY
Revision Comments Originator Date
1.0 Initial Release S. Milnor / Kontron July 1, 2013
1.1 Created sharper images for Fig 19, 60, 69 Fixed small typos and grammar mistakes
S. Milnor / Kontron July 5, 2013
2.0 Update to SMARC 2.0 Hardware Specification
B. Mayer / Technagon March 23, 2017
SMARC Design Guide 2.0 Page 4 of 119 Mar 23, 2017 ©SGeT e.V.
CONTENTS
1 Introduction .......................................................................................................................................... 10 1.1 General Introduction .................................................................................................................... 10 1.2 Purpose of This Document .......................................................................................................... 10 1.3 Design Help ................................................................................................................................. 10 1.4 Abbreviations and Acronyms Used ............................................................................................. 11 1.5 Document References ................................................................................................................ 13
1.5.1 SGET Documents ............................................................................................................... 13 1.5.2 Industry Standards Documents ........................................................................................... 13
1.6 Schematic Example Correctness ................................................................................................ 15 1.7 Software Support ........................................................................................................................ 15 1.8 Schematic Example Conventions ............................................................................................... 16
2 Infrastructure: Connector, Power Delivery, System Management ...................................................... 18 2.1 Module Connector ....................................................................................................................... 18 2.2 Module Power ............................................................................................................................. 21
2.2.1 Input Voltage Range ........................................................................................................... 21 2.2.2 Input Voltage Rise Time ...................................................................................................... 21 2.2.3 Module Maximum Input Power ............................................................................................ 21 2.2.4 Power Path .......................................................................................................................... 21
2.3 Module I/O Voltage ..................................................................................................................... 23 2.4 VIN_PWR_BAD# ........................................................................................................................ 24 2.5 CARRIER_PWR_ON .................................................................................................................. 24 2.6 Reset In to Module ...................................................................................................................... 24 2.7 Power Button ............................................................................................................................... 25 2.8 Force Recovery ........................................................................................................................... 26 2.9 Power Up Sequence ................................................................................................................... 27
2.9.1 CARRIER_STBY# ............................................................................................................... 28 2.10 Boot Selection ............................................................................................................................. 29
2.10.1 Boot Definitions ................................................................................................................... 29 2.10.2 SMARC BOOT_SEL Pins ................................................................................................... 30
2.11 RTC Backup Power ..................................................................................................................... 31 2.12 Reserved / Test Interfaces .......................................................................................................... 32
3 Display Interfaces ................................................................................................................................ 33 3.1 Module LVDS .............................................................................................................................. 33
3.1.1 NEC 1280 x 768 Single Channel LVDS Example ............................................................... 33 3.1.2 LVDS Dual Channel example ............................................................................................. 35 3.1.3 Display Parameters and EDID ............................................................................................ 37
3.2 HDMI ........................................................................................................................................... 38 3.3 DisplayPort (DP++) ..................................................................................................................... 39
3.3.1 HDMI over DP++ ................................................................................................................. 39 3.4 Embedded DisplayPort (eDP) ..................................................................................................... 40 3.5 MIPI DSI ...................................................................................................................................... 41
4 Low / Medium Speed Serial I/O Interfaces ......................................................................................... 42 4.1 Asynchronous Serial Ports .......................................................................................................... 42
4.1.1 RS232 Ports ........................................................................................................................ 42 4.1.2 RS485 Half-Duplex.............................................................................................................. 43
4.2 I2C Interfaces .............................................................................................................................. 45 4.2.1 General ................................................................................................................................ 45 4.2.2 I2C Level Translation, Isolation and Buffering .................................................................... 45 4.2.3 I2C_PM Bus EEPROMs ...................................................................................................... 47 4.2.4 General I2C Bus EEPROMs ............................................................................................... 49 4.2.5 I2C Based I/O Expanders ................................................................................................... 50 4.2.6 Other I2C Devices ............................................................................................................... 51
4.3 Touch Screen Controller Interfaces ............................................................................................ 53 4.3.1 General ................................................................................................................................ 53 4.3.2 Interface Types / Driver Considerations .............................................................................. 53
SMARC Design Guide 2.0 Page 5 of 119 Mar 23, 2017 ©SGeT e.V.
4.3.3 Touch Controller Modules / ICs / Screens .......................................................................... 53 4.3.4 I2C Interface to Touch Controller ........................................................................................ 55
4.4 I2S Interfaces .............................................................................................................................. 56 4.4.1 General Information ............................................................................................................ 56 4.4.2 Cirrus Logic I2S Audio Example ......................................................................................... 56 4.4.3 Texas Instruments TLV320AIC3105 I2S Audio Example ................................................... 57 4.4.4 lntel High Definition Audio over I2S2................................................................................... 58 4.4.6 Audio Switch ........................................................................................................................ 59
4.5 SPI Interfaces .............................................................................................................................. 59 4.5.1 General ................................................................................................................................ 59 4.5.2 SMARC Implementation ...................................................................................................... 60 4.5.3 SPI Device Examples – 1.8V I/O ........................................................................................ 61
4.6 CAN Bus ...................................................................................................................................... 62 4.6.1 General ................................................................................................................................ 62 4.6.2 SMARC Implementation ...................................................................................................... 63 4.6.3 Isolation ............................................................................................................................... 63
5 High Speed Serial I/O Interfaces......................................................................................................... 64 5.1 USB ............................................................................................................................................. 64
5.1.1 General ................................................................................................................................ 64 5.1.2 USB0 Client / Host Direct From Module ............................................................................. 64 5.1.3 USB1 and USB2 Host Ports direct from Module ................................................................. 66 5.1.4 USB 3.0 ............................................................................................................................... 67 5.1.5 USB 3.0 OTG ...................................................................................................................... 67 5.1.6 USB Hub On Carrier ........................................................................................................... 69
5.2 GBE ............................................................................................................................................. 72 5.2.1 GBE Carrier Connector Implementation Example .............................................................. 72 5.2.2 GBE Mag-Jack Connector Recommendations ................................................................... 74 5.2.3 GBE LEDs ........................................................................................................................... 75 5.2.4 GBE software-defined Pins ................................................................................................. 77
5.3 PCIe ............................................................................................................................................ 77 5.3.1 General ................................................................................................................................ 77 5.3.2 PCIe x1 Device Down on Carrier ........................................................................................ 78 5.3.3 Mini-PCIe ............................................................................................................................. 79 5.3.4 PCIe Reference Clock buffer .............................................................................................. 80
5.4 SATA ........................................................................................................................................... 81 5.4.1 General ................................................................................................................................ 81 5.4.2 mSATA / MO-300 ................................................................................................................ 82
5.5 M.2 .............................................................................................................................................. 82 5.5.1 B keying ............................................................................................................................... 83 5.5.2 M keying .............................................................................................................................. 84 5.5.3 E keying ............................................................................................................................... 84
6 Memory Card Interfaces ...................................................................................................................... 86 6.1 SD Card ....................................................................................................................................... 86
7 Camera Interfaces ............................................................................................................................... 87 7.1 General ........................................................................................................................................ 87 7.2 Camera Data Interface Formats.................................................................................................. 87 7.3 Camera Sensors and Camera Module Vendors ......................................................................... 87 7.4 Serial Camera Interface Example ............................................................................................... 87 7.5 Other Camera Options ................................................................................................................ 88
8 GPIO ................................................................................................................................................... 89 8.1 SMARC Module Native GPIO ..................................................................................................... 89 8.2 GPIO Expansion ......................................................................................................................... 89
9 Carrier Power Circuits ......................................................................................................................... 90 9.1 Power Budgeting ......................................................................................................................... 90 9.2 Input Power Sources ................................................................................................................... 91 9.3 Power Budgeting, Continued – Fixed 5V Power Source ............................................................ 92 9.4 Fixed 5V DC Power Input Circuit Example ................................................................................. 93 9.5 Power Hot Swap Controller ......................................................................................................... 96
SMARC Design Guide 2.0 Page 6 of 119 Mar 23, 2017 ©SGeT e.V.
9.6 High Voltage LED Supply ............................................................................................................ 97 9.7 3.0V to 5.25V Power Input Example ........................................................................................... 98 9.8 12V Input ..................................................................................................................................... 99 9.9 Wide Range Power Input .......................................................................................................... 100 9.10 Power Monitoring ...................................................................................................................... 100 9.11 Power Over Ethernet ................................................................................................................. 102 9.12 Li-ION Battery Charger ............................................................................................................. 104
9.12.1 General .............................................................................................................................. 104 9.12.2 Battery Charger Circuit Example ....................................................................................... 105
10 Thermal Management ................................................................................................................... 109 10.1 General ...................................................................................................................................... 109 10.2 Heat Spreaders ......................................................................................................................... 109 10.3 Heat Sinks ................................................................................................................................. 111 10.4 Thermal Resistance Calculations.............................................................................................. 112
11 Carrier PCB Design Rule Summary .............................................................................................. 113 11.1 General – PCB Construction Terms ......................................................................................... 113 11.2 Differential Pair Cautions .......................................................................................................... 114 11.3 General Routing Rules and Cautions ....................................................................................... 115 11.4 Trace Parameters for High-Speed Differential Interfaces ......................................................... 116 11.5 Trace Parameters for Single Ended Interfaces ......................................................................... 117 11.6 PCB Construction Suggestions ................................................................................................. 118
SMARC Design Guide 2.0 Page 7 of 119 Mar 23, 2017 ©SGeT e.V.
FIGURES
Figure 1 Schematic Symbol Conventions .................................................................................................. 16 Figure 2 Module Connector Pins P1-74 and S1-75 ................................................................................... 19 Figure 3 Module Connector Pins P75-156 and S76-158 ........................................................................... 20 Figure 4 Basic Module and Carrier Power Path ........................................................................................ 22 Figure 5 Reset Switch ................................................................................................................................ 24 Figure 6 Power Button Switch .................................................................................................................... 25 Figure 7 Force Recovery Switch ................................................................................................................ 26 Figure 8 SMARC Carrier Power up Sequence - No Power Button Case .................................................. 27 Figure 9 SMARC Carrier Power up Sequence - With Power Button Case ................................................ 28 Figure 10 Boot Selection Jumpers ............................................................................................................. 30 Figure 11 RTC Backup: Coin Battery / Super Cap .................................................................................... 31 Figure 12 Module LVDS: NEC Single Channel Display ............................................................................. 33 Figure 13 LVDS Dual Channel ................................................................................................................... 36 Figure 14 LVDS Dual Channel Power Supply ........................................................................................... 36 Figure 15 Carrier EDID EEPROM .............................................................................................................. 37 Figure 16 HDMI Implementation ................................................................................................................ 38 Figure 17 DisplayPort ++ ........................................................................................................................... 39 Figure 18 HDMI over DP++........................................................................................................................ 40 Figure 19 Embedded DisplayPort (eDP) .................................................................................................... 41 Figure 20 MIPI DSI ..................................................................................................................................... 41 Figure 21 Asynchronous Serial Port Transceiver – RS232 – TRS3253E ................................................. 42 Figure 22 Asynchronous Serial Port Transceiver – RS232 – MAX13235E ............................................... 43 Figure 23 Asynchronous Serial Port Transceiver - RS485 – Half Duplex ................................................. 44 Figure 24 I2C Power Domain Isolation – using FETs ................................................................................ 45 Figure 25 I2C Power Domain Isolation and Buffer – Fairchild FXMA2102 ................................................ 46 Figure 26 I2C_PM EEPROM: Carrier Power Domain ............................................................................... 47 Figure 27 I2C_PM EEPROM: Module Power Domain ............................................................................... 48 Figure 28 I2C_GP EEPROM...................................................................................................................... 49 Figure 29 I2C Device: I/O Expander .......................................................................................................... 50 Figure 30 I2C Device: Accelerometer ........................................................................................................ 51 Figure 31 I2C Device: Accelerometer and Magnetometer ......................................................................... 51 Figure 32 I2C Device: Gyroscope .............................................................................................................. 52 Figure 33 Touch Screen Connector – I2C Interface .................................................................................. 55 Figure 34 I2S Audio Codec Cirrus Logic WM8904 .................................................................................... 56 Figure 35 I2S Audio CODEC: Texas Instruments ..................................................................................... 57 Figure 36 Audio Amplifier: Texas Instruments ........................................................................................... 57 Figure 37 HD Audio .................................................................................................................................... 58 Figure 38 Audio switch ............................................................................................................................... 59 Figure 39 SPI Flash Socket ....................................................................................................................... 60 Figure 40 CAN Bus Implementation .......................................................................................................... 63 Figure 41 USB0 Client / Host Direct From Module .................................................................................... 65 Figure 42 USB1 and USB4 Host Ports Direct From Module ..................................................................... 66 Figure 43 USB 3.0 host dual ...................................................................................................................... 67 Figure 44 USB 3.0 OTG ............................................................................................................................. 68 Figure 45 USB Hub (1 of 2)........................................................................................................................ 70 Figure 46 USB Hub (2 of 2)........................................................................................................................ 71 Figure 47 GBE without POE ...................................................................................................................... 72 Figure 48 GBE separate magnetic for current and voltage mode line driver ............................................. 73 Figure 49 GBE LED Current Sink .............................................................................................................. 75 Figure 50 GBE LED Current Sink / Source ................................................................................................ 76 Figure 51 Interfacing a PCIe x1 Carrier Board Device .............................................................................. 78 Figure 52 Mini-PCIe Slot ............................................................................................................................ 79 Figure 53 PCIe Clock buffer ....................................................................................................................... 80 Figure 54 mSATA / MO-300....................................................................................................................... 82
SMARC Design Guide 2.0 Page 8 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 55 M.2 Key B .................................................................................................................................. 83 Figure 56 M.2 Key M .................................................................................................................................. 84 Figure 57 M.2 Key E .................................................................................................................................. 85 Figure 58 Micro SD Card Implementation .................................................................................................. 86 Figure 59 Serial Camera Implementation .................................................................................................. 88 Figure 60 5V Input Connector .................................................................................................................... 93 Figure 61 5V Carrier Power Switch ............................................................................................................ 93 Figure 62 3.3V 2A Buck Converter ............................................................................................................ 94 Figure 63 1.8V Buck Converter .................................................................................................................. 94 Figure 64 1.5V Buck Converter .................................................................................................................. 95 Figure 65 12V Boost Converter for Backlight Power ................................................................................. 95 Figure 66 Hot Swap Controller ................................................................................................................... 96 Figure 67 LP8545 LED Backlight Power .................................................................................................... 97 Figure 68 5V, 2A Buck-Boost Converter .................................................................................................... 98 Figure 69 3.3V 2A Buck-Boost Converter .................................................................................................. 98 Figure 70 12V Step Down Switcher ........................................................................................................... 99 Figure 71 Wide Range Power Input Switcher .......................................................................................... 100 Figure 72 Power Monitor - Incoming Power............................................................................................. 101 Figure 73 GbE with PoE ........................................................................................................................... 103 Figure 74 Li-ION Battery Charger - Block Diagram ................................................................................. 106 Figure 75 Li-ION Battery Charger - Schematic ........................................................................................ 107 Figure 76 Battery Fuel Gauge .................................................................................................................. 108 Figure 77 Charger Present Detection ...................................................................................................... 108 Figure 78 Heat Spreader Example – 82mm x 50mm Module .................................................................. 110 Figure 79 Heat Sink Add-On to Heat Spreader ....................................................................................... 111 Figure 80 Stand-Alone Heat Sink ............................................................................................................ 111 Figure 81 PCB Cross Section – Striplines and Asymmetric Microstrips .................................................. 114
TABLES Table 1 Schematic Power Net Naming ...................................................................................................... 17 Table 2 Boot Select Pins ............................................................................................................................ 30 Table 3 I2C Device Examples - 1.8V I/O ................................................................................................... 52 Table 4 Popular Touch Technologies ........................................................................................................ 53 Table 5 Touch Controller Module / IC / Screen Vendors ........................................................................... 53 Table 6 SPI Device Examples - 1.8V I/O ................................................................................................... 61 Table 7 Recommended Gigabit Ethernet Connectors with Magnetics ...................................................... 74 Table 8 PCIe Data Transfer Rates ............................................................................................................. 77 Table 9 SMARC PCIe Signal Summary ..................................................................................................... 77 Table 10 SATA SSD Form Factors ............................................................................................................ 81 Table 11 SATA SSD Vendors .................................................................................................................... 81 Table 12 Camera Sensors ......................................................................................................................... 87 Table 13 Camera Module Vendors ............................................................................................................ 87 Table 14 Hypothetical Power Budget Example – Part 1 ............................................................................ 90 Table 15 Input Power Source Possibilities................................................................................................. 91 Table 16 Hypothetical Power Budget Example – Part 2 ............................................................................ 92 Table 17 Lithium- Ion Battery Cell Voltages ............................................................................................. 104 Table 18 Heat Spreader Hole Types ....................................................................................................... 110 Table 19 Hypothetical Thermal Parameters ............................................................................................ 112 Table 20 PCB Terms and Symbols .......................................................................................................... 113 Table 21 High-Speed Differential Trace Parameters ............................................................................... 116 Table 22 Single Ended Trace Parameters ............................................................................................... 117 Table 23 PCB Construction Example - 4 Layers ..................................................................................... 118 Table 24 PCB Construction Example - 6 Layers ..................................................................................... 118 Table 25 PCB Construction Example – 8 Layers .................................................................................... 119
SMARC Design Guide 2.0 Page 9 of 119 Mar 23, 2017 ©SGeT e.V.
SMARC Design Guide 2.0 Page 10 of 119 Mar 23, 2017 ©SGeT e.V.
1 INTRODUCTION
1.1 General Introduction
SMARC (“Smart Mobility Architecture”) is a computer Module standard maintained by the SGeT (“Standardization Group for Embedded Technologies”). SMARC Modules are small form factor (82mm x 50mm and 82mm x 80mm), low power (typically <6W) computer Modules that are used on a Carrier board that utilizes a 314 pin 0.5mm pitch right-angle memory socket style connector to host the Module. SMARC Modules may utilize ARM, low power RISC or low power x86 CPUs / SOCs. The SMARC Modules are specified in the SGeT Smart Mobility Architecture Hardware Specification 2.0. The specification document and an errata document are available free of charge from the SGET web site (www.sget.org), subject to their terms of use. Similarly, this SMARC Design Guide is available free of charge from the SGET web site, subject to the SGET terms of use.
1.2 Purpose of This Document
The primary purpose of this document is to serve as a Design Guide for developers of SMARC Carrier Boards and for SMARC Module customers who wish to have a SMARC based system developed. A secondary purpose of this document is to serve as a reference to SMARC Module developers, to help them understand the application of the Modules they are developing. Finally, this document should be valuable to FAEs and Product managers to help them understand the SMARC infrastructure.
1.3 Design Help
There are a number of ways to have a SMARC Carrier board developed:
Design internally, but have your SMARC Module vendor review your design. Make sure to also have the appropriate semiconductor companies review the portions of the design that utilize their components.
Use a 3rd party firm that specializes in SMARC Carrier development. Such resources may be listed on the SGET web page (www.sget.org).
Contact your SMARC Module vendor. The Module vendor will have an FAE available for advice. Many vendors will also undertake custom Carrier design projects, for significant opportunities.
SMARC Design Guide 2.0 Page 11 of 119 Mar 23, 2017 ©SGeT e.V.
1.4 Abbreviations and Acronyms Used
ADC Analog to Digital Converter
ARM Advanced RISC Machines www.arm.com
BCT Boot Configuration Table
BSP (software) Board Support Package
CAD Computer Aided Design
CAN Controller Area Network
CPLD Complex Programmable Logic Device
CODEC Coder – Decoder
CSI Camera Serial Interface www.mipi.org
DAC Digital to Analog Converter
DB-9 Connector, D shaped, B shell size, 9 pins
DDC Display Data Channel
DDI Digital Display Interface
DE Differential Ended (signal pair)
DNI Do Not Install (component is not loaded)
DP DisplayPort
DP++ Dual-mode DisplayPort
DSP Digital Signal Processor
DSI Display Serial Interface
EDID Extended Display Identification Data www.vesa.org
EEPROM Electrically Erasable Programmable Read Only Memory
eMMC Embedded Multi Media Card www.jedec.org
ESD Electro Static Discharge
FET Field Effect Transistor
FIFO First In First Out (buffer memory)
FS Full Speed (USB 2.0 12 Mbps)
GBE Gigabit Ethernet www.ieee.org
Gbps Gigabit per second
GPIO General Purpose Input / Output
GPS Global Positioning System
HDA High Definition Audio – Intel defined format www.intel.com
HDMI High Definition Multimedia Interface www.hdmi.org
HID Human Interface Device: USB device class
HS High Speed (USB 2.0 480 Mbps)
IC Integrated Circuit
I2C Inter-Integrated Circuit www.nxp.com
I2S Inter-Integrated Circuit – Sound www.nxp.com
IEEE Institute of Electrical and Electronics Engineers www.ieee.org
IO Input Output
ISO International Organization for Standardization (French) www.iso.org
JEDEC Joint Electron Device Engineering Council www.jedec.org
JPEG Joint Photographic Experts Group www.jpeg.org
LED Light Emitting Diode
Li-Ion Lithium Ion (rechargeable battery technology)
LVDS Low Voltage Differential Signaling
M2.5 Metric 2.5mm
M3 Metric 3.0mm
MAC Media Access Controller (e.g. logic circuits in GBE)
Mbps Megabit per second
MIPI Mobile Industry Processor Interface www.mipi.org
MLC Multi Level Cell (flash memory reference)
MOD Module (the SMARC Module) (schematic notation)
SMARC Design Guide 2.0 Page 12 of 119 Mar 23, 2017 ©SGeT e.V.
MO-297 Module Outline 297 (“Slim SATA” format) www.jedec.org
MO-300 Module Outline 300 (mini-PCIe Express card format) www.jedec.org
MPEG Motion Picture Experts Group www.mpeg.org
MXM Mobile pci eXpress Module www.mxm-sig.org
MXM3 MXM Revision 3
NAND A high density flash memory technology
ns Nano second (10 E -9)
NC Not Connected
NXP A semiconductor company www.nxp.com
OS Operating System
OTG On the Go (USB term – device can be host or client)
PCB Printed Circuit Board
PHY Physical (transceiver) – drives cable
PICMG PCI Industrial Computer Manufacturing Group www.picmg.org
PCI Peripheral Component Interface www.pcisig.org
PCIe PCI Express www.pcisig.org
PCI-SIG PCI Special Interest Group www.pcisig.org
PCM Pulse-Code Modulation
PLL Phase Locked Loop
POE Power Over Ethernet
ps Pico second (10 E -12)
PWM Pulse Width Modulation
RGB Video data in Red Green Blue pixel format
RISC Reduced Instruction Set Computing
ROM Read Only Memory
RS232 Recommend Standard 232 (asynchronous serial ports)
RS485 Asynchronous serial data, differential, multidrop
RTC Real Time Clock (battery backed clock and memory)
SAR Successive Approximation Register
SATA Serial ATA (serial mass storage interface) www.sata-io.org
SD Secure Digital (memory card)
SE Single Ended (signal, as opposed to differential)
SGeT Standardization Group for Embedded Technologies www.sget.org
SLC Single Level Cell (flash memory reference)
SMARC Smart Mobility Architecture www.sget.org
SMSC A semiconductor company, now MICROCHIP www.smsc.com
SOC System On Chip
S/PDIF Sony/Philips Digital Interconnect Format
SPI Serial Peripheral Interface
SSD Solid State Disk
TI Texas Instruments – semiconductor company www.ti.com
TIM Thermal Interface Material
UART Universal Asynchronous Receiver Transmitter
UL Underwriters Laboratories www.ul.com
USB Universal Serial Bus www.usb.org
VESA Video Electronics Standards Association www.vesa.org
WEC7 Windows Embedded Compact 7 (an OS)
YUV Video data format, more common in television
X5R Ceramic capacitor dielectric – good quality
X7R Ceramic capacitor dielectric – best quality
X86 Intel architecture (80x86) CPUs
SMARC Design Guide 2.0 Page 13 of 119 Mar 23, 2017 ©SGeT e.V.
1.5 Document References
1.5.1 SGET Documents
Smart Mobility Architecture Hardware Specification, V 2.0, June 2, 2016 © SGET (Standardization Group For Embedded Technologies) www.sget.org
1.5.2 Industry Standards Documents
BT.656 (“Recommendation ITU-R BT.656-5 Interface for digital component video signals in 525-line and 625-line television systems operating at the 4:2:2 level of Recommendation ITU-R BT.601”), International Telecommunications Union, December 2007 (www.itu.int)
CAN (“Controller Area Network”) Bus Standard – ISO 11898
CSI-2 (Camera Serial Interface version 2) The CSI-2 standard is owned and maintained by the
MIPI Alliance (“Mobile Industry Processor Interface Alliance”) (www.mipi.org).
CSI-3 (Camera Serial Interface version 3) The CSI-3 standard is owned and maintained by the
MIPI Alliance (“Mobile Industry Processor Alliance”) (www.mipi.org)
COM Express – the formal title for the COM Express specification is “PICMG® COM.0 COM
Express Module Base Specification”, Revision 2.1, May 14, 2012. This standard is owned and
maintained by the PICMG (“PCI Industrial Computer Manufacturer’s Group”) (www.picmg.org)
DisplayPort and Embedded DisplayPort These standards are owned and maintained by VESA
(“Video Electronics Standards Association”) (www.vesa.org)
D-PHY CSI-2 physical layer standard – owned and maintained by the MIPI Alliance
(www.mipi.org)
DSI (Display Serial Interface) The DSI standard is owned and maintained by the MIPI Alliance (“Mobile Industry Processor Alliance”) (www.mipi.org)
eMMC (“Embedded Multi-Media Card”) the eMMC electrical standard is defined by JEDEC
JESD84-B45 and the mechanical standard by JESD84-C44 (www.jedec.org).
eSPI (“Enhanced Serial Peripheral Interface”) The eSPI Interface Base Specification is defined
by Intel (https://downloadcenter.intel.com/de/download/22112)
Fieldbus - this term refers to a number of network protocols used for real – time industrial control. Refer to the following web sites: www.profibus.com/downloads and www.canopen.org
GBE MDI (“Gigabit Ethernet Medium Dependent Interface”) defined by IEEE 802.3. The
1000Base-T operation over copper twisted pair cabling defined by IEEE 802.3ab
(www.ieee.org).
HDA (HD Audio), High Definition Audio Specification, Intel, Revision 1.0a, June 17, 2010 (http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/high-definition-audio-specification.pdf)
HDMI Specification, Version 1.3a, November 10, 2006 © Hitachi and other companies
(www.hdmi.org).
The I2C Specification, Version 2.1, January 2000, Philips Semiconductor (now NXP)
(www.nxp.com).
I2S Bus Specification, Feb. 1986 and Revised June 5, 1996, Philips Semiconductor (now NXP)
(www.nxp.com).
IEEE1588 - 2008. IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems (http://standards.ieee.org/findstds/standard/1588-2008.html)
SMARC Design Guide 2.0 Page 14 of 119 Mar 23, 2017 ©SGeT e.V.
JTAG (“Joint Test Action Group”) This is defined by IEEE 1149.1-2001 - IEEE Standard Test Access Port and Boundary Scan Architecture (www.ieee.org )
JEDEC MO-300 (mSATA) defines the physical form factor of the mSATA format
(www.jedec.org). The electrical connections are defined in the Serial ATA document.
MXM3 Graphics Module Mobile PCI Express Module Electromechanical Specification,
Version 3.0, Revision 1.1, © 2009 NVidia Corporation (www.mxm-sig.org ).
PICMG® EEEP Embedded EEPROM Specification, Rev. 1.0, August 2010 (www.picmg.org).
PCI Express Specifications (www.pci-sig.org).
PCI Express Mini Card Electromechanical Specification Revision 2.0, April 21, 2012, © PCI-
SIG (www.pci-sig.org).
RS-232 (EIA “Recommended Standard 232”) this standard for asynchronous serial port data
exchange dates from 1962. The original standard is hard to find. Many good descriptions of the
standard can be found on-line, e.g. at Wikipedia, and in text books.
Serial ATA Revision 3.1, July 18, 2011, Gold Revision, © Serial ATA International Organization
(www.sata-io.org).
SD Specifications Part 1 Physical Layer Simplified Specification, Version 3.01, May 18,
2010, © 2010 SD Group and SD Card Association (“Secure Digital”) (www.sdcard.org).
SM Bus – “System Management Bus” Specification Version 3.0, 2© 2014 System Management Interface Forum, Inc. (http://www.smbus.org )
SPDIF (aka S/PDIF) (“Sony Philips Digital Interconnect Format) - IEC 60958-3.
SPI Bus – “Serial Peripheral Interface” – de-facto serial interface standard defined by Motorola. A
good description may be found on Wikipedia
(http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus).
UL 1642 Lithium Batteries – safety standard governing the use of lithium batteries
(www.ul.com)
USB Specifications (www.usb.org).
VESA Enhanced Extended Display Identification Data Standard, Rev. 1, Feb 9, 2000, VESA
(www.vesa.org) See also the “EDID” page on Wikipedia.
SMARC Design Guide 2.0 Page 15 of 119 Mar 23, 2017 ©SGeT e.V.
1.6 Schematic Example Correctness
The schematic examples shown in this Design Guide are believed to be correct but correctness cannot be guaranteed. Most of the examples have been pulled from designs that have been built, tested, and are known to work. Most of them have been re-formatted to fit better in this design guide.
1.7 Software Support
Many hardware examples and suggestions are given in the following pages. SMARC Carrier hardware design is generally straightforward. However, before committing to a particular hardware selection, it is wise to check out the software driver support. A particular device may be supported in, say, for example, Linux but not in Windows. Your overall project may go smoother if you pick out hardware that already has software support in your target OS. There are various possible sources for software drivers for a particular IC: the IC vendor, the OS vendor, the OS community, your Module vendor, your Carrier design partner, other independent sources and of course writing your own. Most SMARC Module vendors offer a BSP (Board Support Package) for their Module. Your target Carrier device may be supported in the BSP – check this angle out as well.
SMARC Design Guide 2.0 Page 16 of 119 Mar 23, 2017 ©SGeT e.V.
1.8 Schematic Example Conventions
Some of the conventions used in the schematic examples are described below. Note off-page connections that tie directly to the SMARC Module have the notation “MOD” in the off-page connect symbol.
Figure 1 Schematic Symbol Conventions
V _ 3 V 0 _R T CV _M O D _ IN _ L E D
M O D
M O D
M O D
V _ 1 2 V0 V _ 3 V3V _ 5 V0 V _ 1 V8 V _ 1 V5
V _M O D _ IN V _C A R R IE R _ IN
O ff-S h e e t In te r-c o n n e c t: R e g u la r
O ff-S h e e t In te r-c o n n e c t: T o /F ro m S M A R C M o d u le
O n -S h e e t In te r-c o n n e c t
In p u t
O u tp u t
B id ire c t io n a l
B id ire c t io n a l
O u tp u t
In p u t
G lo b a l P o w e r S y m b o ls
D N I
A b b re v ia t io n s
D o N o t In s ta ll
SMARC Design Guide 2.0 Page 17 of 119 Mar 23, 2017 ©SGeT e.V.
Table 1 Schematic Power Net Naming
V_IN_RAW
Power in to the overall system, before any filtering, fusing, polarity or rise time protection
V_IN
Power in to the overall system, after (optional) filtering, fusing, polarity or rise time protection
V_MOD_IN
Power into the SMARC Module. It must be within the 3.0V to 5.25V range defined by the SMARC specification
V_CARRIER_IN
Power in to the Carrier Board. It may be the same as V_MOD_IN, depending on the design at hand. On SMARC Evaluation Carrier boards, V_CARRIER_IN is sometimes kept separate from V_MOD_IN to allow easier measurements and tracking of where the power goes.
V_5V0
5V supply on the Carrier Board
V_3V3
3.3V supply on the Carrier Board
V_1V8
1.8V supply on the Carrier Board
V_1V5
1.5V supply on the Carrier Board
V_3V0_RTC
Supply voltage from the Carrier Board to the SMARC VDD_RTC pin (pin S147) This is a low voltage, low current supply separate from V_MOD_IN, used to supply the Module RTC (Real Time Clock) in the absence of V_MOD_IN.
V_MOD_IN_LED
Same as V_MOD_IN except isolated by a series jumper – used for power status LEDs – jumper can be removed to prevent status LEDs from consuming power
SMARC Design Guide 2.0 Page 18 of 119 Mar 23, 2017 ©SGeT e.V.
2 INFRASTRUCTURE: CONNECTOR, POWER DELIVERY, SYSTEM MANAGEMENT
2.1 Module Connector
The SMARC Module connector is well described in the Smart Mobility ARChitecture Hardware Specification 2.0 and the complete description is not repeated here. Briefly, the SMARC Module connector is a low profile, right angle 314 pin memory – socket style connector. The same connector is commonly used for MXM3 graphics cards. However, it is important to understand that the SMARC usage and pin-out of this connector is totally different from the usage as graphics card. The SMARC Module connector is available from multiple sources, including at least one vendor that has qualified their offering for automotive use. Various height profiles are available for the SMARC Module connector. The lowest profile available has a Carrier Board PCB top-side to Module PCB bottom-side separation of 1.5mm, and a connector body height of 4.3mm.
SMARC Design Guide 2.0 Page 19 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 2 Module Connector Pins P1-74 and S1-75
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
X1-1
SMARC-Connector_2parts_SM2.0<Assembly>
SMB_ALERT_1V8P1
GND_01P2
CSI1_CK+P3
CSI1_CK-P4
GBE1_SDPP5
GBE0_SDPP6
CSI1_RX0+P7
CSI1_RX0-P8
GND_02P9
CSI1_RX1+P10
CSI1_RX1-P11
GND_03P12
CSI1_RX2+P13
CSI1_RX2-P14
GND_04P15
CSI1_RX3+P16
CSI1_RX3-P17
GND_05P18
GBE0_MDI3-P19
GBE0_MDI3+P20
GBE0_LINK100P21
GBE0_LINK1000P22
GBE0_MDI2-P23
GBE0_MDI2+P24
GBE0_LINK_ACTP25
GBE0_MDI1-P26
GBE0_MDI1+P27
GBE0_CTREFP28
GBE0_MDI0-P29
GBE0_MDI0+P30
SPI0_CS1P31
GND_06P32
SDIO_WPP33
SDIO_CMDP34
SDIO_CDP35
SDIO_CKP36
SDIO_PWR_ENP37
GND_07P38
SDIO_D0P39
SDIO_D1P40
SDIO_D2P41
SDIO_D3P42
SPI0_CS0P43
SPI0_CKP44
SPI0_DINP45
SPI0_DOP46
GND_08P47
SATA_TX+P48
SATA_TX-P49
GND_09P50
SATA_RX+P51
SATA_RX-P52
GND_10P53
ESPI_CS0P54
ESPI_CS1P55
ESPI_CKP56
ESPI_IO_0P57
ESPI_IO_1P58
GND_11P59
USB0+P60
USB0-P61
USB0_EN_OCP62
USB0_VBUS_DETP63
USB0_OTG_IDP64
USB1+P65
USB1-P66
USB1_EN_OCP67
GND_12P68
USB2+P69
USB2-P70
USB2_EN_OCP71
RSVD_01P72
RSVD_02P73
USB3_EN_OCP74
CSI1_TX+/I2C_CAM1_CKS1
CSI1_TX-/I2C_CAM1_DATS2
GND_25S3
RSVD_05S4
CSI0_TX-/I2C_CAM0_CKS5
CAM_MCKS6
CSI0_TX+/I2C_CAM0_DATS7
CSI0_CK+S8
CSI0_CK-S9
GND_26S10
CSI0_RX0+S11
CSI0_RX0-S12
GND_27S13
CSI0_RX1+S14
CSI0_RX1-S15
GND_28S16
GBE1_MDI0+S17
GBE1_MDI0-S18
GBE1_LINK100S19
GBE1_MDI1+S20
GBE1_MDI1-S21
GBE1_LINK1000S22
GBE1_MDI2+S23
GBE1_MDI2-S24
GND_29S25
GBE1_MDI3+S26
GBE1_MDI3-S27
GBE1_CTREFS28
PCIE_D_TX+S29
PCIE_D_TX-S30
GBE1_LINK_ACTS31
PCIE_D_RX+S32
PCIE_D_RX-S33
GND_30S34
USB4+S35
USB4-S36
USB3_VBUS_DETS37
AUDIO_MCKS38
I2S0_LRCKS39
I2S0_SDOUTS40
I2S0_SDINS41
I2S0_CKS42
ESPI_ALERT0S43
ESPI_ALERT1S44
RSVD_06S45
RSVD_07S46
GND_31S47
I2C_GP_CKS48
I2C_GP_DATS49
HDA_SYNC/I2S2_LRCKS50
HDA_SDO/I2S2_SDOUTS51
HDA_SDI/I2S2_SDINS52
HDA_CK/I2S2_CKS53
SATA_ACTS54
USB5_EN_OCS55
ESPI_IO_2S56
ESPI_IO_3S57
ESPI_RESETS58
USB5+S59
USB5-S60
GND_32S61
USB3_SSTX+S62
USB3_SSTX-S63
GND_33S64
USB3_SSRX+S65
USB3_SSRX-S66
GND_34S67
USB3+S68
USB3-S69
GND_35S70
USB2_SSTX+S71
USB2_SSTX-S72
GND_36S73
USB2_SSRX+S74
USB2_SSRX-S75
SMB_ALERT_1V8#
CSI1_CK_PCSI1_CK_NGBE1_SDPGBE0_SDPCSI1_D0_P
CSI1_D1_PCSI1_D1_N
CSI1_D2_PCSI1_D2_N
CSI1_D3_NCSI1_D3_P
GBE0_MDI3_N
GBE0_MDI0_N
GBE0_MDI3_PGBE0_LINK100#GBE0_LINK1000#GBE0_MDI2_NGBE0_MDI2_PGBE0_LNK#_ACT#GBE0_MDI1_NGBE0_MDI1_PGBE0_CTREF
GBE0_MDI0_PSPI0_CS1#
SDIO_WPSDIO_CMDSDIO_CD#SDIO_CLKSDIO_PWR_EN
SDIO_D0SDIO_D1SDIO_D2SDIO_D3
SDIO_D[0..3]
SPI0_CS0#SPI0_CKSPIO_DINSPIO_DO
SATA_TX_PSATA_TX_N
SATA_RX_PSATA_RX_N
ESPI_CS0#ESPI_CS1#ESPI_CKESPI_IO_0ESPI_IO_1
USB0_D_PUSB0_D_N
USB1_D_PUSB1_D_N
USB2_D_PUSB2_D_N
USB0_EN_OC#USB0_VBUS_DETUSB0_OTG_ID
USB1_EN_OC#
USB2_EN_OC#RESERVED_01RESERVED_02USB3_EN_OC#
CSI1_TX_P/I2C_CAM1_CKCSI1_TX_N/I2C_CAM1_DAT
RESERVED_05CSI0_TX_N/I2C_CAM0_CKCAM_MCKCSI0_TX_P/I2C_CAM0_DAT
CSI0_CK_NCSI0_CK_P
CSI0_RX0_PCSI0_RX0_N
CIS0_RX1_PCIS0_RX1_N
GBE1_MDI0_PGBE1_MDI0_NGBE1_LINK100#GBE1_MDI1_PGBE1_MDI1_NGBE1_LINK1000#GBE1_MDI2_PGBE1_MDI2_N
GBE1_MDI3_PGBE1_MDI3_NGBE1_CTREFPCIE_D_TX_PPCIE_D_TX_N
PCIE_D_RX_PGBE1_LINK_ACT#
PCIE_D_RX_N
USB4_D_PUSB4_D_NUSB3_VBUS_DETAUDIO_MCKI2S0_LRCKI2S0_SDOUTI2S0_SDINI2S0_CKESPI_ALERT0#ESPI_ALERT1#RESERVED_06RESERVED_07
I2C_GP_CKI2C_GP_DATHDA_SYNC/I2S2_LRCKHDA_SDO/I2S2_SDOUTHDA_SDI/I2S2_SDINHDA_CK/I2S2_CKSATA_ACT#USB5_EN_OC#ESPI_IO2ESPI_IO3ESPI_RESET#USB5_D_PUSB5_D_N
USB3_SSTX_PUSB3_SSTX_N
USB3_SSRX_NUSB3_SSRX_P
USB3_D_PUSB3_D_N
USB2_SSTX_PUSB2_SSTX_N
USB2_SSRX_PUSB2_SSRX_N
CSI1_D0_N
SMARC Design Guide 2.0 Page 20 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 3 Module Connector Pins P75-156 and S76-158
V_MOD_IN
V_RTC
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
X1-2
SMARC-Connector_2parts_SM2.0<Assembly>
PCIE_A_RSTP75
USB4_EN_OCP76
RSVD_03P77
RSVD_04P78
GND_13P79
PCIE_C_REFCK+P80
PCIE_C_REFCK-P81
GND_14P82
PCIE_A_REFCK+P83
PCIE_A_REFCK-P84
GND_15P85
PCIE_A_RX+P86
PCIE_A_RX-P87
GND_16P88
PCIE_A_TX+P89
PCIE_A_TX-P90
GND_17P91
HDMI_D2+/DP1_LANE0+P92
HDMI_D2-/DP1_LANE0-P93
GND_18P94
HDMI_D1+/DP1_LANE1+P95
HDMI_D1-/DP1_LANE1-P96
GND_19P97
HDMI_D0+/DP1_LANE2+P98
HDMI_D0-/DP1_LANE2-P99
GND_20P100
HDMI_CK+/DP1_LANE3+P101
HDMI_CK-/DP1_LANE3-P102
GND_21P103
HDMI_HPD/DP1_HPDP104
HDMI_CTRL_CK/DP1_AUX+P105
HDMI_CTRL_DAT/DP1_AUX-P106
DP1_AUX_SELP107
GPIO0/CAM0_PWRP108
GPIO1/CAM1_PWRP109
GPIO2/CAM0_RSTP110
GPIO3/CAM1_RSTP111
GPIO4/HDA_RSTP112
GPIO5/PWM_OUTP113
GPIO6/TACHINP114
GPIO7P115
GPIO8P116
GPIO9P117
GPIO10P118
GPIO11P119
GND_22P120
I2C_PM_CKP121
I2C_PM_DATP122
BOOT_SEL0P123
BOOT_SEL1P124
BOOT_SEL2P125
RESET_OUTP126
RESET_INP127
POWER_BTNP128
SER0_TXP129
SER0_RXP130
SER0_RTSP131
SER0_CTSP132
GND_23P133
SER1_TXP134
SER1_RXP135
SER2_TXP136
SER2_RXP137
SER2_RTSP138
SER2_CTSP139
SER3_TXP140
SER3_RXP141
GND_24P142
CAN0_TXP143
CAN0_RXP144
CAN1_TXP145
CAN1_RXP146
VDD_IN_01P147
VDD_IN_02P148
VDD_IN_03P149
VDD_IN_04P150
VDD_IN_05P151
VDD_IN_06P152
VDD_IN_07P153
VDD_IN_08P154
VDD_IN_09P155
VDD_IN_10P156
PCIE_B_RSTS76
PCIE_C_RSTS77
PCIE_C_RX+S78
PCIE_C_RX-S79
GND_37S80
PCIE_C_TX+S81
PCIE_C_TX-S82
GND_38S83
PCIE_B_REFCK+S84
PCIE_B_REFCK-S85
GND_39S86
PCIE_B_RX+S87
PCIE_B_RX-S88
GND_40S89
PCIE_B_TX+S90
PCIE_B_TX-S91
GND_41S92
DP0_LANE0+S93
DP0_LANE0-S94
DP0_AUX_SELS95
DP0_LANE1+S96
DP0_LANE1-S97
DP0_HPDS98
DP0_LANE2+S99
DP0_LANE2-S100
GND_42S101
DP0_LANE3+S102
DP0_LANE3-S103
USB3_OTG_IDS104
DP0_AUX+S105
DP0_AUX-S106
LCD1_BKLT_ENS107
LVDS1_CK+/eDP1_AUX+/DSI1_CLK+S108
LVDS1_CK-/eDP1_AUX-/DSI1_CLK-S109
GND_43S110
LVDS1_0+/eDP1_TX0+/DSI1_D0+S111
LVDS1_0-/eDP1_TX0-/DSI1_D0-S112
eDP1_HPDS113
LVDS1_1+/eDP1_TX1+/DSI1_D1+S114
LVDS1_1-/eDP1_TX1-/DSI1_D1-S115
LCD1_VDD_ENS116
LVDS1_2+/eDP1_TX2+/DSI1_D2+S117
LVDS1_2-/eDP1_TX2-/DSI1_D2-S118
GND_44S119
LVDS1_3+/eDP1_TX3+/DSI1_D3+S120
LVDS1_3-/eDP1_TX3-/DSI1_D3-S121
LCD1_BKLT_PWMS122
RSVD_08S123
GND_45S124
LVDS0_0+/eDP0_TX0+/DSI0_D0+S125
LVDS0_0-/eDP0_TX0-/DSI0_D0-S126
LCD0_BKLT_ENS127
LVDS0_1+/eDP0_TX1+/DSI0_D1+S128
LVDS0_1-/eDP0_TX1-/DSI0_D1-S129
GND_46S130
LVDS0_2+/eDP0_TX2+/DSI0_D2+S131
LVDS0_2-/eDP0_TX2-/DSI0_D2-S132
LCD0_VDD_ENS133
LVDS0_CK+/eDP0_AUX+/DSI0_CLK+S134
LVDS0_CK-/eDP0_AUX-/DSI0_CLK-S135
GND_47S136
LVDS0_3+/eDP0_TX3+/DSI0_D3+S137
LVDS0_3-/eDP0_TX3-/DSI0_D3-S138
I2C_LCD_CKS139
I2C_LCD_DATS140
LCD0_BKLT_PWMS141
RSVD_09S142
GND_48S143
eDP0_HPDS144
WDT_TIME_OUTS145
PCIE_WAKES146
VDD_RTCS147
LIDS148
SLEEPS149
VIN_PWR_BADS150
CHARGINGS151
CHARGER_PRSNTS152
CARRIER_STBYS153
CARRIER_PWR_ONS154
FORCE_RECOVS155
BATLOWS156
TESTS157
GND_49S158
PCIE_A_RST# PCIE_B_RST#
USB_4_EN_OC#RESERVED_03RESERVED_04
PCIE_C_REFCK_PPCIE_C_REFCK_N
PCIE_A_REFCK_PPCIE_A_REFCK_N
PCIE_A_RX_PPCIE_A_RX_N
PCIE_A_TX_PPCIE_A_TX_N
HDMI_D2_P/DP1_LANE0_PHDMI_D2_N/DP1_LANE0_N
HDMI_D1_P/DP1_LANE1_PHDMI_D1_N/DP1_LANE1_N
HDMI_D0_P/DP1_LANE2_PHDMI_D0_N/DP1_LANE2_N
HDMI_CK_P/DP1_LANE3_PHDMI_CK_N/DP1_LANE3_N
HDMI_HDP/DP1_HPDHDMI_CTRL_CK/DP1_AUX_PHDMI_CTRL_DAT/DP1_AUX_NDP1_AUX_SELGPIO0/CAM0_PWRGPIO1/CAM1_PWRGPIO2/CAM0_RSTGPIO3/CAM1_RSTGPIO4/HDA_RSTGPIO5/PWM_OUTGPIO6/TACHINGPIO7GPIO8GPIO9GPIO10GPIO11
I2C_PM_CKI2C_PM_DATBOOT_SEL0#BOOT_SEL1#BOOT_SEL2#RESET_OUT#RESET_IN#POWER_BTN#SER0_TXSER0_RXSER0_RTS#SER0_CTS#
SER1_TXSER1_RXSER2_TXSER2_RXSER2_RTS#SER2_CTS#SER3_TXSER3_RX
CAN0_TXCAN0_RXCAN1_TXCAN1_RX
PCIE_C_RST#PCIE_C_RX_PPCIE_C_RX_N
PCIE_C_TX_PPCIE_C_TX_N
PCIE_B_REFCK_PPCIE_B_REFCK_N
PCIE_B_RX_PPCIE_B_RX_N
PCIE_B_TX_PPCIE_B_TX_N
DP0_LANE0_PDP0_LANE0_NDP0_AUX_SELDP0_LANE1_PDP0_LANE1_NDP0_HPDDP0_LANE2_PDP0_LANE2_N
DP0_LANE3_PDP0_LANE3_N
DP0_AUX_PDP0_AUX_NLCD1_BKLT_ENLVDS1_CK_P/eDP1_AUX_P/DSI1_CLK_P
LVDS1_D0_P/eDP1_TX0_P/DSI1_D0_PLVDS1_D0_N/eDP1_TX0_N/DSI1_D0_NeDP1_HPDLVDS1_D1_P/eDP1_TX1_P/DSI1_D1_P
LVDS1_CK_N/eDP1_AUX_N/DSI1_CLK_N
UDB3_OTG_ID
LVDS1_D1_N/eDP1_TX1_N/DSI1_D1_NLCD1_VDD_ENLVDS1_D2_P/eDP1_TX2_P/DSI1_D2_PLVDS1_D2_N/eDP1_TX2_N/DSI1_D2_N
LVDS1_D3_P/eDP1_TX3_P/DSI1_D3_PLVDS1_D3_N/eDP1_TX3_N/DSI1_D3_NLCD1_BKLT_PWMRESERVED_08
LVDS0_D0_P/eDP0_TX0_P/DSI0_D0_PLVDS0_D0_N/eDP0_TX0_N/DSI0_D0_NLCD0_BKLT_ENLVDS0_D1_P/eDP0_TX1_P/DSI0_D1_P
LVDS0_D2_P/eDP0_TX2_P/DSI0_D2_PLVDS0_D2_N/eDP0_TX2_N/DSI0_D2_NLCD0_VDD_ENLVDS0_CK_P/eDP0_AUX_P/DSI0_CLK_P
LVDS0_D1_N/eDP0_TX1_N/DSI0_D1_N
LVDS0_CK_N/eDP0_AUX_N/DSI0_CLK_N
LVDS0_D3_P/eDP0_TX3_P/DSI0_D3_PLVDS0_D3_N/eDP0_TX3_N/DSI0_D3_NI2C_LCD_CLKI2C_LCD_DATLCD0_BKLT_PWM
LID#SLEEP#VIN_PWR_BAD#
CHARGING#CHARGER_PRESENT#
eDP0_HPDWDT_TIME_OUT#PCIE_WAKE#
RESERVED_09
CARRIER_STANDBY#CARRIER_PWR_ONFORCE_RECOV#BAT_LOW#
TEST#
VDD_RTC
SMARC Design Guide 2.0 Page 21 of 119 Mar 23, 2017 ©SGeT e.V.
2.2 Module Power
2.2.1 Input Voltage Range
Per the SMARC Module Hardware Specification, the SMARC Modules may accept input power over the voltage range 3.0V to 5.25V. This range coincides with the range of a single-level lithium – ion cells and allows the use of common 5V or 3.3V fixed DC supplies.
2.2.2 Input Voltage Rise Time
There are currently no limits in the SMARC Module Hardware Specification on the Module power supply rise times. In general, it is not wise to expose the Module and Carrier electronics to extremely fast power supply rise times (as may be the case if a low impedance power source such as a battery pack or power brick is “hot-plugged”). Input power supply rise times faster than 50V / millisecond to the Module should be avoided. If a unit is to be “hot-plugged” to a low impedance power source, then the Carrier should implement measures to slow the power rise time as seen by the Module and Carrier circuits. The Carrier can do this by implementing a FET and hot-swap controller in the input power path. This is discussed in Section 9.5 Power Hot Swap Controller.
2.2.3 Module Maximum Input Power
The SMARC V2.0 specification document states that the allowable input voltage range is 3.0V to 5.25V. The rationale for this is that this range coincides with the voltage range of single level lithium-ion cells, and that it also allows the use of common 5V or 3.3V bench supplies. However, it is not mandatory in the V2.0 specification that Modules are required to work at the lower end (3.0V) of this range. The SMARC Module physical connector is a MXM3 connector (although the pinout is completely different). The MXM3 specification document requires that the MXM3 connector pins be able to carry 0.5A current minimum. SMARC Modules allocate 10 pins for input power (and 49 GND pins for signal and power return). Thus, per the MXM3 connector requirement, the 10 pins should be capable of handling 5A. This allows a maximum power input range of 15W (for 3.0V power in) to 26W (for 5.25V power in). For conservative design, let us operate the MXM3 connector pins at no more than 70% of their capacity. Then the following maximum power inputs are achieved:
10 pins * 0.5A * 70% * 3.0V = 10.5W (low end of Li-Ion battery) 10 pins * 0.5A * 70% * 4.75V = 16.6W (low end of 5V bench supply)
These numbers apply to the Module only, and not to the Carrier circuits. The 10.5W is adequate for low power Modules that are to be served by single level Lithium-Ion cells. The 16.6W should be adequate for higher power Modules (Including x86 designs) operating from a 5V supply.
2.2.4 Power Path
The power path for a basic, fixed input voltage arrangement SMARC Module and Carrier board system is shown in Figure 4 Basic Module and Carrier Power Path below. A number of features in the figure are optional and may be omitted (and bypassed) in a minimal implementation. The figure also shows Carrier Board power supply sections assuming a typical system powered by a power source in the 3.0V to 5.25V range
SMARC Design Guide 2.0 Page 22 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 4 Basic Module and Carrier Power Path
SMARCModule
Optional
Power
SupervisorVIN_PWR_BAD#
RESET_IN#
PWR_BTN#
VDD_IN
Open Drain - pulled
low if input power
is out of spec
CARRIER_PWR_ON
EN
IN OUT
IN OUT
EN
LCD_BKLT_EN
IN
EN
OUT
IN
IN
EN
EN
OUT
OUT
V_5V0
V_BKLT
V_3V3
V_1V8
V_1V5
USB Power
Switches
LCD Backlight
Voltage depends on
backlight type
Mini-PCIe
SATA MO-300
USB Hub
General Purpose 3.3V
Module I/O
Low voltage I2C and
I2S peripherals
Mini PCIe
SATA MO-300
Optional
Hot Swap
Controller + FET
Carrier Board Power Supplies – Enabled by Module CARRIER_PWR_ON signal
FET Switch (if 5V input)
Buck-Boost Converter (if 3.0 to 5.25V input)
Boost converter (if 3.3V input)
RESET_OUT#Active low reset
to Carrier Board
Boost Converter
Buck Converter (if 5V input)
Buck-Boost (if 3.0 to 5.25V)
FET Switch (if 3.3V input)
Optional
Common – Mode
Choke / Filter
Buck Converter
Buck Converter
Optional
LDO V_1V8_ALWAYS
For optional I2C_PM
Periphals that need to be
powered when
CARRIER_PWR_ON
Is inactive
V_IN
V_IN_RAW
I2C_PM
Optional I2C_PM
devices active when
CARRIER_PWR_ON
is low
Power
domain
Isolation
I2C_PM
devices active when
CARRIER_PWR_ON
is high
V_1V8_ALWAYS
Power Rail
V_1V8
Power Rail
Module IO Module – Carrier IO
.
SMARC Design Guide 2.0 Page 23 of 119 Mar 23, 2017 ©SGeT e.V.
2.3 Module I/O Voltage
The SMARC Module Hardware Specification specifies the use of 1.8V Module I/O I/O at 1.8V is used in general for low power interfaces. Many contemporary peripherals of interest are available with I/O interfaces that support 1.8V and 3.3V; some are available at 1.8V only, and others at 3.3V only. Specific examples are given in various document sections below. If devices that support only 3.3V are implemented, a level shifter has to be used to interface them to the SMARC Module.
SMARC Design Guide 2.0 Page 24 of 119 Mar 23, 2017 ©SGeT e.V.
2.4 VIN_PWR_BAD#
This optional signal may be used to tell the Module that the input power to the Module is not ready. An open-drain driver should be used.
2.5 CARRIER_PWR_ON
The CARRIER_PWR_ON signal is driven by the Module at a 1.8V level. It is a signal to Carrier that the Carrier board specific power supplies may be enabled. This is illustrated in Figure 4 Basic Module and Carrier Power Path above.
2.6 Reset In to Module
The SMARC RESET_IN# signal may be used to force a SMARC system reset. It is an input to the Module. The signal is pulled up on the Module. If used, by the Carrier board, then an open drain device or switch to GND should be used. A switch example is shown in the following figure. The signal is ESD protected in this example, as the switch (and the switch interaction with humans) introduces an ESD hazard.
Figure 5 Reset Switch
MOD
TH
Panasonic EVQ-PBC04MSW1
G
A1
A2
B1
GND
B2
D212
3
1
50V100nF
21C285
V_MOD_IN
RESET_IN#
SMARC Design Guide 2.0 Page 25 of 119 Mar 23, 2017 ©SGeT e.V.
2.7 Power Button
SMARC defines a pin to allow the implementation of a Carrier based power button. However - caution - the SMARC Hardware Specification does not define the power up behavior of a Module. The following possibilities exist after a cold power on:
a) Module boots
b) Module waits for a Power Button press to boot
c) The Module is configurable – either behavior a) or behavior b) may be configured
Users are advised to check with your Module vendor on this topic. A Power Button switch example is shown in the figure below. If your Module waits for a Power Button press on power up and you want it to always boot on power up, you have to arrange for a “power button press” on power up, using an open drain device to interface to the SMARC Module.
Figure 6 Power Button Switch
MOD
TH
G
SW2Panasonic EVQ-PBC04M
A1
A2
B1
GND
B2
D202
3
1
C284
50V100nF
21
V_MOD_IN
POWER_BTN#
SMARC Design Guide 2.0 Page 26 of 119 Mar 23, 2017 ©SGeT e.V.
2.8 Force Recovery
Some Modules support a “force recovery” function in which the primary boot media can be re-initialized over a designated I/O interface, such as a USB client interface, asynchronous serial port, or Ethernet port. This is Module specific; refer to your Module documentation for further details.
Figure 7 Force Recovery Switch
MOD
D222
3
1
C283100nF50V
21
SW3Panasonic EVQ-PBC04M
TH
G
A1
A2
B1
GND
B2
V_MOD_IN
FORCE_RECOV#
SMARC Design Guide 2.0 Page 27 of 119 Mar 23, 2017 ©SGeT e.V.
2.9 Power Up Sequence
The basic power up sequence for SMARC Modules and Carriers is shown in the following two figures. There is a Module design and / or configuration dependence with regard to the power button behavior. Depending on design and / or configuration, the Module may always boot without waiting for a power button press, or it may wait for a power button press. These cases are shown in the figures. It is recommended to arrange that the main Carrier power supplies not come up until the Module asserts the CARRIER_PWR_ON signal. When this is high, you know that the Module power supplies are all up. If the Carrier power is up before the Module supplies are up, there is a risk that the Carrier circuits will back-feed power to the Module I/O pins, which might interfere with a Module boot.
Figure 8 SMARC Carrier Power up Sequence - No Power Button Case
POWER IN (3-5.25V)
V_MOD_IN (3-5.25V)
POWER_BTN#
CARRIER_PWR_ON
CARRIER_STBY#
Carrier Power Rails
V_5V0
V_3V3
V_1V8
V_1V5
RESET_OUT#
ACPI-State
(only for x86 designs)S0S5 >> S3
SMARC Design Guide 2.0 Page 28 of 119 Mar 23, 2017 ©SGeT e.V.
The case of a Module that is designed or configured to wait for a power button press before it comes up is diagramed below. When power is applied to the Module, in this case, only a small portion of the Module is using that power – typically, the Module Power Management section – and that circuitry waits for a power button press. When it sees one, the Module proceeds with the boot. When the main Module power rails are up, the Module asserts CARRIER_PWR_ON. The Carrier should use this signal to enable the various Carrier power rails. However, Carrier circuits that are involved in power management (battery charge level, reset monitors, etc.) may be powered ahead of CARRIER_PWR_ON, coincident with the Module power.
Figure 9 SMARC Carrier Power up Sequence - With Power Button Case
POWER IN (3-
5.25V)
V_MOD_IN (3-
5.25V)
POWER_BTN#
CARRIER_PWR_ON
CARRIER_STBY#
Carrier Power Rails
V_5V0
V_3V3
V_1V8
V_1V5
RESET_OUT#
ACPI-State
(only for x86 designs)S0S5 >> S3
NOT x86 chipset
Power button signal
2.9.1 CARRIER_STBY#
A low level on CARRIER_STBY# indicates that the system is going into the standby state, where only power management functions and system memory are powered. The ACPI equivalent is suspend to ram (S3). This signal can be used to switch off power supplies on the Carrier board that are not necessarily needed during standby. Any devices that should be able to wake the system out of the standby state should use the CARRIER_PWR_ON signal instead.
SMARC Design Guide 2.0 Page 29 of 119 Mar 23, 2017 ©SGeT e.V.
2.10 Boot Selection
2.10.1 Boot Definitions
Most SOCs used on SMARC Modules have the following attributes:
1) An internal ROM exists. The internal ROM code is executed after the SOC comes out of reset. This ROM code is provided by the silicon vendor and is generally not available or visible to users.
2) A set of SOC strap pins is used to select what SOC physical device interface (SD Card, SPI, eMMC, etc.) will be used for the second – stage boot process (also known as BCT or Boot Configuration Table boot). There is no commonality between various SOCs as to how the strap pins are defined.
3) The SOC pin configuration is very flexible – most SOC pins can be used for several functions, and the SMARC Module designer must choose a pin configuration that works for the design at hand. The SOC pin configuration is set by a Boot Configuration Table that is read out from the external boot media (SD Card, SPI, eMMC, etc.).
There are several stages in the boot process:
1) Internal SOC ROM execution
2) second stage boot, from non-volatile memory external to the SOC: BCT is loaded and various other system parameters are set
3) Operating System load
The Operating System load may occur from the same memory as the second stage BCT boot, or the second stage code may pass the Operating System load off to another device, such as a USB drive or SATA drive.
SMARC Design Guide 2.0 Page 30 of 119 Mar 23, 2017 ©SGeT e.V.
2.10.2 SMARC BOOT_SEL Pins
The SMARC Hardware Specification defines 3 SMARC pins, designated BOOT_SEL0# through BOOT_SEL2#, that may be used to tell the Module what physical device to do a BCT boot from. The SMARC BOOT_SELx# pins serve to abstract the SOC – dependent strap definitions into a common SMARC definition. The table below is reproduced from the SMARC Hardware Specification document.
Table 2 Boot Select Pins
Carrier Connection BOOT_SEL2# BOOT_SEL1# BOOT_SEL0#
Boot Source
0 GND GND GND Carrier SATA
1 GND GND Float Carrier SD Card
2 GND Float GND Carrier eMMC Flash
3 GND Float Float Carrier SPI
4 Float GND GND Module device (NAND, NOR) – vendor specific
5 Float GND Float Remote boot (GBE, serial) – vendor specific
6 Float Float GND Module eMMC Flash
7 Float Float Float Module SPI
The Module BOOT_SELx# pins may be set by jumpers on the Carrier Board, as shown in the figure below. The diodes and capacitors are for ESD protection, as the jumpers may experience ESD events. Alternatively, the BOOT_SELx# pins can be set by low value option resistors to GND on the Carrier. The resistors are either installed (for a GND connection) or not installed, per the table above.
Figure 10 Boot Selection Jumpers
THT2/1x2/2.54
FCI 77311-118-02LFJ45
2
11
2
THT2/1x2/2.54
FCI 77311-118-02LFJ46
2
11
2
D232
3
1 D24
2
3
1
C286100nF
50V
21
C287
50V100nF
21C288
50V100nF
21
D25
2
3
1
R288
0402
1KOhm
21
1KOhmR289
0402
21
R290
0402
1KOhm
21
V_MOD_INV_MOD_IN
V_MOD_IN
MOD MODMOD
THT2/1x2/2.54
FCI 77311-118-02LFJ44
2
11
2
BOOT_SEL0#BOOT_SEL2# BOOT_SEL1#
SMARC Design Guide 2.0 Page 31 of 119 Mar 23, 2017 ©SGeT e.V.
2.11 RTC Backup Power
The Module RTC (Real Time Clock) circuit requires a backup power source if the Module RTC circuit is expected to keep time in the absence of the primary power source (i.e. the power to Module VDD_IN pins, P147 through P156). The RTC backup power, if used, is applied to the Module VDD_RTC pin, pin S147. The RTC backup power may be provided by a battery or by a large value capacitor, known as a “Supercap”. If a battery is used, the battery is typically a small lithium coin cell with a capacity of a few hundred mAh. Lithium coin cells offer a high energy density, low self-discharge rate, and are not rechargeable. For safety reasons, they must be protected against charging on the Carrier board by a redundant set of circuit elements – typically either two diodes in series or a diode and a resistor. The resistor, if used, must be large enough to limit the battery charging current to be equal to or lower than the amount specified as allowable by the battery vendor. The safety aspects of lithium battery use is governed by a UL document (UL 1642 Lithium Batteries, www.ul.com). The Supercap solution differs from the lithium battery solution in that it needs to be charged by the Module (when the Module has its primary power source); hence a blocking diode should not be used with the Supercap. The time period over which the RTC backup power is effective depends on the Module RTC backup current draw, the exact voltage range over which the Module RTC circuit is functional, on the capacity characteristics of the battery or Supercap, on the drops incurred across the Carrier board circuit protection elements, and on the operating temperature. In general terms, a suitable lithium battery solution can provide RTC backup current on a scale of years; the Supercap solution on a scale of days to weeks.
Figure 11 RTC Backup: Coin Battery / Super Cap
0402
1KOhm
R269
21
0402 R270
1KOhm
21
Renata SMTU2032-LFBT1
2PSMT
21
+
-
V_3V0_RTC
3.3V200mF
Elna DSK-3R3H204T614-H2L
C2401
2
V_3V0_RTC
Vishay BAT54W-V
D12
CA
Coin Battery Holder, R/A, SMT
Super Cap
SMARC Design Guide 2.0 Page 32 of 119 Mar 23, 2017 ©SGeT e.V.
2.12 Reserved / Test Interfaces
The Module TEST# pin (pin S157) should normally be left not connected. If pulled low, then Module specific test function(s) may be enabled. Reserved pins should be left not connected and may be used in future revisions of the SMARC specification.
SMARC Design Guide 2.0 Page 33 of 119 Mar 23, 2017 ©SGeT e.V.
3 DISPLAY INTERFACES
3.1 Module LVDS
3.1.1 NEC 1280 x 768 Single Channel LVDS Example
The Module LVDS interface may be used with single channel LVDS displays. SMARC Modules typically support LVDS 18 bit single channel operation (three data pairs plus one clock pair). They may also support LVDS 24 bit single channel operation (four data pairs plus one clock pair). Recall that there are two 24 bit color mappings in common use: most significant color bits on fourth data pair (sometimes referred to as the standard 24 bit mapping), and least significant color bits on the fourthLVDS data pair (referred to as 24 bit / 18 bit compatible or as 24 bit / 6 bit pack or similar). The standard 24 bit color mapping is more common but is incompatible with the 18 bit packing. The example below shows an implementation used with an NEC 1280 x 768 single channel LVDS panel (NL 12876AC18-03). This panel uses a discrete wire 30 pin Hirose DF19 series connector. The panel backlight electronics accepts a 12V supply, and panel brightness is controlled by a 3.3V PWM signal. There is no EDID EEPROM on this particular NEC display. This display happens to support 18 bit, 24 bit / 18 bit compatible and standard 24 bit LVDS packings. The panel also allows the image to be reversed. This can be useful if you find the panel connector orientations to be inconvenient – you can rotate the display 180 degrees, alter the scan direction strap, and have the image appear in the correct orientation. These options are set by pull-up and pull-down choices on connector pins 11, 26 and 27 in the image below. Refer to the display data sheet for further information. The display LVDS data and clock differential pairs may be connected directly to the SMARC Module. The backlight PWM and panel enable need level translation and / or buffering as shown in the figure.
Figure 12 Module LVDS: NEC Single Channel Display
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
V_3V3
21
R52
DNI0402
1KOhm
10V
C1381uF
2
1 C14122uF10V
2
1
C173
16V1uF
2
1
SMT
J2
Hirose DF19G-30P-1H
30/1x30/1.0
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
M1
M2
4.7KOhmR19
0402
21
V_3V3
1KOhmDNI0
402
R53
21
TI TPS22924C
U3
BGA6
B1
A1
C1
C2
B2
A2VIN_A2
VIN_B2
ON
GND
VOUT_A1
VOUT_B1
V_3V3
V_12V0
R511KOhm
0402
21
DNI0402
R184.7KOhm
21
0402
R20
4.7KOhm
21
MOD
0402
R1690Ohm
21
25V100nFC116 2
1
C117100nF25V
2
1
MOD
V_1V8
U9TI SN74AVC2T244DQ
MicroQFN8
1
2 7
6
54
8
3 A2
VCCB
OE# GND
B2
B1A1
VCCA
V_3V3
10KOhm
DNI
R240
0402
21
V_1V8
MOD
V_3V3
C183470nF6.3V2
1
1uF16V
C174
2
1
0402
100KOhmR257
21
MOD
LVDS_CK_P
LVDS3_N
LVDS3_P
LVDS_CK_N
LVDS2_N
LVDS2_P
LVDS1_N
LVDS1_P
LCD_BKLT_EN
LVDS0_N
LVDS0_P
LCD_VDD_EN
SIX_BIT_PACK#
SC
MODE
LVDS_BKLT_PWM_3V3LVDS_BKLT_PWM_3V3
BUFFER_OE#
LVDS_BKLT_EN_3V3
LVDS_BKLT_EN_3V3
LCD_BKLT_PWM
V_3V3_SWITCHED_A
V_3V3_SWITCHED_A
Vil = 0.6V
Vih = 1.2 V
NEC Panel Connector
30 Pin, 1mm Pitch, R/A, SMT
SMARC Design Guide 2.0 Page 34 of 119 Mar 23, 2017 ©SGeT e.V.
Power for the display’s logic is gated by the Module LCD_VDD_EN signal, as shown above. The NEC LVDS display in the example above accepts a 12V feed to power the display’s LED backlight. The SMARC Module provides two backlight control signals, LCD_BKLT_EN and LCD_BKLT_PWM (enable and brightness). Some displays require a higher voltage feed to their LED backlight electronics. An example of this is given in Section 9.6 High Voltage LED Supply.
SMARC Design Guide 2.0 Page 35 of 119 Mar 23, 2017 ©SGeT e.V.
3.1.2 LVDS Dual Channel example
The schematic example below shows an implementation on the Carrier that can be used either for a dual channel LVDS display or two single channels LVDS displays with common supply voltage. The LVDS signals are routed through common mode chokes to the LVDS connector. All display signals include ESD devices. Supply voltage for LVDS display and backlight can be selected by jumper settings. The control signals for backlight, LVDS display and I2C bus are routed over level shifters from 1.8V on SMARC connector side to the display I/O voltage. Additional comments to schematic example: • Signal LVDS_VDDEN:
If FET power switching is used this signal pin can also be connected to EN_PANELPOWER instead of PG_VPANEL. In this case PU resistor R15 and diode D1 can be removed.
• LVDS connector type: Neither connector type nor pinout of the connector underlies any standards specification. So everyone is free to select a suitable LVDS connector for best application fit.
• Comment on jumper settings: CN1-JP1: Default: JP1 shorting 1-2 => Panel supply = 3.3V Alternate: JP1 shorting 5-6 => Panel supply = 5.0V CN2-JP2: Default: JP2 shorting 3-4 => Backlight voltage = 12.0V Alternate: JP2 shorting 5-6 => Backlight voltage = 5.0V
• Comment on alternate power switching: If leakage currents are not considered as an issue for the design, the load switch might be replaced by a P-Channel FET and N-Channel FET for the Gate control.
• Comment on different power rails for both LVDS channels: It might be considered to implement different voltage rails for both channels, which is not covered with this design example.
• Comment on ESD-Devices: Place the ESD device close to the LVDS connector and close to the backlight pin header.
In a LVDS implementation with two single LVDS channels, the panel EDID EEPROMs would be in conflict and measures need to be taken to avoid this. One possible solution is that the second LVDS EDID EEPROM could be read over the I2C_GP pin pair rather than the I2C_LCD pin pair.
SMARC Design Guide 2.0 Page 36 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 13 LVDS Dual Channel
Figure 14 LVDS Dual Channel Power Supply
+VDD_PANEL
+VDD_PANEL
+VDD_PANEL
+VDD_PANEL
+VDD_PANEL +VCC_BKLT
+VDD_PANEL +VDD_PANEL+V1P8
+V1P8
+VDD_PANEL+VDD_PANEL
+VDD_PANEL
+VDD_PANEL
+VDD_PANEL
DDC_CKDDC_DAT
PG_VPANEL
LVDS0_CK-LVDS0_CK+
LVDS0_3-LVDS0_3+
LVDS0_2-LVDS0_2+
LVDS0_1-LVDS0_1+
LVDS0_0-LVDS0_0+
LVDS1_CK-LVDS1_CK+
LVDS1_3-LVDS1_3+
LVDS1_2-LVDS1_2+
LVDS1_1-LVDS1_1+
LVDS1_0-LVDS1_0+
I2C_LCD_CK
I2C_LCD_DAT
LCD_BKLT0_CTRLLCD_BKLT0_EN
LCD_BKLT1_CTRLLCD_BKLT1_EN
BKLT0_VDD_EN
TVS6RCLAMP0504FA
1234 5 6
CN5
BH_8_S2.54mm
1 23 45 67 8
ESD6
RClamp7534P.TNT
2
34
51
L7
90_100MHz_0.5A
1 2
4 3
TV
S5
06
03
-24
0E
2R
5P
P
12
L2
90_100MHz_0.5A
1 2
4 3
C150.1uF_16V
ESD2
RClamp7534P.TNT
2
34
51
C1
12
20
pF
_5
0V
R82.2K_+-1%
TVS3
0603-240E2R5PP
12
CN3
BH_34_S2.0mm
1 23 45 67 89 10
11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 34
TV
S4
06
03
-24
0E
2R
5P
P
12
C130.1uF_16V
ESD3
RClamp7534P.TNT
2
34
51
L8
90_100MHz_0.5A
1 2
4 3
R92.2K_+-1%
R15100K_+-1%
L3
90_100MHz_0.5A
1 2
4 3
L10
90_100MHz_0.5A
1 2
4 3
D1
USCD022HA K
C9 0.1uF_16VL4
90_100MHz_0.5A
1 2
4 3
L9
90_100MHz_0.5A
1 2
4 3
L5
90_100MHz_0.5A
1 2
4 3
R2
01
00
K_
+-1
%
C10 0.1uF_16V
R2
11
00
K_
+-1
%
C170.1uF_16V
C1
22
20
pF
_5
0V
TVS7RCLAMP0504FA
1234 5 6
ESD5
RClamp7534P.TNT
2
34
51
TVS2
0603-240E2R5PP
1 2
C8 0.1uF_16V
ESD1
RClamp7534P.TNT
2
34
51
TVS1RCLAMP0504FA
1234 5 6
R2
31
00
K_
+-1
%
C160.1uF_16V
S1
S2D1
D2G1
G2
Q5BSS138DW-7-F_0.2A/50V
6
34 5
2 1
C140.1uF_16V
L6
90_100MHz_0.5A
1 2
4 3
ESD4
RClamp7534P.TNT
2
34
51
L1
90_100MHz_0.5A
1 2
4 3
CN4
BH_8_S2.54mm
1 23 45 67 8
R2
41
00
K_
+-1
%
LVDS_VDDENLVDS0_L_0+LVDS0_L_0-
LVDS0_L_1-LVDS0_L_2+LVDS0_L_1+
LVDS0_L_2-
LVDS0_L_3+LVDS0_L_3-
LVDS0_L_CK+LVDS0_L_CK-
LVDS1_L_0+LVDS1_L_0-
LVDS1_L_1+LVDS1_L_1-
LVDS1_L_2+LVDS1_L_2-
LVDS1_L_3+ LVDS1_L_3-
LVDS1_L_CK+LVDS1_L_CK-
LVDS0_L_0-LVDS0_L_0+
LVDS0_L_1+LVDS0_L_1-
LVDS0_L_2+LVDS0_L_2-
LVDS0_L_3+LVDS0_L_3-
LVDS0_L_CK+LVDS0_L_CK-
BKLT0_CTRLBKLT0_EN
DDC_DAT
DDC_CK
DDC_DAT
DDC_CK
BKLT1_CTRLBKLT1_EN
LVDS1_L_0-LVDS1_L_0+
LVDS1_L_1+LVDS1_L_1-
LVDS1_L_2+LVDS1_L_2-
LVDS1_L_3+LVDS1_L_3-
LVDS1_L_CK+LVDS1_L_CK-
LVDS0_L_0+LVDS0_L_0-
LVDS0_L_1+
LVDS0_L_2+
LVDS0_L_1-
LVDS0_L_2-
LVDS0_L_3+
LVDS0_L_CK+
LVDS0_L_3-
LVDS1_L_0+
LVDS0_L_CK-
LVDS1_L_1-
LVDS1_L_0-
LVDS1_L_1+
LVDS1_L_2+LVDS1_L_2-
LVDS1_L_3-
LVDS1_L_CK+
LVDS1_L_3+
LVDS1_L_CK-
DDC_CKDDC_DAT
MOD
MOD
MODMOD
MOD
MOD
MOD
MOD
MOD
MOD
MODMOD
MODMOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
+V1P8S
+VDD_PANEL
+V1P8S
+VDD_PANEL
+V3P3_IN
+V5P0_IN
+V12P0_IN +VLCD_12P0
+VLCD_5P0
+VLCD_3P3
+VLCD_5P0
+VLCD_12P0
+VLCD_5P0
+VCC_BKLT
+VDD_PANEL
+VLCD_3P3
+VLCD_5P0
+VLCD_5P0
+VLCD_3P3
LCD0_VDD_ENLCD0_BKLT_PWM
LCD0_BKLT_EN
LCD1_VDD_EN
LCD1_BKLT_ENLCD1_BKLT_PWM LCD_BKLT1_CTRL
LCD_BKLT1_ENLCD_BKLT0_CTRLLCD_BKLT0_EN
PG_VPANEL
B3 120_100MHz_5A
R2
100K_+-1%
U1
SN74AUP1T97DCKR
B1
GND2
A3
Y4
VCC5
C6
CN
2
PH
_6
_S
2.0
mm
12
34
56
B2 120_100MHz_5A
C10.1uF_10V
B1 120_100MHz_5A
C60.1uF_10V
R3
100K_+-1%
TC122uF_25V
U4
TXB0104_QFN12
VC
CA
1
A12
A23
A34
A45
GND6
OE12
B47
B38
B29
B110V
CC
B1
1
JP2
MINI-JUMP_2_S2.0mm
U5
TXB0104_QFN12
VC
CA
1
A12
A23
A34
A45
GND6
OE12
B47
B38
B29
B110V
CC
B1
1
R110K_+-1%
JP1
MINI-JUMP_2_S2.0mm
C40.1uF_10V
C30.1uF_10V
TC222uF_25V
U2
NCP45520IMNTWG-H_ON
Vin11
EN2
Vcc3
GND4
BLEED5
PG6
Vout7
Vin29
CN
1
PH_6_S2.0mm
12
34
56
C70.1uF_10V
U3
NCP45520IMNTWG-H_ON
Vin11
EN2
Vcc3
GND4
BLEED5
PG6
Vout7
Vin29
C50.1uF_10V
F2
F_
MF
-SM
20
0-2
12
C20.1uF_10V
+VCC_BKL_IN
+VLCD_12P0_F
+VDD_PANEL_INEN_PANELPOWER
LCD_PANEL1_VDD_EN
LCD_PANEL0_VDD_EN
PG_VPANEL
LCD_PANEL0_VDD_EN
LCD_PANEL1_VDD_EN
LCD_PANEL0_VDD_EN LCD_PANEL1_VDD_ENMODMODMOD MOD
MODMOD
SMARC Design Guide 2.0 Page 37 of 119 Mar 23, 2017 ©SGeT e.V.
3.1.3 Display Parameters and EDID
Flat panel display parameters (horizontal resolution, vertical resolution, pixel clock rate, blanking periods, etc.) may be hard-coded into a boot-loader or they may be read by boot-loader code from an industry standard data structure known as EDID (Extended Display Identification Data). EDID data is stored in an EEPROM accessed via I2C. The EDID EEPROM may reside on the display assembly or elsewhere in the path between the SOC and the display – on the Carrier or on a display adapter assembly. If the EDID EEPROM resides on the display, then the cabled interface to the display must include the SMARC Module I2C_LCD interface. The interface should be level translated and possibly buffered. The I2C voltage levels on the display are most likely to be at 3.3V levels. A set of back-to-back FETs may be used for I2C level translation, as shown in the figure immediately below. Alternatively, a device such as the Fairchild FXMA2102 I2C buffer / level translator may be used. There is a circuit example using the FXMA2102 later in this document. In the display interface example above, with the 30 pin Hirose DF19 series connector, pins 9 and 10 could be used for the buffered I2C_LCD clock and data, respectively. The figure below shows an EDID EEPROM implementation that may be used on a Carrier. It might be advantageous to use a socket for the EEPROM to allow display parameters to be swapped out. Alternatively, system software could update the EEPROM if the EEPROM WP (Write Protect) pin is set to enable writes. Or, the system designer could implement an EEPROM programming header for update purposes. Caution: if there is an EDID EEPROM on the Carrier and on the display, there will be an I2C address conflict unless one of the two is disabled or set to an alternate address. VESA EDID EEPROMs are expected at 7 bit I2C address 0x50. There are many EDID editors available, some for free. It can be very useful to have access to one if you are trying to adapt a new panel, and if your SMARC Module software knows what to do with EDID data. Alternatively, your SMARC Module and / or Carrier board vendor may well be able to help with display adaptations.
Figure 15 Carrier EDID EEPROM
V_3V3
V_1V8
MOD
MOD
V_1V8
R241
0402
10K
Ohm
21
R242
0402
10K
Ohm
21
DiodesInc BSS138DW-7-F
Q4
35
4
DN
I10K
Ohm
R2
43
0402
21
0402
DN
I10K
Ohm
R2
44
21
R2
45
DN
I10K
Ohm
0402
21
0402
R2
59
2.4
9K
Ohm
21
2.4
9K
Ohm
0402
R2
60
21
0402
2.4
9K
Ohm
R2
61
21
V_3V3
C118
100nF25V2
1
V_3V3
R24
6
DN
I10K
Ohm
0402
21
V_3V3
R2
47
0402
10K
Ohm
21
Atmel AT24HC02
SOIC8
U13
8
7
6
5
43
2
1A0
A1
A2 GND
SDA
SCL
WP
VCC
DiodesInc BSS138DW-7-F
Q3
62
1
Q3
35
4
Q4
62
1I2C_LCD_DAT
I2C_LCD_DAT
I2C_LCD_CK
I2C_EDID_CK
I2C_ADDR_A0
I2C_ADDR_A1
I2C_ADDR_A2
I2C_WP
I2C Addr :0x50
(7 bit Address)
SMARC Design Guide 2.0 Page 38 of 119 Mar 23, 2017 ©SGeT e.V.
3.2 HDMI
Note: a license may be needed to market HDMI capable products. Check with the HDMI organization (www.hdmi.org) and with your SMARC Module vendor. The SMARC HDMI data pairs may be routed directly from the SMARC Module pins to a suitable Carrier HDMI connector. Since HDMI is a hot-plug capable interface, it is important for the Carrier to implement ESD protection on all of the HDMI lines. The ESD protection on the data lines must be low capacitance so as not to degrade high speed signaling. The data lines must route through the ESD protection device pins in a no-stub fashion. The ESD protection should be located close to the HDMI connector. The SMARC pins HDMI_CTRL_CK and HDMI_CTRL_DAT require level translation from V_1V8 to the 5V levels that HDMI uses on those pins. These lines also require pull-up resistors to V_1V8 (the pull-ups are not included on the SMARC Module, because integrated HDMI protection devices such as the Texas Instruments TPD12S016 include the pull-ups in their parts). And, finally, 5V power switching / current limiting to the HDMI connector is required on the Carrier. The ESD protection, level translation and power switching / limiting are all dealt with in integrated devices such as the TI TPD12S016. A circuit diagram is shown in the following figure. The TPD12S016 must be placed close to the HDMI connector, and the HDMI data traces routed in daisy chain fashion (and as differential pairs) from the SMARC Module pins, to and through the TPD12S016 pins, and on to the HDMI connector pins. The TPD12S016 pin-out is specifically designed to facilitate this.
Figure 16 HDMI Implementation
MOD
MOD
MOD
MOD
0402R96
0Ohm
2 1
MOD
MOD
MOD
MOD
TSSOP24
U22
TI TPD12S016
19
14
6
3
2
1
4
5
12
11
24
13
9
8
7
16
15
17
18
20
21
22
23
10HPD_B-
D2+
D2-
D1+
D1-
D0+
D0-
CLK-
CLK+
CEC_B
SCL_B
SDA_B
5V_OUT
VCCA
VCC5V
CT_HPD
LS_OE
HPD_A-
CEC_A
SCL_A
SDA_A
GND_6
GND_14
GND_19
MOD
4.7KOhmR3
DNI 04
02
2
1
MOD
C31
25V100nF
2
1
V_5V0 V_1V8
C1551uF16V
2
1
MOD
R4
04
02
4.7KOhm
2
1
19/1/0.5
SMT
FCI 10029449-001TLF
J25
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1TMDS_DATA2_P
TMDS_DATA2_SHLD
TMDS_DATA2_M
TMDS_DATA1_P
TMDS_DATA1_SHLD
TMDS_DATA1_M
TMDS_DATA0_P
TMDS_DATA0_SHLD
TMDS_DATA0_M
TMDS_CLK_P
TMDS_CLK_SHLD
TMDS_CLK_M
CEC
RSVD
SCL
SDA
DDC/CEC_GND
5V
HPD
MH
1
MH
2
MH
3
MH
4
25V100nFC32
2
1
10uF16V
C216
2
1
HDMI_CTRL_DAT
HDMI_CTRL_CK
HDMI_HPD_CONN
HDMI_DDC_SDA_5V0
HDMI_DDC_SCL_5V0
HDMI_HPD
CT_HPD
LS_OE
V_5V0_HDMI
HDMI_D2_P
HDMI_D2_N
HDMI_D1_P
HDMI_D1_N
HDMI_D0_N
HDMI_D0_P
HDMI_CK_N
HDMI_CK_P
HDMI_D2_P
HDMI_D2_N
HDMI_D1_P
HDMI_D1_N
HDMI_D0_P
Layout Note :
without any stubs
The HDMI trace pairs are to be routed
from the SMARC connector, through the
TPD12S016 pads and to the HDMI connector,
HDMI_D0_N
HDMI_CK_P
HDMI_CK_N
HDMI, R/A, SMT
SMARC Design Guide 2.0 Page 39 of 119 Mar 23, 2017 ©SGeT e.V.
3.3 DisplayPort (DP++)
DisplayPort is directly supported by a dual-source DDI. ESD protection, DC blocking capacitors and hot plug detect are the only components required. The DisplayPort differential data pairs (Lane [0..3]) are AC coupled off Module with capacitors C19-C26. Place the AC blocking capacitors close to the DisplayPort connector. The Aux differential pair is AC coupled on the Module. ESD clamping diodes D1, D2 and D3 protect the Module from external ESD events and should be placed near the DisplayPort connector. The pin-out of the ESD clamp diodes allows for a trace to run under the chip connector to two pins. The Carrier provides up to 500 mA of 3.3V power to the DisplayPort connector. Diode D71 prevents back feeding of power in the event that the monitor is powered up when the Carrier is powered down. Config lines 1 and 2 are pulled to ground per the VESA specification. The DisplayPort Hot Plug Detect signal is buffered by U50 which prevents back feeding of power from the display to the Module as well as level translation to 3.3V levels. R14 connect logic and chassis ground together. Other techniques may be used depending on the overall grounding strategy. Note: The reference schematics assume that the Module’s DisplayPort is dual-source capable – dual source indicates that the Module can output DisplayPort or HDMI/DVI based on the DDC_AUX_SEL signal.
Figure 17 DisplayPort ++
3.3.1 HDMI over DP++
A Dual-mode source Module requires level shifters on the Carrier to convert the low-swing AC coupled differential pairs from the video source to HDMI compliant current mode differential outputs. The example schematics use a Chrontel CH7318C translator which supports data rates up to 1.65GB/s per lane. FET based passive level translators can be used for lower data rates. The DisplayPort AUX channel is configured as a DDC interface for HDMI. Further information on pre-emphasis as well as output current trim capabilities of the CH7318C can be found in the Chrontel datasheet.
i max. 500 mA
0.5A
DP0_HPD_C
V3.3_S0_DP_3
DP0_LANE1_C-
V3.3_S0_DP_3
DP0_LANE0_C+
DP0_LANE0_C-
DP0_Config2
DP0_LANE1_C+
DP0_LANE1_C-DP0_LANE2_C+
DP0_LANE2_C-
DP0_LANE1_C+
DP0_LANE3_C+
DP0_LANE3_C-
DP0_LANE3_C+
DP0_LANE2_C-
DP0_LANE2_C+
DP0_LANE3_C-
DP0_LANE0_C-
DP0_LANE0_C+
DP0_HPD_C
DP0_HPD_C
DP0_CTRLDATA_AUX-
DP0_CTRLCLK_AUX+
DP0_HPD_B
V_3V3
V_1V8
MODDP0_LANE0+
MODDP0_LANE0-MODDP0_LANE1+
MODDP0_LANE1-MODDP0_LANE2+
MODDP0_LANE2-MODDP0_LANE3+
MODDP0_LANE3-
MODDP0_HPD
MODDP0_AUX_SEL
MODDP0_AUX+
MODDP0_AUX-
U50
NC7SZ125 1
2
3
4
5
R16
1M
1%
C24
J3
Molex 47272-0001
ML_Lane0+GNDML_Lane0-ML_Lane1+GNDML_Lane1-ML_Lane2+GNDML_Lane2-ML_Lane3+GNDML_Lane3-Config1Config2AUX CH+GNDAUX CH-Hot PlugReturnDP_PWR
S1
S1
S2
S2
S3
S3
S4
S4
R32
0R
5%
C25
D71
MBR130LSFT1
C21
R15
5M1
FB4
60R@100MHz
C26
R46
100k
1%
D1
Rclamp 0524P
5
1
4
29
3
10
7
6C23
R14
0R
5%
D2
Rclamp 0524P
5
1
4
29
3
10
7
6
C20
C19
C22
D3
Rclamp 0524P
5
1
4
29
3
10
7
6
C305
10n
C6
100n
123456789
1011121314151617181920
100n
10%50V
SMARC Design Guide 2.0 Page 40 of 119 Mar 23, 2017 ©SGeT e.V.
ESD clamping diodes D159, D160 and D161 protect the Module from external ESD events and should be placed near the HDMI connector. The pin-out of the ESD clamp diodes allows for a trace to run under the chip connector to two pins. HDMI uses I2C signaling for the DDC. Resistors R1319 and R1322 provide the necessary pull-up. The FET U35 provides the Hot Plug Detect signal The Carrier provides 5V power to the HDMI connector. A series diode (D72) should be used to prevent back feeding of power in the event that the monitor is powered up when the Carrier is powered down. The HDMI Hot Plug Detect signal is buffered by two FETs U32 and U33 which prevent back feeding of power from the display to the Module as well as level translation to 3.3V levels. Note: The reference schematics assumes that the Module’s DDI ports are dual-source capable – dual source indicates that the Module can output DisplayPort or HDMI/DVI based on the DDC_AUX_SEL signal.
Figure 18 HDMI over DP++
3.4 Embedded DisplayPort (eDP)
The reference schematic provides a generic eDP interface. The eDP connector used in the design is an example only. Other connectors can be used based on the design requirements. JP83 selects 3.3 or 5V for the panel power. R1125 ensures that panel power is disabled when the Module is powering up and before the signal is actively driven. The panel control signals eDP_BKLT_EN, eDP_BKLT_CTRL as well as eDP_HPD are 3.3V level signals, check your panel specifications for correct voltage levels and provide translation if necessary. The reference design supports individual backlight control signals. It should be noted that some panels handle these functions over the AUX channel. The traces from JP83 and associated FETs to the eDP connector carry power to the panel. The traces should be routed with appropriate thickness to handle the current expected. eDP_TX and eDP_AUX differential pairs should be routed as high speed differential pairs. The panel control signals are low speed and do not require any additional care.
use wide traces with minimum 2 VIAs to GND-planePlace ESD-protection diodes close to connector
NOTE44
D159
TVS_RCLAMP0524P
6
7
9
10
8
5
4
2
1
3
D160
TVS_RCLAMP0524P
6
7
9
10
8
5
4
2
1
3
D161
TVS_RCLAMP0524P
6
7
9
10
8
5
4
2
1
3
GND_HDMI
R1322
R1319
V_5V0
R1
%1
K5
0S
02
R1
32
3
R1
%1
K5
0S
02
R1
32
4
DN
IR
13
25
R1
%1
K5
0S
02
DN
IR
1%
1K
50
S0
2R
13
26
R1
%1
K5
0S
02
R1
32
7D
NI
R1
%1
K5
0S
02
DN
IR
13
28
DN
IR
1%
1K
50
S0
2R
13
30
V_3V3
C1
0U
S0
5V
6C
10
68
C1
00
N0
2V
16
C1
06
9
FB
17
6L
CB
14
0R
03
PF
US
E0
_4
A
F1
5
V_5V0
C1
08
2C
47
PS
02
C1
08
3C
47
PS
02
LCB140R03FB177
FB178LCB140R03
V_3V3
FB179LCB140R03
C1
07
0C
10
0N
02
V1
6
C1071C100N02V16
C1072C100N02V16
C1073C100N02V16
C1074C100N02V16
C1
00
N0
2V
16
C1
07
5
C1076C100N02V16
C100N02V16C1077
R1
31
8
GND_HDMI
V_3V3
DNI
R1316
C100N02V16C1078
C1
00
N0
2V
16
C1
07
9
C1
08
0C
10
0N
02
V1
6
U364
CH7318C
2
11
15
21
26
33
40
32
3
25
7
10
45
41
42
38
39
44
49
12
23
22
20
19
18
17
16
29
28
14
13
24
5
1
35
6
4
43
27
34
30
37
46
36
8
9
47
48
31GND6
IN_D4+
IN_D4-
SCL
SDA
GND7
VCC8
GND8
HPD_SINK
CCT1
GND11
GND9
HPDEN
REXT
CCT2
GND1
GND2
GND5
OUT_D4+
OUT_D4-
SCL_SINK
SDA_SINK
OUT_D3+
OUT_D3-
GND4
OUT_D2+
OUT_D2-
OUT_D1+
OUT_D1-
GND3
GND10
IN_D3-
IN_D1+
IN_D1-
IN_D2+
IN_D2-
IN_D3+
NC
HPD
OE#
TRIM
DDC_EN
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
C1081C100N02V16
STP10
R1
%1
K2
1S
02
R1
33
2
R1
33
3
R1
%2
0K
0S
02
J118
J_TH_HDMI
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1TMDS_DAT2+
SHLD_D2
TMDS_DAT2-
TMDS_DAT1+
SHLD_D1
TMDS_DAT1-
TMDS_DAT0+
SHLD_D0
TMDS_DAT0-
TMDS_CLK+
SHLD_CLK
TMDS_CLK-
CEC
Reserved
SCL
SDA
GND_DDC
VCC5
HPD
MH1
MH2
MH3
MH4
BO1
SHIELD_GND
DN
IR
13
65
R1
%1
K5
0S
02
DN
IR
13
66
R1
%1
K5
0S
02
R1331
DP0_AUX+
DP0_HPD3_3
DP0_LANE1_C_+
DP0_LANE0_C_-
DP0_LANE0_C_+
DP0_LANE0-
DP0_HDMI_LS_REXT
DP0_HDMI_LS_OE#
DP0_HPD_LS
V_
5V
0_
S0
_H
DM
ICO
N_
F
V_3V3_S0_HDMI
DP0_LANE3-
DP0_LANE3+
DP0_LANE2-
DP0_LANE2+
DP0_LANE1-
DP0_LANE1+
DP0_LANE0+
DP0_AUX-
DP0_LANE1_C_-
DP0_LANE2_C_+
DP0_LANE2_C_-
DP0_LANE3_C_+
DP0_LANE3_C_-
DP0_LANE1_EXT_-
DP0_LANE1_EXT_-
DP0_LANE1_EXT_-
DP0_LANE1_EXT_+
DP0_LANE1_EXT_+
DP0_LANE1_EXT_+
DP0_LANE0_EXT_-
DP0_LANE0_EXT_-
DP0_LANE0_EXT_-
DP0_LANE0_EXT_+
DP0_LANE0_EXT_+
DP0_LANE0_EXT_+
DP0_LANE3_EXT_-
DP0_LANE3_EXT_-
DP0_LANE3_EXT_-
DP0_LANE3_EXT_+
DP0_LANE3_EXT_+
DP0_LANE3_EXT_+
DP0_LANE2_EXT_-
DP0_LANE2_EXT_-
DP0_LANE2_EXT_-
DP0_LANE2_EXT_+
DP0_LANE2_EXT_+
DP0_LANE2_EXT_+
V_5V0_S0_HDMICON
V_5V0_S0_HDMICON
V_5V0_S0_HDMICON
DP0_HPD_EXT
DP0_HPD_EXT
DP0_CTRLDAT_C
DP0_CTRLDAT_C
DP0_CTRLCLK_C
DP0_CTRLCLK_C
DP0_CTRLCLK_EXT
DP0_CTRLCLK_EXT
DP0_CTRLCLK_EXT
DP0_CTRLDAT_EXT
DP0_CTRLDAT_EXT
DP0_CTRLDAT_EXT
DP0_HDMI_LS_PC0
DP0_HDMI_LS_PC0
DP0_HDMI_LS_PC1
DP0_HDMI_LS_PC1
DP0_HDMI_LS_TEST0
DP0_HDMI_LS_TEST0
DP0_HDMI_LS_TEST1
DP0_HDMI_LS_TEST1
DP0_HPD_EXT
DP0_HDMI_LS_I2C_EN
DP0_HDMI_LS_I2C_EN
FOR TEST PURPOSE ONLY
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
D72MBR130LSFT1
R1321MOD
DP0_AUX_SEL
R1%100KS02
R1%2K21S02
R1%2K21S02
R1%0R0S02
R1
%0
R0
S0
2
R1%4K7S02
V_1V8
DP0_HPD
BSS138DW-7F
2
6
U35
1
5
43
V_1V8
DP0_HPD3_3
MOD
MOD
MOD
SMARC Design Guide 2.0 Page 41 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 19 Embedded DisplayPort (eDP)
3.5 MIPI DSI
The LVDS signal lines may alternatively be used to support up to two MIPI DSI (Display Serial Interface) displays. DSI is a high-speed differential bus and includes one clock lane and up to four data lanes. There is no AC coupling required. VDD and Backlight signals are the same is in LVDS mode. It is recommended to check with your SMARC Module vendor if MIPI DSI is supported by the used SMARC Module.
Figure 20 MIPI DSI
SM
AR
C M
OD
UL
E
DSI_D1+
DSI_D1-
DSI_CLK+
DSI_CLK-
DSI_TE
MIP
I D
SI D
isp
lay
DSI_D0+
DSI_D0-
DSI_D1+
DSI_D1-
DSI_CLK+
DSI_CLK-
DSI_TE
DSI_D0+
DSI_D0-
DSI_D3+
DSI_D3-
DSI_D2+
DSI_D2-
DSI_D3+
DSI_D3-
DSI_D2+
DSI_D2-
eDP_HPDeDP_HPD
eDP_TX0+_CeDP_TX0-_C
eDP_TX1+_CeDP_TX1-_C
eDP_TX2+_CeDP_TX2-_C
eDP_TX3+_CeDP_TX3-_C
V12_S0_eDP_PWR
V5/V3.3_S0_eDP_PWR
eDP_BKLT_ENeDP_BL_PWM
V12_S0_eDP_PWR
V5/V3.3_S0_eDP_PWR
VCC_5V0
VCC_3V3
eDP_TX0+eDP_TX0-
eDP_TX1+eDP_TX1-
eDP_TX2+eDP_TX2-
eDP_TX3+eDP_TX3-
eDP_AUX+
eDP_AUX-
LCD0_BKLT_ENLCD0_BKLT_PWM
LCD0_VDD_EN MOD
C421 C100N03X7R
C898
C1US03V6
C885
C100N03X7R
R1123R1%200K03
eDPJ212
JEDP_40
RSVD_1
1
H_GND_2
2
Lane3_N
3
Lane3_P
4
H_GND_5
5
Lane2_N
6
Lane2_P
7
Lane1_N
9
H_GND_8
8
Lane1_P
10
H_GND_11
11
Lane0_N
12
Lane0_P
13
H_GND_14
14
AUX_CH_P
15
AUX_CH_N
16
H_GND_17
17
LCD_VCC_18
18
LCD_VCC_19
19
LCD_VCC_2020LCD_VCC_21
21
LCD_Self_Test(NC)
22
LCD_GND_23
23
RSVD_40
40
BL_PWR_39
39
BL_PWR_38
38
BL_PWR_37
37
BL_PWR_36
36
RSVD_35
35
RSVD_34
34
BL_PWM_DIM(NC)
33
BL_ENABLE(NC)
32
BL_GND_31
31
BL_GND_30
30
BL_GND_29
29
BL_GND_28
28
HPD
27
LCD_GND_26
26
LCD_GND_25
25
LCD_GND_24
24
M141M242
M343
M444
C886
C100N03X7R
C418 C100N03X7R
C887
C639 C100N03X7R
R1124
R1%10K03
C889C100N03X7R
C419 C100N03X7R
C422 C10US06V25
C888
R1125
R1%10K03
C630 C100N03X7R
C890
C100N03X7R
C423 C100N03X7R
C420 C10US05V16
C891
Q69BS138
C637 C100N03X7R
JP83JMPRM254RED_LF
Q68A
QIRF7329
1
2
87
J104XST1X3S
Q68B
QIRF7329
3
4
56
C892C100N03X7R
MOD
MOD
VCC_12V
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
eDP_AUX-_CeDP_AUX+_C
C882
C100N03X7R
MOD
C883
SHLDGND
MOD
MOD
SMARC Design Guide 2.0 Page 42 of 119 Mar 23, 2017 ©SGeT e.V.
4 LOW / MEDIUM SPEED SERIAL I/O INTERFACES
4.1 Asynchronous Serial Ports
4.1.1 RS232 Ports
The SMARC Module asynchronous serial ports run at 1.8V logic levels. The transmit and receive data lines from and to the Module are active high, and the handshake lines are active low, per industry convention. If the asynchronous ports are to interface with RS232 level devices, then a Carrier RS-232 transceiver is required. The logic side of the transceiver must be able to run at 1.8V levels. The selection of 1.8V compatible transceivers is a bit limited, although more are appearing with time. Two such devices are the Texas Instruments TRS3253E, and the Maxim MAX13235E, illustrated in the figures below. The TI part is more cost effective, but has a top speed of 1 Mbps. The MAX 13235E can operate at maximum speeds over 3 Mbps (but your SMARC Module may or may not - check with your Module vendor). The transceivers invert the polarity of the incoming and outgoing data and handshake lines.
Figure 21 Asynchronous Serial Port Transceiver – RS232 – TRS3253E
Pin 6 of U35 (INVALID#) may be connected to a GPIO of the SMARC Module (GPIO10 in this example) but it has to be checked if this GPIO is not needed for another function.
4.7KOhm
0402 R12
21
V_1V8
QFN32
TI TRS3253EIRSMU35
33
26
6
17
18
19
20
21
22
23
25
3
30
15
27
8
32
24
16
28
9
10
11
12
13
14
7
5
4
2
1
31
29C1+
C1-
C2+
C2-
DIN1
DIN2
DIN3
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
FORCEON
FORCEOFF#
NC_16
NC_24
NC_32
NC_8
VCC
VL
V+
V-
DOUT1
DOUT2
DOUT3
RIN1
RIN2
RIN3
RIN4
RIN5
INVALID#
GND
TPAD
MOD
C92
25V100nF
2
1
R167
0OhmDNI
040221
100nFC93
25V2
1
V_5V0
C254330nF
1 2
1KOhmR48
0402
21
V_1V8
330nF C252
1 2C253330nF
1
2
MOD
47nF16V
C25921
V_1V8
DNI4.7KOhmR10
0402
21
5/1/1x5/1.0
JST SM05B-SRSS-TBJ39
SMT
7 6
5
4
3
2
11
2
3
4
5
M1
M2
SMT
J40
5/1/1x5/1.0
JST SM05B-SRSS-TB
7 6
5
4
3
2
11
2
3
4
5
M1
M2
MOD
MOD
MOD
MOD
MOD
GPIO10
SER1_RX
SER0_TX
SER0_RX
SER1_TX
SER0_1_INVALID#
SER0_SER1_XCVR_OFF#
TRS3253E_V-_1
TRS3253E_V+_1
FORCEON_1
TRS3253E_C2-_1
TRS3253E_C2+_1
TRS3253E_C1-_1
TRS3253E_C1+_1
SER1_TXD_RS232
SER1_RXD_RS232
SER0_TXD_RS232
SER0_RXD_RS232
SER0_RTS_RS232#
SER0_CTS_RS232#
SER0_RTS#
SER0_CTS#
5 Pin, 1mm Pitch, R/A, SMT
5 Pin, 1mm Pitch, R/A, SMT
SMARC Design Guide 2.0 Page 43 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 22 Asynchronous Serial Port Transceiver – RS232 – MAX13235E
4.1.2 RS485 Half-Duplex
A half-duplex RS485 asynchronous serial port implementation is shown below. This hardware implementation is suitable for multi-drop RS485 networks. The Maxim MAX13451E transceiver accepts 1.8V logic I/O and has other, flexible features of interest such as internal termination options. Multi-drop RS485 nodes should be strung together in daisy chain fashion using shielded twisted pair cable with a defined differential impedance (usually 120 ohms; sometimes 100 ohm cables are used). The two end-points of the system should be resistively terminated across the pair. The termination value should equal the differential impedance of the twisted pair cable used. The Maxim transceiver allows the termination to be enabled or disabled on the TERM# pin, and can be selected to be 100 ohms or 120 ohms via the TERM100 pin state. These pins can be controlled by Carrier GPIOs if desired. The RS485 driver is enabled when the SMARC SER2_RTS# signal is asserted low (if the resistor options in front of the XOR gate are loaded as shown, such that the XOR gate inverts the SER2_RTS2# signal for the RS485_DE2 function). A suitable, likely application specific, software driver is required to make the multi-drop RS485 network work.
U70
TSSOP20
18
9
16
8
17
7
3
11
19
1
20
14
10
15
12
13
6
5
4
2C1+
C1-
C2+
C2-
T1IN
T2IN
R1OUT
R2OUT
FORCEON
FORCEOFF
READY
VCC
VL
V+
V-
T1OUT
T2OUT
R1IN
R2IN
GND
MAX13235E
J60
7 6
5
4
3
2
11
2
3
4
5
M1
M2
SM05B-SRSS-TB
TP5
R460
DNI0402
4.7KOhm
21
V_1V8
1KOhm
0402 R461
21
V_1V8
C4631uF16V
2
1
C461330nF
060316V
2
1
C462
47nF
16V2
1
V_5V0
MOD
MOD
16V0603
330nFC465
2
1C464330nF
060316V
2
1
C460
47nF
16V2
1
MOD
MOD
SER2_RX
SER2_TX
SER2_FORCEOFF
READY_SER2
SER2_RX_RS232
SER2_RX_RS232SER2_TX_RS232SER2_TX_RS232
FORCEON_SER2
SER2_CTS_RS232
SER2_CTS_RS232
SER2_RTS_RS232SER2_RTS_RS232
SER2_CTS
SER2_RTS
SMARC Design Guide 2.0 Page 44 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 23 Asynchronous Serial Port Transceiver - RS485 – Half Duplex
MOD
MOD
JST SM06B-SRSS-TB
1x6-1.0RA
J61
8
7
6
5
4
3
2
11
2
3
4
5
6
M1
M2
25V100nF
C467
2
1
R467
0402
10K
Ohm
21
0402
R468
10K
Ohm
21
0402
R463
DN
I10K
Ohm
21
10K
Ohm
0402
DN
I
R462
21
V_1V8
10K
Ohm
0402
R464
21
0402
10K
Ohm
R465
21
V_5V0 V_1V8
TP6
25V100nF
C466
2
1
2
1
7
3
Maxim MAX13451EAUD+
TSSOP14
U71
15
11
12
10
6
4
9
8
14
13
5
DI
RO
DE
RE
TERM
TERM100
SRL
INV
FAULT
VCC
VL
A
B
GND
T_PAD
MOD
V_1V8
U72
SC70-5
1015-2777
Fairchild NC7SZ86P5X
3
5
42
1
V_1V8
C468
25V100nF
2
1
10K
Ohm
0402
R466
21
3M 961204-6300
4/2x2/2.54ST
J62
4
2
3
11
3
2
4
R471
0402
100Ohm
21
10KOhm0402 R472
21
R469
0402
10K
Ohm
DN
I
21
SER2_RX
SER2_TX
SER2_RTS
TERM_2
RS485_SER2_N
RS485_SER2_P
FAULT_2
TERM100_2
INV_2
SRL_2
RS485_RE2
RS485_RE2
RS485_DE2
RS485_DE2
Jumper
Open
01-02 03-04Jumper
RS485 receiver disabled
Closed
OpenOpen Closed
OpenInvalidClosedClosedRS485 receiver enbled when transmitter disabledRS485 receiver always enabled
State
SMARC Design Guide 2.0 Page 45 of 119 Mar 23, 2017 ©SGeT e.V.
4.2 I2C Interfaces
4.2.1 General
The I2C bus is a versatile low bandwidth multi-drop bus originally defined by Philips (now NXP). It is a two wire bus (clock and data) that relies on the use of open-drain drivers and passive pull-ups. The bus can be single master or multi-master. SMARC Modules are always I2C masters. Whether or not they allow other masters is Module implementation dependent. Most SMARC systems use the I2C bus as a way for the SMARC I2C Masters to interface to a variety of I2C Slave peripherals. The standard I2C interface operation speeds are 100 kHz and 400 kHz. Some implementations allow faster speeds.
4.2.2 I2C Level Translation, Isolation and Buffering
FETs may be used to perform I2C level translation, as shown in this figure. This arrangement provides no buffering. It can provide isolation to prevent one side of the bus dragging down the other if one of the rails is collapsed. The rail that is to collapse should be the rail driving the FET gates.
Figure 24 I2C Power Domain Isolation – using FETs
Q31
35
4
DiodesInc BSS138DW-7-F
Q31
62
1
Q32
35
4
DiodesInc BSS138DW-7-F
Q32
62
1
V_3V3
10K
Ohm
0402
R4
73
21
R4
74
0402
10K
Ohm
21
MOD
V_1V8
V_1V8
MOD
I2C_GP_DAT I2C_GP_DAT_3V3
I2C_GP_SCL_3V3I2C_GP_SCL
SMARC Design Guide 2.0 Page 46 of 119 Mar 23, 2017 ©SGeT e.V.
The circuit shown just below can provide power domain isolation, voltage level shifting and I2C bus buffering. The Fairchild FXMA2102 power rails VCCA and VCCB can be at the same voltage level or at different levels, over a range of 1.65V to 5.5V. Either rail can come up before the other. If you have many I2C devices, it is a good idea to split them up into segments with up to about 6 devices on each segment, and isolate the segments with a bi-directional I2C buffer such as the FXMA2102. I2C bus performance degrades with too much capacitive loading.
Figure 25 I2C Power Domain Isolation and Buffer – Fairchild FXMA2102
MOD
Fairchild FXMA2102U29
MicroPak-8
8
7
6
45
3
2
1VCCA
A0
A1
OE GND
B1
B0
VCCB
100nFC68
25V2
1 C69
25V100nF
2
1
V_1V8
04020OhmR122 21
V_3V3
10K
Ohm
04
02
R186
21
R187
04
02
10K
Ohm
21
V_3V310K
Ohm
R188
0402
DN
I
2
1
DN
I10K
Ohm
R189
0402
2
1
V_1V8MOD
I 2C_GP_DAT
I 2C_GP_CK
I2C_IO_3V3_CK
I2C_IO_3V3_DAT
Level shifted I2C
SMARC Design Guide 2.0 Page 47 of 119 Mar 23, 2017 ©SGeT e.V.
4.2.3 I2C_PM Bus EEPROMs
The SMARC I2C_PM bus is special in that it is used on the Module for power management functions, and it always runs from a 1.8V rail on the Module. The 1.8V voltage rail requirement on the I2C_PM bus allows it to be powered from a simple, low quiescent current linear or buck switching regulator from V_MOD_IN. On the Module, since it is used for power management, it is “on” even when the Carrier power may be off (i.e. the CARRIER_PW_ON signal may be low, and Carrier circuits that are not involved in power management are powered off). If the I2C_PM bus is used on the Carrier for functions that are not power management functions, then it needs to be isolated from the Module by a set of back to back FETs, as shown in the following figure. The V_1V8 in the figure is a Carrier board power rail that may be collapsed; the Module side of the I2C_PM must not be dragged down.
Figure 26 I2C_PM EEPROM: Carrier Power Domain
V_1V8
V_1V8
V_1V8
R309
0402
10K
Ohm
21
R310
0402
10K
Ohm
DN
I
21
R311
10K
Ohm
0402
DN
I
21
10K
Ohm
0402
R312
21
R313
0402
10K
Ohm
21
C267100nF25V 2
1
R314
0402
10KOhm
21
DN
I
R315
10K
Ohm
0402
21
U42
TSSOP8
Atmel AT24C32D
8
7
6
5
43
2
1A0
A1
A2 GND
SDA
SCL
WP
VCC
MOD
MOD
Q17
35
4
Q18
35
4
10K
Ohm
0402
R316
21
10K
Ohm
0402
R317
21
Q18
DiodesInc BSS138DW-7-F
62
1
Q17
DiodesInc BSS138DW-7-F
62
1
V_1V8
V_1V8
I2C_PM_DAT
I2C_PM_CK
PWR_BOARD_ID_A2
PWR_BOARD_ID_A1
PWR_BOARD_ID_A0
WP_PWR
I2C_PM_CAR_SDA
I2C_PM_CAR_SCL
I2C_PM EEPROM
(7-bit format)
I2C Address : 0x57
SMARC Design Guide 2.0 Page 48 of 119 Mar 23, 2017 ©SGeT e.V.
The SMARC I2C_PM bus may be used on the Carrier for power management functions, such as interfacing to a battery charger or battery fuel gauge. In this case, the power circuits and the I2C_PM interface to the SMARC Module need to be powered whenever power is on.
A local low quiescent current low drop out linear regulator is needed to provide 1.8V for the Carrier board “Module domain” devices.
Figure 27 I2C_PM EEPROM: Module Power Domain
The SMARC Module specification recommends - but does not require - that Carriers have a parameter EEPROM on the I2C_PM bus, preferably configured as shown here, in the “Module Power Domain”. This, in principle, allows the Module to query the Carrier I2C_PM EEPROM before asserting the CARRIER_PWR_ON signal that enables the main Carrier board power feed.
V_MOD_IN Maxim MAX1818
SOT23
U39
4
1
2
5
6
3SHDN#
OUT
SET
POK
IN
GND
1uF25V
2
1
C274
04020Ohm
R295
2 1 22.6KOhm0402 R319
21
R3180402
100KOhm
2 14.7uF10V
C272
2
1
51.1KOhm0402
R320
21
MOD
MOD
Atmel AT24C32D
U41
TSSOP8
8
7
6
5
43
2
1A0
A1
A2 GND
SDA
SCL
WP
VCC
DN
I
R302
10K
Ohm
0402
21
R303
0402
10KOhm
21
C266100nF25V 2
1
R304
0402
10K
Ohm
21
10K
Ohm
0402
R305
21
R306
10K
Ohm
0402
DN
I
21
R307
0402
10K
Ohm
DN
I
21
R308
0402
10K
Ohm
21
I2C_PM_DAT
I2C_PM_CK
1V8_LDO_SET
PWR_BOARD_ID_A2
PWR_BOARD_ID_A1
PWR_BOARD_ID_A0
WP_PWR
V_1V8_LDO
(7-bit format)
I2C Address : 0x57
I2C_PM EEPROM
SMARC Design Guide 2.0 Page 49 of 119 Mar 23, 2017 ©SGeT e.V.
4.2.4 General I2C Bus EEPROMs
The other SMARC I2C buses (I2C_LCD, I2C_GP, I2C_CAM) operate at 1.8V. The power domain isolations described in the previous section do not apply. A simple sample EEPROM circuit is shown for reference.
Figure 28 I2C_GP EEPROM
R220
10K
Ohm
DN
I
0402
21
0402
R2
21
10
KO
hm
DN
I
21
10
KO
hm
R222
0402
21
10
KO
hm
0402
R223
21
V_1V8
0402
10K
Ohm
R224
21
C101
25V100nF
2
1
0402
10KOhmR225
21
V_1V8
R226
10K
Ohm
0402
DN
I
21
MOD
MOD
Atmel AT24H C02U10
SOIC8
8
7
6
5
43
2
1A0
A1
A2 GND
SDA
SCL
WP
VCCI2C_GP_DAT
I2C_GP_CK
GEN_BOAR D_ID_A2
GEN_BOAR D_ID_A1
GEN_BOAR D_ID_A0
WP_GENERIC
(7-bit form at)
I2C Address : 0x56
SMARC Design Guide 2.0 Page 50 of 119 Mar 23, 2017 ©SGeT e.V.
4.2.5 I2C Based I/O Expanders
I2C based “I/O Expanders” are available from Texas Instruments, NXP and others. Multiple expanders may be put onto the same I2C bus by configuring the I/O expander I2C address straps. These devices are an easy and cost effective way to realize additional I/O on SMARC systems. On the device shown in the figure, the I/O ports on the right are all in a high impedance “tri-state” mode when the device powers up. This allows the designer to tie the I/O lines through resistor pull-ups or pull-downs to define a power up state for these lines, before the I2C interface and before software are active. Wider (x16) devices are also available.
Figure 29 I2C Device: I/O Expander
V_1V8
0402
21
R205
10K
Ohm
10K
Ohm
0402
R206
21
10K
Ohm
R207
0402
21
10K
Ohm
DN
I
R208
0402
21
R209
DN
I
0402
10K
Ohm
21
10K
Ohm
0402
R210
DN
I
21
V_1V8
C75100nF25V 2
1
MOD
TI TCA9554
U34
TSSOP16
13
12
11
10
8
14
15
3
2
1
16VCC
A0
A1
A2
SDA
SCL
GND
P0
P1
P2
P3
P4
P5
P6
P7
INT#
MODI2C_GP_DAT
I2C_GP_CK
IO_EXP_6
GP_EXP1_ID_A2
GP_EXP1_ID_A1
GP_EXP1_ID_A0
IO_EXP_0
IO_EXP_1
IO_EXP_2
IO_EXP_3
IO_EXP_4
IO_EXP_5
IO_EXP_7
(7-bit format)I2C Address : 0x20
4
9
7
6
5
SMARC Design Guide 2.0 Page 51 of 119 Mar 23, 2017 ©SGeT e.V.
4.2.6 Other I2C Devices
There is a very wide variety of I2C peripherals available on the market. Since SMARC Modules offer up to four I2C buses (not counting the HDMI private I2C bus), it is easy to incorporate I2C devices into a SMARC system. A few schematic examples are given here, and further suggestions are listed in the table at the end of this section.
Figure 30 I2C Device: Accelerometer
Figure 31 I2C Device: Accelerometer and Magnetometer
DN
I
0402
10K
Ohm
R194
21
V_1V8
MOD
MOD
DN
I
0402
10K
Ohm
R195
21
V_1V8R
196
10K
Ohm
0402
21
V_1V8V_1V8
0402
10K
Ohm
R197
21
MOD
MOD
DN
I
R198
10K
Ohm
0402
21
16V10uF
C221
2
1
R140 04020Ohm21
0Ohm0402R141 DNI21
R142 04020Ohm DNI21
MOD
MOD
0Ohm0402R143 21
V_3V3
25V100nF
C72
2
1
V_1V8
25V100nFC73
2
1
V_3V3
DNIR144
0Ohm21
R145
0Ohm21
DNI
STMicro LIS302DL
U32
LGA14
15
11
3
10
12
7
14
13
9
8
5
4
2
6
1 VDD_IO
VDD
GND_2
GND_4
GND_5
INT1
INT2
SDA/SDI/SDO
SCL/SPC
CS
SDO
GND_10
RSRVD_3
RSRVD_11
THRM_PAD
I2C_GP_DAT
I2C_GP_CK
I2C_LCD_DAT
I2C_LCD_CK
GPIO11
GPIO10LIS302DL_INT1
LIS302DL_INT2
ACCL_I2C_SEL
ACCL_I2C_ADD
ACCL_I2C_SDA
ACCL_I2C_SCL
(7-bit format)
I2C Address : 0x1C
MOD
MOD
MOD
MOD
STMicro LSM303DLHC
U30
LGA14
13
12
9
5
4
3
2
7
11
10
8
6
1
14VDD
VDD_IO
C1
RSVD_8
RSVD_10
RSVD_11
GND
SCL
SDA
INT2
INT1
DRDY
SETP
SETC
R131 04020Ohm21
R132 04020Ohm21
04020OhmR133 DNI21
DNIR134 0Ohm0402
21
220nF16V
C251
2
1
10V
C2004.7uF
2
1C70
25V100nF
2
1
V_3V3
10uFC220
16V2
1
100nFC71
25V2
1V_1V8
DNI R1370Ohm0402
2 1
R1380OhmDNI0402
2 1
DNI R13904020Ohm 2 1
GND
I2C_GP_DAT
I2C_GP_CK
I2C_CAM_DAT
I2C_CAM_CK
GPIO11
GPIO10
INT2
INT1
DRDY
I2C_ACC_CK
I2C_ACC_DAT
(7-bit format)
I2C Address : 0X19 (Accel)
I2C Address : 0X1E (Magnet)
SMARC Design Guide 2.0 Page 52 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 32 I2C Device: Gyroscope
The table below gives a small sampling of other 1.8V I/O I2C devices that are available. The list is meant to just give the reader an idea of what types of devices are available.
Table 3 I2C Device Examples - 1.8V I/O
Function Device Description Vendor Vendor P/N
ADC 8-channel, 12-bit SAR ADC with temperature sensor
Analog Devices AD7291
DAC Quad, 16-bit DAC Analog Devices AD5696R
LED driver 7-bit LED driver with intensity control
Texas Instruments TCA6507
Proximity / Button sensor
Four Channels, Capacitive Proximity/Button Solution
Semtech SX9500
Temperature Sensor
Temperature Monitor, ±1° C On Semiconductor NCT72
UART 128 Word FIFOs Maxim Integrated MAX3108
MOD
MOD
MOD
MODSTMicro L3G4200D
U31
LGA16
14
7
6
5
4
3
2
13
12
11
10
9
8
15
16
1VDD_IO
VDD
RSVD_15
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
GND
SCL/SPC
SDA/SDI/SDO
SDO/SA0
CS
DRDY/INT2
INT1
PLLFILT
C21910uF16V
2
1
04020OhmR127 DNI21
DNIR128 0Ohm0402
21
0Ohm0402
R129 21
0Ohm0402R130 21
V_3V3V_1V8
R19
0 04
02
10K
Ohm
2
1
10K
Ohm
04
02R191
DN
I
2
1
16V10nFC212
2
1
C250
25V470nF
2
1
0402R192
10K
Ohm
2
1
04
02
R19
3
10K
Ohm
2
1
0Ohm
0402R135
DNI
21
0Ohm
0402R136
DNI
21
100nF16V
C209
2
1 C210100nF16V
2
1
V_1V8
MOD
MOD
I2C_GP_DAT
I2C_GP_CK
I2C_CAM_DAT
I2C_CAM_CK
GPIO11
GPIO10
I2C_GYRO_CK
I2C_GYRO_DAT
SDO/SAO
DATA_READY
INT1_GYRO
I2C Address : 0X69
(7-bit format)
SMARC Design Guide 2.0 Page 53 of 119 Mar 23, 2017 ©SGeT e.V.
4.3 Touch Screen Controller Interfaces
4.3.1 General
The two most popular touch technologies used with SMARC systems are summarized in the following table.
Table 4 Popular Touch Technologies
Technology Notes
Resistive
Low cost; rugged. Display clarity and contrast may be compromised by the resistive touch overlay. Usually used with a stylus but may be used with bare fingers. Multi-touch is possible but not common. More straightforward to implement than capacitive touch.
Projected Capacitive
Higher cost, higher barrier to entry and better quality and user experience than resistive touch. Multi-touch capable. Excellent optics.
There are many other touch technologies, some better suited to certain situations such as user’s wearing gloves and so on. An overview may be found on the EloTouch website: www.elotouch.com under “Touchscreens”.
4.3.2 Interface Types / Driver Considerations
Various host interface types are used by touch screen controllers. A given controller may implement one or more of the following interfaces: USB client, I2C, asynchronous serial port, I2S, SPI, or other interface. USB interfaces for touch screen controllers are attractive as there is the potential that the software effort is minimal: the touch screen controller may act as a USB HID (Human Interface Device) class device, and the operating system at hand may be able to understand the generic touch HID implementation directly. However, for more advanced touch implementations, such as multi-touch (the ability to track and decipher multiple, simultaneous touch hits on a screen), a more specialized driver is usually necessary. The driver is often touch controller vendor specific. Additionally, a touch controller vendor may offer multiple hardware interfaces, but the driver may be optimized for one particular hardware interface. The conclusion is: check out the software driver situation before going down a particular hardware path.
4.3.3 Touch Controller Modules / ICs / Screens
Table 5 Touch Controller Module / IC / Screen Vendors
Vendor Notes Web Link
Atmel Key vendor of touch screen controller ICs for projected capacitive screens. Atmel is a silicon vendor, and generally will not help directly with touch screen integration issues, unless your company is a Tier 1 company. Atmel has a network of partners that they will steer you to for help with integration issues. Some of the partners from Atmel’s list are included in this list.
www.atmel.com
Data Modul Selection of touch screen panels, overlays and www.data-modul.com
SMARC Design Guide 2.0 Page 54 of 119 Mar 23, 2017 ©SGeT e.V.
controller modules for projective capacitive technology and for resistive touch screens. Company is based in Germany and has a presence in the USA. Products are marketed under the “Easy Touch” trade mark.
EloTouch Elo offers a variety of finished touch panels. They also offer a popular controller chip for resistive touch panels, under the marketing name “AccuTouch COACh V Controller Chip”.
www.elotouch.com
Pixcir Vendor of controller ICs for projected capacitive screens. Based in China and in Switzerland.
www.pixcir.com
Precision Design Associates
Touch modules and touch overlay screens. Based in Marietta, Georgia, USA.
www.pdaatl.com
Touch International
Touch overlays, modules and integration services. One of the larger and better known companies in this field. Based in the state Texas, USA. The Touch International website has an overview of various touch technologies.
www.touchinternational.com
MSC Technologies
Vendor of its own product group of Touch Screen Panels, Overlays and Controller Cards for PCAP (Projected Capacitive) Touch Technology; also offers other touch technologies, TFT panels and display systems. MSC has its own sales presence in Central Europe and is marketed by Avnet / Avnet Embedded in all other countries of the world.
www.msc-technologies.eu
Also check with your SMARC Module vendor or your SMARC Carrier design partner – some of them have in-house solutions for particular display panels. Also remember to consider the availability of software drivers for the choices that you are making.
SMARC Design Guide 2.0 Page 55 of 119 Mar 23, 2017 ©SGeT e.V.
4.3.4 I2C Interface to Touch Controller
Atmel is a popular choice for projected capacitance touch controllers. Atmel supplies USB and I2C drivers for the mXT1664S touch screen controller. Multi-touch is supported in the I2C driver but not, as of this writing apparently, in the USB driver. The circuit shown below provides buffering and level translation for a SMARC interface to an I2C interfaced touch controller board. The Atmel mXT1664S can be configured for 1.8V I2C operation, and hence this voltage translation may not be necessary in a custom design. However, off-the-shelf touch controller modules may not be configured for 1.8V I/O (and the particular touch module behind this example was not). In any case, some buffering when cabling to an external board is not a bad thing to have, for robustness.
Figure 33 Touch Screen Connector – I2C Interface
MOD
DNI0Ohm0402
21 R475
R47604020Ohm 21
V_3V3
10K
Ohm
0402
R486
21
V_1V8
C470100nF25V
2
1
100nF25V
C473
2
1
MOD
MOD
C472100nF25V
2
1 C475100nF
25V2
1
100nF25V
C476
2
1
2
1 C477100nF25V
C471100nF25V
2
1
100nF25V
C474
2
1
V_1V8
MOD
MOD
10K
Ohm
0402
R488
21
R489
0402
10K
Ohm
21
V_3V3
0Ohm0402R485 21
R47904020Ohm
21
R48004020Ohm
21
R48204020OhmDNI
21
R48104020OhmDNI
21
TI SN74AVC1T45U73
SOT553
2
4
6
5
3
1VCCA
A
DIR
VCCB
B
GND
0402
R483
10K
Ohm
21
Fairchild FXMA2102U75
MicroPak-8
8
7
6
45
3
2
1VCCA
A0
A1
OE GND
B1
B0
VCCB
V_1V8
R484
0402
10K
Ohm
21
R487
0402
10K
Ohm
21
V_3V3
TI SN74AVC1T45U74
SOT553
2
4
6
5
3
1VCCA
A
DIR
VCCB
B
GND0402 R4780Ohm 21
R477DNI0Ohm0402
21
MOD
V_5V0V_3V3
Molex 53261-1071
J63
SMT10/1/1x10/1.25
12
11
10
9
8
7
6
5
4
3
2
11
2
3
4
5
6
7
8
9
10
SH1
SH2
MOD
MODI2C_CAM_DAT
I2C_CAM_CK
I2C_LCD_DAT
I2C_LCD_CK
GPIO10
RESET_OUT#
GPIO1/CAM1_PWR#
GPIO6/TACHIN RESET_1V8
TS_GPIO_1V8
TS_RST
I2C_TS_DAT
I2C_TS_CK
TS_GPIO
SMARC Design Guide 2.0 Page 56 of 119 Mar 23, 2017 ©SGeT e.V.
4.4 I2S Interfaces
4.4.1 General Information
The I2S (Inter IC Sound) bus specification was initially released in 1986 by Philips (NXP) and later revised in 1996. I2S is a synchronous serial bus used for interfacing digital audio devices such as Audio CODECs and DSP chips. Generally PCM audio data is transmitted over the I2S interface. The I2S bus may have a single bidirectional data line or two separate data lines. The signals constituting the I2S bus are a serial clock/ bit clock (output from the master), a left right clock (output from the master) that indicates the channel being transmitted and a single bidirectional data line or two data lines - one input and one output. A SMARC Module can generally be configured as I2S master or slave. SMARC Modules may support up to three independent I2S interfaces each having separate input and output data lines.
4.4.2 Cirrus Logic I2S Audio Example
An example of an I2S based audio circuit using the Cirrus Logic WM8904 CODEC is given below. The circuit uses a SMARC I2S interface for the audio PCM data, and a SMARC I2C interface to allow a path for software setup of registers within the CODEC.
Figure 34 I2S Audio Codec Cirrus Logic WM8904
GND_AUDIO GND_AUDIO
LIN
E_O
UT
_R
IGH
T_R
C
LIN
E_O
UT
T_LE
FT
_R
C
LINE_OUT_RIGHT_I2S
LINE_OUT_LEFT_I2S
GND_AUDIO
V_1V8_S0_I2S_CODEC
I2S0_CK
GND
V_1V8_S0_I2S_CODEC
MAX 5.86 mA
GND_AUDIO
MAX 4,41 mA
MAX 1,05 mA
V_1V8_S0_I2S_CODEC
GND
MAX 0.76 mA
GND
Y1
3
4
2
1EN
GND
V_VCC
OUT
OSC
12MHz 50ppm
DNI
ZNL9
Place Charge pump caps as close as posibe to Codec
CPVOUTP_I2S
ZOBEL NETWORKs
(reduce high frequency switching noise from charge pump)
I2C_WM8904_DAT
I2C_WM8904_CK
I2C Address: 0x1A
(7-bit format)
I2C_GP_CK
I2C_GP_DAT
GND_AUDIO
V_MICBIAS_I2S
V_3V3_MIC
V_3V3_S0
CODEK_OPTION_SW_I2S_HDA#
V_3V3_MIC
ZNL16
Place Both Microphone decoupling caps as close as posible to codec WM8904VMIDC_I2S
V_3V3_MIC
V_1V8_S0
V_1V8_S0_I2S_CODEC
V_1V8_S0_I2S_CODEC
MIC_LEFT_I2S
MIC_RIGHT_I2S
LINE_IN_LEFT_I2S
LINE_IN_RIGHT_I2S
GND_AUDIO GND_AUDIO
HE
AD
PH
ON
E_O
UT
_R
IGH
T_R
C
HE
AD
PH
ON
E_O
UT
T_LE
FT
_R
C
HEADPHONE_OUT_RIGHT_I2S
HEADPHONE_OUT_LEFT_I2S
ZOBEL NETWORKs
(reduce high frequency switching noise from charge pump)
ZNL17
Place ZOBEL Network as close as possible to codec
U60
33
22
10
8
17
14
15
13
3
19
21
12
11
20
4
6
9
5
16
31
32
30
29
28
2
25
1
27
23
7
18
26
24IN2R
IN2L
LINEOUTR
CPVDD
AVDD
IN1L/DMIC_DAT1
IRQ/GPIO1
IN1R/DMIC_DAT2
SCLK
MCLK
BCLK/GPIO4
LRCLK
DACDAT
ADCDAT
LINEOUTL
DGND
CPGND
V_DCVDD
V_DBVDD
MICBIAS
CPVOUTP
CPVOUTN
VMIDC
V_MICVDD
SDA
HPOUTL
HPOUTR
HPOUTFB
LINEOUTFB
CPCA
CPCB
AGND
GND_PAD
WM8904
V_3V3_MIC_FB
ZNL18
Place Microphone decoupling cap and FB as close as posible to codec WM8904
MAX 0.01 mA
HEADPHONE_GND_AUDIO_FB
CPCA_I2S
CPCB_I2S
CPVOUTN_I2S
LINE_OUT_GND_AUDIO_FB
I2S0_LRCK
V_1V8_S0_I2S_CODEC
NCNC_GPIO1_I2S
GND GND
GND
V_1V8_S0_I2S_CODEC
GND_AUDIO
V_1V8_S0_I2S_CPVDD
V_1V8_S0_I2S_AVDD
GND
GND GND
GND_AUDIO
AUDIO_MCK
AUDIO_MCK_RAUDIO_MCK_OSC
AUDIO_MCK_R
ZNL38
Place R295 and R315 with shared pad with minimum stub
V_VOUT_8
V_VOUT_7
CT
GND
V_VIN_1
V_VIN_2
V_VBIAS
ON
THMPAD_9
GND GND
GND
8
7
6
5
1
2
4
3
9
TPS22965
U58
V_VOUT_8
V_VOUT_7
CT
GND
V_VIN_1
V_VIN_2
V_VBIAS
ON
THMPAD_9
U57
TPS22965
9
3
4
2
1
5
6
7
8
GND GND
GND
GND
GND
GND
GND
V_3V3_S0
FB906032A
120
FB1106032A
120
FB2706032A
120
GND
C345
1u
16V
0402
0402
50V
C15
100n
0402
50V
C16
100n
040216V2u2 C200
0402
50V
C18
100n
0402
50V
C19
100n
0402
50V
C62
100n
DN
I
100n
C197
50V
0402
040210V4u7 C296
100k
0402
DN
I
R192
1%
DN
I
R195
1%
100k
0402
0402
1%
20R
R174
100n
C235
50V
0402
R175
1%
20R
0402
100n
C63
50V
0402
0402
50V
C241
100n
0402
50V
C64
100n
100n
C246
50V
0402
C1894u710V 0402
DNI0R1% 0402
R295
R31504021%
0R
0402
16V
1u
C183
C2944u710V 0402
040210V4u7 C295
0402
50V
1n
C272
040
250V
C264
100n
C281
1n
50V
0402
100n
C267
50V
0402
C185
1u
16V
0402
0402
16V
1u
C192
DNI04021%
0R R39
DNI04021%
0R R40
0402
20R
1%
R135
0402
1%
20R
R129
0402
C239
10u
6V
30402
6V
3
C240
10u
04021%0R R49
R540R 1% 0402
22
MOD
MOD
MODI2S0_SDOUT
I2S0_SDINMOD
MOD
MOD
MOD
SMARC Design Guide 2.0 Page 57 of 119 Mar 23, 2017 ©SGeT e.V.
4.4.3 Texas Instruments TLV320AIC3105 I2S Audio Example
An alternative I2S audio CODEC example from TI is shown below. As in the WM8904 example, the I2S carries the PCM audio from and to the SMARC Module, and the I2C is used for chip setup parameters.
Figure 35 I2S Audio CODEC: Texas Instruments
Figure 36 Audio Amplifier: Texas Instruments
MOD
MOD
04020Ohm R6521
J7
CUI SJ-43516
RASMT6/1/3.5mm
6
5
4
3
2
1 1
2
3
4
5
6
QFN4
Abracon ASEMB-12.000MHZ
Y2
34
21STBY GND
VDD OUT
QFN32
TI TLV320AIC3105
J8
33
26
17
21
6
30
29
28
27
23
22
19
20
32
7
24
18
25
15
16
14
13
12
11
10
31
8
9
1
3
2
4
5DOUT
DIN
BCLK
WCLK
MCLK
SDA
SCL
RESET#
MIC1L/LINE1L
MIC1R/LINE1R
MIC2L/LINE2L
MIC2R/LINE2R
MIC3L/LINE3L/MICDET
MIC3R/LINE3R
MICBIAS
AVDD
DRVDD_18
DRVDD_24
IOVDD
DVDD
HPLCOM
HPLOUT
HPRCOM
HPROUT
LEFT_LOP
LEFT_LOM
RIGHT_LOP
RIGHT_LOM
DVSS
DRVSS
AVSS1
AVSS2
T_PAD
C208 100nF21
0402 R660Ohm 2 1
0Ohm0402
DNI
R672 1
V_1V8
DNI
10nF16V
C213
2
1
V_3V3_AUD
GND_AUDIO_1
470nFC17821
470nFC17921
2KOhmR265
04
02
21
V_1V8
GND_AUDIO_1
Semtech RCLAMP0504P
D5
6
4
3
1
7
2
5 V
NC
TAB
D1
D2
D3
D4
R68 04020Ohm DNI21
0OhmR69 040221
470nFC18021
C181 470nF21
C4100nF
25V2
1
1uF16V
C143
2
1
V_1V8
V_1V8
16V
C1441uF
2
1
GND_AUDIO_1
0Ohm R70040221
C5100nF
25V2
1
100nFC6
25V2
1
16V1uF
C145
2
1 C1461uF16V
2
1C7
25V100nF
2
1
V_3V3
1uF16V
C147
2
1
100nFC8
25V2
1
0OhmR71 040221
FB2
1.2A
120Ohm90mOhm
2 1
GND_AUDIO_1
10uFC218
16V2
1
GND_AUDIO_1
DNI0402
0OhmR7221
JST SM03B-SRSS-TB
J9
SMT3/1/1x3/1.0
5 4
3
2
11
2
3
M1
M2
GND_AUDIO_1
R7304020Ohm 21
0Ohm R74040221
04020Ohm R75DNI 21
DNI0402 R760Ohm 21
MOD
MOD
MOD
JST SM03B-SRSS-TB
SMT3/1/1x3/1.0
J10
5 4
3
2
11
2
3
M1
M2
GND_AUDIO_1
MOD
MOD
MOD
DNI R7704020Ohm 2 1
0402 R780OhmDNI 2 1
0402DNI 0Ohm R792 1
0Ohm R80DNI0402
2 1
0402 R810Ohm 2 1
R8204020Ohm 2 1
0402 R830Ohm 2 1
04020Ohm R842 1
DNI R8504020Ohm 2 1
0Ohm R86DNI0402
2 1
0402 R87DNI 0Ohm 2 1
0402 R88DNI 0Ohm 2 1
MOD
MOD
MOD
MOD
MOD
MOD0Ohm
0402DNI R8921
GND_AUDIO_1
C214
16V10uF
2
1
MOD
MOD
MOD
MOD
MOD
I2C_GP_DAT
I2C_GP_CK
I2C_CAM_DAT
I2C_CAM_CK
I2S2_CK
I2S2_SDIN
I2S2_SDOUT
I2S2_LRCK
I2S1_CK
I2S0_CK
I2S0_LRCK
I2S0_SDOUT
I2S1_SDIN
I2S0_SDIN
I2S1_SDOUT
I2S1_LRCK
AUDIO_MCLK
HP_RIGHT
HP_RIGHT
I2C_CODEC_CK
I2C_CODEC_CK
I2C_CODEC_DAT
I2C_CODEC_DAT
HP_MIC
HP_MIC
HP_LEFT
HP_LEFT
LEFT_LOP
RIGHT_LOP
HP_COM
HP_COM
CAR_RESET_OUT#
CODEC_RESET#
HP_MIC_C
JACK1_R
AUDIO_MCLK_R
AUDIO_MCLK_ROSC_OUT
MICBIAS_CODEC
MIC1L
MIC1R
MIC2L
MIC2R
LINE_2_IN_RIGHT
LINE_2_IN_RIGHT
LINE_2_IN_LEFT
LINE_2_IN_LEFT
LINE_1_IN_RIGHT
LINE_1_IN_RIGHT
LINE_1_IN_LEFT
LINE_1_IN_LEFT
LEFT_LOM
RIGHT_LOM
JACK4_R
I2S_SDOUT
I2S_SDOUT
I2S_LRCK
I2S_LRCK
I2S_CK
I2S_CK
I2S_SDIN
I2S_SDIN
AUDIO_RESET#
I2C Addr :0x58
(7 bit Address)
MOD
MOD
C2281nF
2
1
1nFC229
2
1
GND_AUDIO_1
16V
C215
10uF
2
1
GND_AUDIO_1
21
1.2A90mOhm
FB3
GND_AUDIO_1
R90 04020Ohm21
V_5V0
C148
1uF
16V2
1 C9
100nF25V
2
1
100nF
C10
25V2
1
GND_AUDIO_1
C149
1uF
16V2
1C11
25V100nF
2
1
GND_AUDIO_1
1uF
C150
16V2
1
1uFC151 21
GND_AUDIO_1
1KOhm
0402
DNI
R46
21
1uFC152 21
GND_AUDIO_1
50mOhm1.7A
L121
50mOhm1.7A
L221
1.7A
L3
50mOhm
21
1.7A
L4
50mOhm
21
0OhmR91 DNI0402
21
DNI0Ohm0402R92 21
0Ohm0402R93 21
JST SM02B-SRSS-TB
1x2-1.0SMT
J15
4 3
2
11
2
M1
M2
SMT1x2-1.0
JST SM02B-SRSS-TB
J16
4 3
2
11
2
M1
M2
GND_AUDIO_1
GND_AUDIO_1
0Ohm0402R94 21
1nFC230
2
1C2311nF
2
1
R471KOhm
DNI 0402
21
1uFC153 21
C154 1uF21
TI TPA2016D2
QFN20
U21
21
8
3
20
16
7
6
9
10
12
11
19
17
18
14
15
2
1
5
4
13AVDD
PVDDL_4
PVDDL_5
INL+
INL-
INR+
INR-
SDZ
SCL
SDA
PVDDR_11
PVDDR_12
OUTR+
OUTR-
OUTL+
OUTL-
NC_16
NC_20
AGND
PGND
TH_GND
MOD
MOD
I2C_GP_DAT
I2C_GP_CK
I2C_CAM_DAT
I2C_CAM_CK
LEFT_LOP
RIGHT_LOP
LEFT_LOM
RIGHT_LOM
I2C_AMP_CK
INR+
INL+
INR-
INL-
I2C_AMP_DAT
OUTR_P
OUTR_N
OUTL_P
OUTL_N
OUTR_N_F
OUTR_P_F
OUTL_P_F
OUTL_N_F
SMARC Design Guide 2.0 Page 58 of 119 Mar 23, 2017 ©SGeT e.V.
4.4.4 lntel High Definition Audio over I2S2
The HDA interface uses the same pins as I2S2 in SMARC 2.0 specification. At the time of writing HDA is still the preferred Audio Interface for x86 based Modules, even though I2S is getting integrated in the latest x86 SoC generations. There's a minor conflict with regards to voltage levels of the shared HDA and I2S audio interfaces. SMARC defines the I/O levels of HDA to be 1.5V to comply with the HDA specification. Nevertheless, there's a trend to run the HDA interface at 1.8V in order to save cost for additional voltage regulators. Most of chip vendors as well as codec vendors allow either voltage to be used. Please check with your Module vendor if 1.5V or 1.8V are supported and use an audio codec that is capable to support the regarding I/O voltage. The example schematic shows a simple resistor option (R126 and R127) to support both I/O levels within one design. HDA_SDI signal should have a damping resistor close to the audio codec. It's a good practice to also reserve space for series damping resistors at the other HDA interface lines. Depending on Carrier board implementation it might be useful to also apply series resistors there to improve EMI and signal integrity.
Figure 37 HD Audio
DNI
10V
10V
Line Out
Headphone Out
16V16V
(amplified)
DNI
10V 10V
Line In
10V
10V
DNI
10V
Microphone
10V
10V
10V
16V
16V 16V
10V
10V
10V 10V
10V
16V 16V
16V
10V
DNI
HDA_HP_R
HDA_HP_L
HDA_VBIAS
HDA_FLY_C
HDA_FLY+
HDA_FLY-
HDA_VHP+HDA_VHP-
HDA_SENSEA
HDA_LINE_L
HDA_LINE_R
HP_JD MIC_JD
LINE_OUT1_JD
LINE_OUT1_JD
HP_JD
HDA_SYNC
HDA_SDOHDA_SDI_R
HDA_RST#
HDA_CLK
HDA_SDI
HDA_VCOM
HDA_VREF+
HDA_MIC_L
HDA_MIC_R
HDA_MICBIAS
HDA_LINEIN_C
LINE_IN_JD
HDA_LINEIN_L
HDA_LINEIN_R
MIC_JD
LINE_IN_JD
HDA_CLK_RHDA_SYNC_R
HDA_SDO_RHDA_RST#_R
V_HDA
V_3V3
AGND_HDA
V_3V3_FILT
AGND_HDA
V_HDAV_1V8
V_1V5
AGND_HDA AGND_HDAAGND_HDA
AGND_HDA
AGND_HDAAGND_HDA AGND_HDA
AGND_HDA
AGND_HDA
AGND_HDA
AGND_HDAAGND_HDA
AGND_HDA
AGND_HDA
AGND_HDA
V_3V3
AGND_HDA
V_3V3_FILT
MOD
MOD
MOD
MOD
MOD 0402R128 33Ohm
0402R132 560Ohm
FB1
1.2A 90mOhm
0402R153 0Ohm
C1441.0uF
0402R150 100Ohm
0402
R134
20kOhm
0402R155 0Ohm
C1432.7nF
0402
R1450Ohm
C13518pF
C137100nF
C153100nF
C1482.7nF
X3
XAUDJACK_2503AP_6P_BC
3
54
16
2
0402
R148100kOhm
C154100nF
0402
R130
47kOhm
C150100nF
0402
R137
33Ohm
C1342.7nF
C11710uF
C1472.7nF
C1421.0uF
C151100nF
0402 R140
15kOhm
0402R143 100Ohm
C1451.0uF
C149100nF
0402R139
15kOhmC139100p
C138100p
X2
XAUDJACK_2503AP_6P_LC
3
54
16
2
0402R146 100Ohm
0603
R126R5%0R0S03
0402
R151
10kOhm
0402R154 0Ohm
C155100nF
0402
R138
33Ohm
0402
R142100kOhm
C1192.2uF
0402R152 0Ohm
X4
XAUDJACK_2503AP_6P_PC
3
54
16
2
0402R149 100Ohm
0402
R133
5.1kOhm
0402
R136
2.67kOhmC1251.0uF
C13010uF
U20
CS4207-CNZ
VL_IF1
GPIO0/DMIC-SDA12
VL_HD3
DMIC_SCL4
SDO5
BITCLK6
DG
ND
7
SDI8
VD9
SYNC10
RESET#11
GPIO1/DMIC_SDA212
VA_REF24
LINEIN_R+23
LINEIN_C-22
LINEIN_L+21
MICIN_R-20MICIN_R+19
MICIN_L+18MICIN_L-17
MIC_BIAS16
GPIO315 GPIO214
SENSE_A13
LINEOUT_R1+36
LINEOUT_L1+35
LINEOUT_L1-34
LINEOUT_R2-33LINEOUT_R2+32
LINEOUT_L2+31
LINEOUT_L2-30
VBIAS29
VCOM28
VREF+27
AGND26
VA25
LINEOUT_R1-37
HPOUT_L38
HPREF39
HPOUT_R40
VHP_FILT-41
FLYN42
FLYC43
VHP_FILT+44
FLYP45
VA_HP46
SPDIF_IN47
SPDIF_OUT148
EP
49
C11410uF
C1324.7uF
X1
XAUDJACK_2503AP_6P_LC
3
54
16
2
C11810uF
C1222.2uF
C1332.7nF
C1314.7uF
C136100nF
M1MDSP_02
0402
R147100kOhmC129
1.0uF
C1401.0uF
C1412.7nF
C15210uF
0402R131 560Ohm
C1461.0uF
0603
R127R5%0R0S03
0402
R129
47kOhm
0402
R13539.2kOhm
0402
R141100kOhm
0402R144 100Ohm
SMARC Design Guide 2.0 Page 59 of 119 Mar 23, 2017 ©SGeT e.V.
4.4.6 Audio Switch
The following schematic shows an audio switch. This can be used on baseboards which have both codecs I2S and HD Audio to switch between the two of them.
Figure 38 Audio switch
4.5 SPI Interfaces
4.5.1 General
The SPI (Serial Peripheral Interface) is a full duplex synchronous bus supporting a single master and multiple slave devices. The SPI bus consists of a serial clock line (generated by the master); data output line from the master; a data input line to the master and one or more active low chip select signals (output from the master). Clock frequencies from 1-100MHz may be generated by the master depending on the maximum frequency supported by the components in the system. SMARC Modules running a 1.8V I/O interface are generally limited to about a 50 MHz clock rate on this interface. The SMARC Module will always be the SPI master. SMARC Modules may support a Carrier SPI Boot option.
4
5
3
2
1
V_V+
NC1
NC2
NC3
NC4
NO1
NO2
NO3
NO4
COM1
COM2
COM3
COM4
IN1-2
IN3-4
GND
P1
P2
4
5
3
2
1
J24
1054-2371
1
2
3
5
4
GND_AUDIO
LINE_IN_RIGHT_C
LINE_IN_LEFT_C
LINE_IN_JD
6
14
8
TS3A44159
U51
2
10
4
16
12
7
13
5
1
9
15
11
3
Adio Codec Multipexor HDA (default) / I2S Codec
Line In Jack 3.5 mm
Line Out Jack 3.5 mm
MAX 1.2 uA
GND_AUDIO
LINE_IN_LEFT_MUX
LINE_IN_RIGHT_MUX
LINE_IN_LEFT_HDA
LINE_IN_RIGHT_HDA
1
2
1044-8634
J31
CODEK_OPTION_SW_I2S_HDA#
LINE_IN_LEFT_I2S
LINE_IN_RIGHT_I2S
J43
1
2
3
5
4
GND_AUDIO
LINE_OUT_RIGHT_C
LINE_OUT_LEFT_C
LINE_OUT_LEFT_MUX
LINE_OUT_RIGHT_MUX
LINE_OUT_LEFT_HDA
LINE_OUT_RIGHT_HDA
LINE_OUT_LEFT_I2S
LINE_OUT_RIGHT_I2S
FB16600420mA 0402
0402420mA600 FB21
GND_AUDIO GND_AUDIO
LINE_IN_RIGHT
LINE_IN_LEFT
0402420mA600 FB22
FB24600420mA 0402
LINE_OUT_LEFT
LINE_OUT_RIGHT
GND_AUDIOGND_AUDIO
P1 P2
P3 P4
P5 P6
P7 P8
P9 P10
1 2
43
5
7
6
8
109
J10
Front panel Analog Header
MIC_LEFT
MIC_RIGHT
V_V+
NC1
NC2
NC3
NC4
NO1
NO2
NO3
NO4
COM1
COM2
COM3
COM4
IN1-2
IN3-4
GND
3
11
15
9
1
5
13
7
12
16
4
10
2
U52
TS3A44159
8
14
6
GND_AUDIOGND_AUDIO
MIC_RIGHT_HDA
MIC_LEFT_HDA
MIC_RIGHT_I2S
MIC_LEFT_I2S
U20
2
3 4
51V_IN V_OUT
NR/FBEN
GND
TPS73101
GND_AUDIO GND_AUDIO GND_AUDIO GND_AUDIOGND_AUDIO
RA
RB
GND_AUDIO
Vout = 1,204 * (RA+RB)/RB = 4.28 V
V_4V3_AUDIO
V_5V0_S0
V_5V0_S0_AUDIO
FB_V_4V3_AUDIO
V_4V3_AUDIO
V_4V3_AUDIO
V_4V3_AUDIO
MAX 1.2 uA
J31 CODEC
OPEN HDA
SHORTED I2S
V_MICBIASV_MICBIAS_HDA
V_MICBIAS_I2S
MAX 43 uA
MAX 43 uA
V_1V8_S0
0402420mA600 FB14
MIC_LEFT_MUX
FB15600420mA 0402
MIC_RIGHT_MUX
D44Y
2
1
3
Q8
BSS138W
SOT323
CODEK_OPTION_SW_I2S_HDA#
YD45
HDA CODECI2S CODEC
GND
LED_I2S_CODEC#
V_3V3_S5_LED
JUMPER
H3
V_V+
NC1
NC2
NC3
NC4
NO1
NO2
NO3
NO4
COM1
COM2
COM3
COM4
IN1-2
IN3-4
GND
3
11
15
9
1
5
13
7
12
16
4
10
2
U19
TS3A44159
8
14
6
GND_AUDIOGND_AUDIO
V_4V3_AUDIO
MAX 1.2 uA
GND_AUDIO
GND_AUDIO
HDA / I2S Audio codec LEDs indicationLINE_OUT_JD
GND_AUDIO
FPAH_PRESENCE#
V_1V8_S0
HEADPHONE_OUT_RIGHT_I2S
HEADPHONE_OUT_LEFT_I2S
HEADPHONE_OUT_LEFT_HDA
HEADPHONE_OUT_RIGHT_HDA
GND_AUDIO
Port D of HDA codec
Port C of HDA codec
Port B of HDA codec
MIC_JD
HEADPHONES_JD
JACK DETECT SIGNALS FOR I2S CODEC (Connected to 4x GPI of I2C Expander)
SignalJACK Function
LINE IN LINE_IN_JDPlug
Voltage Log
Unplug 0 0
5V 1
LINE OUT LINE_OUT_JDPlug
Unplug 0 0
5V 1
MIC (*) MIC_JDPlug
Unplug 0 0
5V 1
HEADPHONES (*) HEADPHONES_JDPlug
Unplug
0 0
5V 1
(*) These two JACKs are available via Front Panal Audio Header and plugged Intel HD Audio Front panel dongle
AUDIO_JACK_SENSE#
AUDIO_JACK_SENSE#
HEADPHONE_GND_AUDIO_FB
audio signals, to reduce noise
Route HEADPHONE_GND_AUDIO_FB close to HEADPHONE
ZNL19
MIC_RIGHT_HDA_C
MIC_RIGHT_I2S_C
MIC_LEFT_HDA_C
MIC_LEFT_I2S_C
GND_AUDIO
GND_AUDIO
AUDIO_JACK_SENSE#
To HDA kodek
FB47600420mA 0402
0402420mA600 FB48
HEADPHONE_OUT_RIGHT
HEADPHONE_OUT_LEFTHEADPHONE_OUT_RIGHT_MUX
HEADPHONE_OUT_LEFT_MUX
Port A of HDA codec
LINE_OUT_GND_AUDIO_FB
audio signals, to reduce noise
Route LINE_OUT_GND_AUDIO_FB close to LINE OUT
ZNL22
SENSE_A_HDA
V_5V0_S0
To I2S kodek
U13
4
5
6
1
3
2V_V+
GND
IN
NO
COM
NC
TS5A4624
GND_AUDIO
V_5V0_S0
GND_AUDIO
CODEK_OPTION_SW_I2S_HDA#
GND_AUDIO
V_5V0_S0
CODEK_OPTION_SW_I2S#_HDA_5V0
AUDIO_JACK_SENSE_I2SSOT323
BSS138W
Q6
2
1
3
GND
GND
LED_HDA_CODEC#
CO
DE
K_O
PT
ION
_S
W_I2
S#_H
DA
_3V
3
4
5
3
SOT363
BSS138DW
Q2
1
2
6
SOT363
BSS138DW
Q2
R204
2k2
1%
0402
C358 100u10VB
1%
100R
0402
R317
R193
1%
100k
0402
50V
0402
C139
100n
B 10V100uC359
04021%0R R114
0402
50V
C23
100n
100n
C148
0402
50V
R173
68k1
1%
0402
R179
26k7
1%
0402
04021%0R R55
C56 100u10VB
B 10V100uC57
040216V1u C307
040216V1u C308
C3091u 16V 0402
R169
1%
100k
04
02
R131
10k
1%
0402
R205
2k2
1%
0402
0402
50V
C135
100n
0402
50V
C137
100n
0402
50V
C181
100n 1
00k
1%
R170
04021u
C225
16V
0402
R215
39k2
1%
0402
R216
5k11 1%
0402040216V1u C223
C2161u16V 0402
1u C217040216V
0402
100k
1%
R128
C231
100p
50V
0402
C234
100p
50V
0402
GND_AUDIO GND_AUDIO
C282
100p
50V
0402
C284
100p
50V
0402
NC
GND_AUDIO
GND_AUDIO
GND_AUDIO
0402
50V
10n
C268
0402
6V
3
10u
C270
0402
6V
3
10u
C269
0402
6V
3
10u
C271
0402
16V
1u
C297
0402
16V
1u
C298
FB2806032A
120
04
02
1%
750R
R212
04
02
1%
750R
R213
R214
20k
1%
0402
21
SMARC Design Guide 2.0 Page 60 of 119 Mar 23, 2017 ©SGeT e.V.
4.5.2 SMARC Implementation
Each SPI device requires a chip select, a clock, a data in line and a data out line. The device I/O level must of course be compatible with the SMARC Module I/O level. The Winbond W25Q64FW is an example of a 1.8V I/O compatible SPI Flash device. The figure below illustrates a socket implementation for a SPI Flash memory.
Figure 39 SPI Flash Socket
8-1.27
Lotes_ACA-SPI-004-T01
SMT
J33
8
7
6
5
4
3
2
11
2
3
4
5
6
7
8
100nF25V
C64
2
1
MOD
MOD
04
02
10KOhm
R179
DNI
21
R180
0402
10KOhm
21
V_1V8
0402
10KOhm
R181
21
MOD
MOD
DNI
R182
04
02
10KOhm
21
SPI0_DO
SPI0_DIN SPI0_CK
SPI0_WP# SPI0_HOLD
SPI0_CS0#
SMARC Design Guide 2.0 Page 61 of 119 Mar 23, 2017 ©SGeT e.V.
4.5.3 SPI Device Examples – 1.8V I/O
The table below shows a small sample of the devices available on the market with a 1.8V SPI interface. It is only a sample and is meant to give an idea of the type of devices available. Remember to check the software driver situation before settling on a particular device.
Table 6 SPI Device Examples - 1.8V I/O
Function Device Description Vendor Vendor P/N
ADC 8-channel, 12-bit SAR ADC with temperature sensor
Analog Devices AD7298
DAC Quad, 16-bit nano DAC Analog Devices AD5686R
Flash Memory 64 Mbit SPI Flash memory Winbond W25Q64FW
IO Expander 8-bit GPIO expander with integrated level shifters
Exar XRA1404
Temperature Sensor
Digital thermometer ±2 °C resolution Range - 55°C to +120 °C
Maxim Integrated DS1722
Touch Screen Controller
4 wire resistive touch screen controller
Texas Instruments TSC2008-Q1
UART bridge UART with 128 Word FIFOs and support for 9-bit multi-drop mode data filtering
Maxim Integrated MAX3108
SMARC Design Guide 2.0 Page 62 of 119 Mar 23, 2017 ©SGeT e.V.
4.6 CAN Bus
4.6.1 General
The CAN (“Controller Area Network”) bus is a differential half duplex data bus used in automotive and industrial settings. A CAN bus uses shielded or unshielded twisted differential pair wiring, terminated in the pair differential impedance of 120 ohms at the endpoints of the bus. Nodes on the bus are arranged in daisy-chain fashion, although stubs of up to 0.3 meters are allowed at each node. The standard allows data rates of up to 1 Mbps, with a maximum bus length of 40 meters at that rate. Various slower rates are defined, along with longer and longer bus lengths allowed as the data rates go down. A bus rate of 250 kbps is in common use in automotive situations. With CAN FD also faster baud rates are possible. The two lines in a CAN twisted pair are referred to as CAN_H and CAN_L (for CAN High and CAN Low). There are two bus states on the CAN physical layer: the Dominant state and the Recessive state. In the Dominant state, CAN_L is pulled to GND through an open drain driver and CAN_H is pulled to the CAN Vcc through an open drain driver. In the Recessive state, CAN_L and CAN_H are not actively driven and they are pulled to a voltage of (Vcc / 2) by passive components. Hence the CAN bus is essentially a differential open-drain bus. On the system logic side of a CAN transceiver, the CAN Dominant state is a logic low and the Recessive state a logic high. The CAN protocol has features important to a real time environment:
Nodes are prioritized: CAN nodes are assigned an 11 bit identifier o The lower the ID number, the higher priority
Latency time is guaranteed
Data packets are limited to 8 bytes maximum o Higher level protocols take care of handling large data sets
The bus has Multi-master capability
There are error detection and signaling features
The CAN bus base standard is defined by ISO 11898-1:2003, available for a fee from the ISO (www.iso.org). There are some very helpful CAN application notes from Texas Instruments (a vendor of CAN MAC and transceiver devices) available for free. These include “Introduction to the Controller Area Network (CAN)”, TI document number SLOA101A, and “Controller Area Network Physical Layer Requirements”, document number SLLA270. The original CAN bus protocol definition by Bosch is also freely available on the web (CAN Specification, Version 2.0 © 1991 Robert Bosch GmbH). Various connectors are used in CAN bus implementations. The use of DB-9 connectors is fairly common. The TI application note (SLLA270) referenced above has pin-out information for a couple of common CAN connector implementations.
SMARC Design Guide 2.0 Page 63 of 119 Mar 23, 2017 ©SGeT e.V.
4.6.2 SMARC Implementation
The SMARC specification allows for up to two logic level CAN ports. The ports run at the Module I/O voltage (typically 1.8V) and consist of an asynchronous CAN TX line and an RX line from and to the SMARC Module CAN protocol controller. A Carrier based CAN transceiver is required to create a SMARC system CAN implementation. CAN PHYs are available from Texas Instruments, On Semiconductor, NXP, Freescale, Microchip and numerous other vendors. The logic interface for CAN PHYs is typically suited for 3.3V logic I/O, so level translation is required if the SMARC Module is running 1.8V I/O. Precautions must be taken to prevent a CAN system from sending out frames or blocking a CAN-Bus unintentionally, for example during reset and power down. During power down, CAN Transceivers are designed to be HIGH-Z. During power up or reset, they must be put into a “listen only mode”. It is the responsibility of the application software to activate the CAN-transceiver after all initialization is done. A SMARC Carrier board CAN transceiver implementation is shown below. This example shows two 60 ohm terminations (or 120 ohms across the CAN pair). This is appropriate only if the node is an end-point, and intermediate nodes should not be terminated. The example transceiver TJA1051 has a “silent input pin”. If left open, the transceiver enters “listen only mode”. Using a GPIO allows the application software to set the can transceiver into “normal mode = able to send” by pulling “silent” low. A pull down resistor on the gate of T1 is necessary to disable the transceiver in case of a CPU reset or power fail. It is recommended to use GPIO8 as CAN0_EN and GPIO9 as CAN1_EN.
Figure 40 CAN Bus Implementation
4.6.3 Isolation
Some CAN transceiver application notes show optical isolation between the CAN protocol controller and the CAN transceiver. See, for example, NXP (Philips) application note AN96116 for the PCA82C250 CAN transceiver. They suggest using the 6N137 optical transceivers. Be careful to take into account the I/O levels and current sink / source requirements of the various devices in the chain.
CAN_HCAN_L
ConnectorCAN Ports
D1
PESD1CAN bi dual 50nA
32
1CAN_LCAN_H
R160.4R
X1A
CON DSUB-M/F 9pol UNC clip 90
A5A9A4A8A3A7A2A6A1
A10
A11
Level Shift
U2
74LV1T125
OE#1
+5
A2
-3
Y4
U3
74LV1T125
OE#1
+5
A2
-3
Y4
V_3V3
CAN_RX_3V3
V_1V8
C3
100nF 16V
12
V_3V3
CAN_TX_3V3C4
100nF 16V
12
V_1V8
U1
IC TJA1051/T3 SMT SO8_150 4.5-5.5
TXD1
GND2
VCC3
RXD4
VIO5
CANL6
CANH7
S8
R260.4R
C54n7
12
CAN_RX_3V3CAN_TX_3V3
C1100nF12
V_5V0C210uF12
V_3V3
C6
100nF 16V
12
R32.2k
12
T1BSS138
32
1
R44.7k
12
CANx_TX_M
CANx_RX_M
GPIO_x MOD
MOD
MOD
SMARC Design Guide 2.0 Page 64 of 119 Mar 23, 2017 ©SGeT e.V.
5 HIGH SPEED SERIAL I/O INTERFACES
5.1 USB
5.1.1 General
The USB (Universal Serial Bus) is a hot-pluggable general purpose high speed I/O standard for computer peripherals. The standard defines connector types, cabling, and communication protocols for interconnecting a wide variety of electronic devices. The USB 2.0 Specification defines data transfer rates as high as 480 Mbps (also known as High Speed USB). A USB host bus connector uses four pins: a power supply pin (5V), a differential pair (D+ and D- pins) and a ground pin. Additionally a fifth pin, USB ID (mostly used in devices supporting USB-OTG), may also be used which indicates whether the device operates in Host mode or a Client/Device mode. SMARC Modules support up to six independent USB 2.0 busses, designated USB0 to USB5. Of these, SMARC USB0 and USB3 can be configured as a host, client or OTG port. OTG operation is optional. SMARC USB1, USB2, USB4 and USB5 are always hosts. A USB host is usually the smarter device – a host computer for example. A USB client is usually a peripheral device, such as a camera, printer or mass storage device. USB clients are often based on microcontrollers that include USB client interface hardware. USB3.0 Super Speed is supported on USB2 and USB3 and defines data rates up to 5 Gbps. Therefore these ports have two additional differential signal pairs SSRX and SSTX. USB3 may also support a USB3.0 OTG port.
5.1.2 USB0 Client / Host Direct From Module
The figure below shows a USB-OTG implementation on the USB0 port terminated on a micro USB Type A/B connector The ESD diodes should be placed close to the connector, and the USB traces routed as differential pairs in “no stub” fashion – the traces should go through the pads of the ESD protection devices, without introducing a stub. If the client device is bus powered, the Carrier can supply 5V, 500mA power to the client device. The Module USB0_EN_OC# signal controls the power switch and current limiter, the Texas Instruments TPS2052, which in turn supplies power to a bus-powered client device. Per the USB specification, bus powered USB 2.0 devices are limited to a maximum of 500 mA. The TPS2052 limits the current and can stand an indefinite short circuit to GND. The current limiting is somewhat imprecise, and kicks in between 500 mA and 1A.
SMARC Design Guide 2.0 Page 65 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 41 USB0 Client / Host Direct From Module
040221
0Ohm
R291
MOD
MOD
UMT3 ROHM RJU003N03T106
Q7
3
1
2
Q8
UMT3 ROHM RJU003N03T106
3
1
2
USB_VBUS_OTG
V_3V3
0402
4.7KOhmR1
DNI
21
SO8
TI TPS2052B
U18
5
6
7
8
4
3
2
1GND
IN
EN1
EN2
OC1#
OUT1
OUT2
OC2#
Vishay SI2305CDS-T1-GE3
Q15
SOT233
2
1
10KOhm0402
R174
2 1
Vishay SI2305CDS-T1-GE3
Q16
SOT23
3 2
1
1MEGOhm
R262
0402
21
C1
25V100nF
2
1
4.7uFC191
10V2
1
MOD
FB1
1.2A90mOhm120Ohm
21
MOD
5/1/1x5/0.65RA
J6Molex 0475900001
S4
S3
S2
S1
5
4
3
2
15V
D-
D+
ID
GND
S1
S3
S2
S4
100nFC2
25V2
1
C3100nF25V2
1
V_5V0
VBUS_OTG_PWR
TI TPD2E009
SOT23
D1
3
12
190mOhm
TDK ACM2012-900-2P-T002FB7
2x1.2x1.2
1 4
32
MOD
MOD
USB0_VBUS_DET
USB0_DN
USB0_DP
CARRIER_PWR_ON
USB0_EN_OC#
VBUS_OTG_EN#
VUSB_OTG
OTG_PORT_N
OTG_PORT_P
USB0_OTG_ID
USB0_OC#
Type AB Micro USB, R/A, SMT
SMARC Design Guide 2.0 Page 66 of 119 Mar 23, 2017 ©SGeT e.V.
5.1.3 USB1 and USB2 Host Ports direct from Module
Carrier board implementation of USB host ports from SMARC USB1 and USB4 is straightforward. An implementation of a dual USB Type A Host port header is shown in the figure below. The ESD diodes should be placed close to the connector, and the USB traces routed as differential pairs in “no stub” fashion – the traces should go through the pads of the ESD protection devices, without introducing a stub. If the target USB devices are “down” on the Carrier, then much or all of this circuit may be omitted. The SMARC USB pairs are routed directly to the target device. The ferrite choke in the USB lines, the ESD diodes, and the TPS2052 power switch and associated passives may be eliminated. However, in some cases, it is desirable to have the capability to “power cycle” a USB peripheral under software control. If this is the case, it might be desirable to retain the TPS2052 power switch, or a similar device for 3.3V power switching, with the power control function performed by the USB1_EN_OC or USB4_EN_OC, as appropriate.
Figure 42 USB1 and USB4 Host Ports Direct From Module
MOD
21 0402R326
0Ohm
U44
SO8
TI TPS2052B
5
6
7
8
4
3
2
1GND
IN
EN1
EN2
OC1#
OUT1
OUT2
OC2#25V
C289100nF
2
1
50mOhm
1050-8120
L14
1.7A
21
V_5V0
16V47uFC292
2
1
C290
25V100nF
2
1
R323
0402
4.7KOhmDNI
21
V_3V3
0402R325
0Ohm
21
MOD
V_3V3
R324
0402
4.7KOhmDNI
21
C29347uF16V
2
11050-8120
50mOhm
21
1.7A
L15
100nFC291
25V2
1
THT
TE 5787617-1J48
2PORT
S4
S3
S2
S1
B4
B3
B2
B1
A4
A3
A2
A1VCCA
USBA_N
USBA_P
GNDA
VCCB
USBB_N
USBB_P
GNDB
S1
S2
S3
S4
FB11TDK ACM2012-900-2P-T002
190mOhm
1 4
32
190mOhm
TDK ACM2012-900-2P-T002FB12
1 4
32MOD
MOD
SOT23
D26
TI TPD2E009
3
12
TI TPD2E009
D27
SOT23 3
12
MOD
MOD
USB4_DN
USB4_DP
USB1_DN
USB1_DP
USB_VBUS_A4
USB_VBUS_A4
USB_VBUS_A4_FB
USB4_DP_CONN
USB4_DN_CONN
USB1_DN_CONN
USB1_DP_CONN
USB1_EN_OC
USB_VBUS_A1
USB_VBUS_A1
USB_VBUS_A1_FB
USB1_OC
USB2_OC
USB4_EN_OC
Dual Stacked, Type A USB, R/A, TH
SMARC Design Guide 2.0 Page 67 of 119 Mar 23, 2017 ©SGeT e.V.
5.1.4 USB 3.0
A USB 3.0 port consists of a USB 2.0 port and a set of unidirectional SuperSpeed signals. The following example shows an implementation of a stacked dual USB 3.0 connector that is utilizing USB2 and USB3 without using the optional OTG capabilities of USB3. Place the ESD diodes as close as possible to the connector. For SuperSpeed Signals, ESD diodes with optimized package and low I/O capacitance should be used to create only minimal impact on signal integrity. Also the common mode chokes should be selected carefully. Ensure that their differential mode cutoff frequency is well above the maximum frequency of 2.5 GHz of a USB3.0 signal. Each USB 3.0 port should be able to supply up to 900mA and should be decoupled with at least 120µF of low ESR capacitance.
Figure 43 USB 3.0 host dual
5.1.5 USB 3.0 OTG
USB3 may support OTG functionality, depending on Module’s capabilities. Check with your Module’s vendor manual whether USB3 supports OTG. Please note that dual role devices should have a VBUS capacitance that is in a range of 1.0µF to 6.5µF. The ESD diodes should be placed as close as possible to the connector. Take care that VBUS and ID pins are also protected against ESD events as they are directly connected to the SMARC 2.0 Module. The Module will control the power switch by driving USB3_EN_OC#. It will be driven low in order to cut-off power to VBUS as it is required for client mode.
IEC 61000-4-2, level 4 compliant
ESD protected by D3
16V
16V
16V
2.5A
2.5A
190mOhm2x1.2x1.2
190mOhm2x1.2x1.2
USB3_SSRX-_CONUSB3_SSRX+_CON
USB3_SSTX-_CONUSB3_SSTX+_CON
USB23_ILIM
USB3_SSRX-_CONUSB3_SSRX+_CON
USB3_SSTX-_CONUSB3_SSTX+_CON
USB2_SSTX-
USB2_SSTX+
USB2_SSRX-
USB2_SSRX+
USB2+
USB2-
USB3-
USB3+ VCC_USB3
VCC_USB3
USB3_OC#
V5_USB3_SW VCC_USB3
USB3_EN_OC#
USB2_EN_OC#V5_USB2_SW
USB2_OC#
USB3_SSTX-
USB3_SSTX+
USB3_SSRX-
USB3_SSRX+
USB2-_CON
USB2_SSRX-_CONUSB2_SSRX+_CON
USB2_SSTX-_CONUSB2_SSTX+_CONUSB2_SSTX+_CON
USB2_SSTX-_CON
USB2_SSRX+_CONUSB2_SSRX-_CON
USB2+_CON
USB3-_CONUSB3+_CON
VCC_USB2
VCC_USB2
V_5V0
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
D3
OnSemi NUP4114
1
2
3 4
5
6
FB9Murata DLP11TB800UL2L
1
4 3
2
X5
Molex 0484060003
P1_VCC1
P1_USB2.0_D-2
P1_USB2.0_D+3
P1_GND4
P2_VCC10
P2_USB2.0_D-11
P2_USB2.0_D+12
P2_GND13
H1H1
H2H2
H3H3
H4H4
P1_USB3_SSTX-8
P1_USB3_SSTX+9
P1_USB3_SSRX-5
P1_USB3_SSRX+6
P1_GND_DRAIN7
P2_USB3_SSRX-14
P2_USB3_SSRX+15
P2_GND_DRAIN16
P2_USB3_SSTX-17
P2_USB3_SSTX+18
FB4
40mOhm
FB8Murata DLP11TB800UL2L
1
4 3
2
C84.7uF
+ C9Panasonic 16SVP180MX
0402R153 0Ohm
FB6TDK ACM2012-900-2P-T002
1
4 3
2
C12100nF
0402
R15451kOhm FB5
40mOhm
FB3TDK ACM2012-900-2P-T002
1
4 3
2
D5
TI TPD4E02B04
12345 6
78910
0402R152 0Ohm
+ C11Panasonic 16SVP180MX
C10100nF
D6DCDS2C05GTA
D4
TI TPD4E02B04
12345 6
78910
FB10Murata DLP11TB800UL2L
1
4 3
2
U2
TI TPS2561DRC
GND1
IN2
IN3
EN14
EN25
FAULT2#6
ILIM7
OUT28
OUT19
FAULT1#10
PAD11
FB7Murata DLP11TB800UL2L
1
4 3
2
SMARC Design Guide 2.0 Page 68 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 44 USB 3.0 OTG
16V
2.5A
16V 16V
16V
USB3_EN_OC#
USB3_ILIM
V5_USB3_SW
USB3_OC#
USB3_VBUS
USB3_VBUS
CARRIER_PWR_ON
USB3_VBUS_DET
USB3-
USB3+
USB3_VBUS
USB3-_CONUSB3+_CONUSB3_OTGID
USB3_OTGID
USB3_SSTX-
USB3_SSTX+
USB3_SSRX-
USB3_SSRX+USB3_SSRX+_CONUSB3_SSRX-_CON
USB3_SSTX-_CON
USB3_SSRX-_CONUSB3_SSRX+_CON
USB3_SSTX-_CON
USB3_SSTX+_CONUSB3_SSTX+_CON
V_5V0
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
0402R157 0Ohm
FB11
40mOhmC1574.7uF
FB12FBD90R0A33S05D
1
4 3
2
0402
R1561MegOhm
FB13
FBD80R0A10S041
4 3
2
FB14
FBD80R0A10S041
4 3
2
X6
USB3_MICROAB
VBUS1
D-2
D+3
ID4
GND5
SSTX-6
SSTX+7
GND_D8
SSRX-9
SSRX+10 SHLD
11
SHLD12
T2Diodes DMN63D8LW 1
23
0402
R15551kOhm
D7
OnSemi NUP4114
1
2
3 4
5
6
U21
TI TPS2561DRC
GND1
IN2
IN3
EN14
EN25
FAULT2#6
ILIM7
OUT28
OUT19
FAULT1#10
PAD11
T1Alpha & Omega AO3413
1
2 3
D8
TI TPD4E02B04
12345 6
78910
C1564.7uF
C15910nF
C158100nF
SMARC Design Guide 2.0 Page 69 of 119 Mar 23, 2017 ©SGeT e.V.
5.1.6 USB Hub On Carrier
Additional USB ports may be implemented on a SMARC Carrier board using a USB hub to interface with one of the SMARC USB ports (usually USB1 or USB2, saving the SMARC USB0 for possible client or OTG use). The USB 2.0 compliant (and 480 Mbps capable) family of hubs from Microchip / SMSC (www.microchip.com or www.smsc.com) is recommended. Parts with two, three, four or seven downstream ports are available. A Carrier hub implementation example using the seven port SMSC USB2517i is shown in the two figures below. There are three configuration straps on this particular SMSC hub, designated CFG_SEL[2] through CFG_SEL[0]. The options need to be considered carefully. The example schematic has the 2:0 configuration straps set to binary 110, which, per the SMSC data sheet, sets the hub to the following:
SMSC hub defaults in effect
Other strap options disabled
Hub LED pins configured to indicate USB speed
Individual port power switching
Individual port over-current sensing
External EEPROM not used
External I2C interface not used Although the sample schematic shows the external EEPROM and I2C interfaces, they are not used. Note that the “DNI” designation on the schematic stands for “Do Not Install” – i.e. the part is not loaded, in this example. If implementing such a hub (or any piece of configurable silicon), it is wise to keep your options open and have all strap options accessible for re-configuration by option resistors or other means. It may keep you out of trouble and save a board spin. Since the hub operates at 3.3V, the signals from the SMARC Modules that are at 1.8V (RESET_OUT# and the I2C_GP_ signals, if used) levels need to be level shifted to 3.3V to interface to the hub. In this example, there are 7 down-stream ports. Two of them are used for off-Carrier cabled connections. These nets are designated with USB_HUB2_ and USB_HUB3_ prefixes. Since they are used for cabled connections, these are protected by a USB power switch (U19, in the second figure below). Four of the other hub ports are assumed to go to on-Carrier destinations (such as mini-PCIe cards, or a touch controller, or other on-Carrier USB peripheral). One of the 7 down-stream ports is not used. The behavior of a USB port, at least initially, may differ slightly depending on whether that port is direct from the SMARC Module or whether the port is through a hub. With software adjustments, or “tweaking”, the direct and through – the –hub ports may appear virtually identical to a client device.
SMARC Design Guide 2.0 Page 70 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 45 USB Hub (1 of 2)
C176
2
1
1uF16V
C177
16V1uF
2
1
V_3V3
04
02
1MEGOhmR263
21
C189
50V18pF
2
1
V_3V3
0402R27
4.7KOhm
21
0402
1KOhmR60
21
R28
04
02
DNI4.7KOhm
21
V_3V3
R264
0402
12KOhm
2 1
V_3V3
0402
4.7KOhm
R292 1
R300402
4.7KOhm
2 1
V_3V3
V_3V3
MOD
0402
0Ohm
R170
2 1
25V
C127100nF
2
1
V_3V3
4.7KOhm
R310402
2 1
V_3V3
R32
0402
4.7KOhm
2 1
V_3V3
V_3V3
R33
4.7KOhm
04022 1
0402
4.7KOhm
R342 1
0402R61DNI
1KOhm
21
R35
0402
4.7KOhm
21
V_3V3
4.7KOhm
0402
R362 1
V_3V3
Y1
24M
EG
Hz
18pFC190
50V2
1
SMSC USB2517I-JZXU16
QFN64
65
19
64
57
52
56
55
54
53
37
14
15
36
38
35
16
17
39
18
31
32
33
34
47
48
49
50
51
30
12
11
20
23
22
26
21
27
28
9
8
7
6
4
3
2
1
46
24
13
10
5
63
62
61
60
59
58
45
44
43
42
41
40
25
29PRTPWR_1
CRFILT
SDA/SMBDATA/NON_REM1
SCL/SMBCLK/CFG_SEL0
HS_IND/CFG_SEL1
RESET_N#
VBUS_DET
SUSP_IND/LOCAL_PWR/NON_REM0
USBDM_UP
USBDP_UP
XTALOUT
XTALIN/CLKIN
PLLFLT
RBIAS
VDD33_5
VDD33_10
CFG_SEL2
VDD33_24
VDD33_46
USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1
USBDM_DN2/PRT_DIS_M2
USBDP_DN2/PRT_DIS_P2
USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3
USBDM_DN4/PRT_DIS_M4
USBDP_DN4/PRT_DIS_P4
OCS_N1#
OCS_N2#
OCS_N4#
PRTPWR_2
OCS_N3#
PRTPWR_3
PRTPWR_4
USBDM_DN5/PRT_DIS_M5
USBDP_DN5/PRT_DIS_P5
PRTPWR_5
LED_A_N1#/PRTSWP1
LED_B_N1#/BOOST0
LED_A_N2#/PRTSWP2
LED_B_N2#/BOOST1
LED_A_N3#/PRTSWP3
LED_B_N3#/GANG_EN
LED_A_N4#/PRTSWP4
LED_B_N4#
LED_A_N5#/PRTSWP5
LED_B_N5#
PRTPWR_6
LED_A_N6#/PRTSWP6
LED_B_N6#
OCS_N5#
OCS_N6#
PRTPWR_7
LED_A_N7#/PRTSWP7
LED_B_N7#
OCS_N7#
USBDM_DN6/PRT_DIS_M6
USBDP_DN6/PRT_DIS_P6
USBDM_DN7/PRT_DIS_M7
USBDP_DN7/PRT_DIS_P7
VDD33_52
VDD33_57
VDD33_64
TEST
GND_PAD
Power
Upstream
Downstream1
Downstream2
Downstream3
Downstream4
EEPROM/Config
Downstream5
Downstream6
Downstream7
Misc
V_1V8
0402
DNI
R374.7KOhm
21
TI SN74LVC1T45
SC70-6
U17
2
4
6
5
3
1VCCA
A
DIR
VCCB
B
GND
100nFC187
16V 2
1
V_3V3
4.7KOhm
R380402
2 1
R1710Ohm
0402
DNI
21
DNI
0402R172
0Ohm
21
4.7KOhm
0402R392 1
V_3V3
10KOhm
0402
DNI
R250
21
04
02
10KOhmR251
DNI
21
04
02
10KOhmR252
DNI
21
0402R253
10KOhmDNI
21
0402R254
10KOhmDNI
21
10KOhmR255
0402
DNI
21
100nFC124
25V 2
1
16V
C188100nF
2
1
V_3V3
100nFC125
25V 2
1
10V4.7uFC201
2
1C128
25V100nF
2
1C129
100nF25V 2
1
100nF25V
C130
2
1C131
25V100nF
2
1
100nF25V
C132
2
1
10V
4.7uFC202
2
1
MOD
MOD
4.7KOhmDNI0
402
R40
21
R62
0402
1KOhm
21
V_3V3 V_3V3
R41
04
02
4.7KOhm
21
R63
DNI0402
1KOhm
21
V_3V3
0402
1KOhmR64
21
R424.7KOhm
DNI04
02
21
V_3V3
Atmel AT24HC02
SOIC8
U14
DNI
8
7
6
5
43
2
1A0
A1
A2 GND
SDA
SCL
WP
VCC
C126
25V100nF
DNI2
1
DNI10KOhm0
402 R256
21
V_3V3
USBHUB5_DN_MPCIe1_P
USBHUB5_DN_MPCIe1_N
HUB_RESET#
HUB_RESET#
USB1_DP_HUB
USB1_DN_HUB
OCS_1
USBHUB6_DN_IO2_P
USBHUB1_DN_IO1_N
USBHUB1_DN_IO1_P
USBHUB6_PRTPWR_IO2
USBHUB1_PRTPWR_IO1
USBHUB6_DN_IO2_N
USBHUB5_PRTPWR_MPCIe1
USBHUB4_DN_MPCIe0_N
USB_RBIAS
USBHUB4_PRTPWR_MPCIe0
OCS_5
OCS_7
OCS_6
CFG_SEL2
OCS_4
XTALIN
RESET_OUT#
NON_REM0
USBHUB_ID_A2
USBHUB_ID_A1
USBHUB_ID_A0
VBUS_DET_HUB
USBHUB4_DN_MPCIe0_P
XTALIN2
PLLFILT
CRFILT
SCL_CFG_SEL0
SDA_NON_REM
EEP_WP
I2C_GP_CK_3V3
I2C_GP_DAT_3V3
OCS_2
OCS_3
USBHUB3_DN_TYPEA1_N
USBHUB3_DN_TYPEA1_P
USBHUB2_DN_TYPEA0_P
USBHUB2_DN_TYPEA0_N
USBHUB2_PRTPWR_TYPEA0
USBHUB3_PRTPWR_TYPEA1
CFG_SEL1
SMARC Design Guide 2.0 Page 71 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 46 USB Hub (2 of 2)
THT
TE 5787617-1J4
2PORT
S4
S3
S2
S1
B4
B3
B2
B1
A4
A3
A2
A1VCCA
USBA_N
USBA_P
GNDA
VCCB
USBB_N
USBB_P
GNDB
S1
S2
S3
S4
FB8TDK ACM2012-900-2P-T002
190mOhm
1 4
32
190mOhm
TDK ACM2012-900-2P-T002FB9
1 4
32
SOT23
D3
TI TPD2E009
3
12
TI TPD2E009
D2
SOT23 3
12
V_3V3
R44
0402
4.7KOhm
21
R43
0402
4.7KOhm
21
100nF25V
C135
2
1
100nFC134
25V 2
1
25V100nF
C133
2
1
47uF16V
C206
2
1
16V47uFC205
2
1
SO8
U19TI TPS2052B
5
6
7
8
4
3
2
1GND
IN
EN1
EN2
OC1#
OUT1
OUT2
OC2#
V_5V0
1.7A
1050-8120
50mOhm
L12
21
50mOhm1.7A
1050-8120
L1121
USBHUB2_DN_TYPEA0_CONN_N
USBHUB2_DN_TYPEA0_CONN_P
USBHUB3_DN_TYPEA1_CONN_P
USBHUB3_DN_TYPEA1_CONN_N
USBHUB3_VBUS_A1
USBHUB3_VBUS_A1
USBHUB2_VBUS_A0
USBHUB2_VBUS_A0
OCS_2
USBHUB2_VBUS_A0_FB
OCS_3
USBHUB3_VBUS_A1_FB
USBHUB3_DN_TYPEA1_N
USBHUB3_DN_TYPEA1_P
USBHUB2_DN_TYPEA0_P
USBHUB2_DN_TYPEA0_N
USBHUB2_PRTPWR_TYPEA0
USBHUB3_PRTPWR_TYPEA1
Dual Stacked, Type A USB, R/A, TH
SMARC Design Guide 2.0 Page 72 of 119 Mar 23, 2017 ©SGeT e.V.
5.2 GBE
5.2.1 GBE Carrier Connector Implementation Example
SMARC Modules include GBE MAC / PHYs but do not include the isolation magnetics. If the SMARC GBE is used, then the Carrier must include GBE compatible magnetics with 1:1 turn ratios. Usually RJ45 jacks with integrated magnetics are used. An example is given in the following figure.
Figure 47 GBE without POE
There are two kinds of 1000Base-T Line Driver implementations. The current mode line drivers pull current from one side of the magnetic. To generate the IEEE-specified five level pulse amplitude modulated (PAM) signals two 50 Ohm termination resistors to center tap voltage are required. They are placed in parallel to the output impedance at line driver side. The magnetic center taps are connected to each other and to the center tap reference voltage. This voltage can be provided by the GBE PHY to the magnetic with the GBE_CTREF pins at the SMARC Module. Voltage mode line driver use series resistors to generate the PAM signal at the magnetic. They are more power efficient, but even more complex. The line driver enables the internal series resistors at the transmit signal pairs.
SMARC Design Guide 2.0 Page 73 of 119 Mar 23, 2017 ©SGeT e.V.
For most voltage mode PHYs the center taps at the magnetic can be connected to each other and clamped by separate or combined capacitors. They are not connected to any center tap voltage provided by the PHY. There are some voltage mode PHYs available, that do not allow to combine the center taps, due to different voltage levels at RX and TX pairs. This PHYs do not provide the usage of RJ45 connectors with integrated magnetics. See SMARC Module documentation for selected GBE PHY and line driver version.
Figure 48 GBE separate magnetic for current and voltage mode line driver
SMARC Design Guide 2.0 Page 74 of 119 Mar 23, 2017 ©SGeT e.V.
5.2.2 GBE Mag-Jack Connector Recommendations
SMARC GBE Mag-Jack (magnetics integrated into an RJ45 jack housing) should meet the following general characteristics:
The turn ratios should be 1:1
An integrated common mode choke should be included
Termination resistors on the primary side (i.e. the Ethernet cable side) should be included
The secondary side transformer center-taps may be tied together or may be brought out separately. If they are brought out separately, they are tied together on the Carrier PCB.
The secondary side center-taps need to be tied to the SMARC GBE_CTREF voltage, with bypass capacitors connected to GND.
Mag-Jacks (and RJ45 jacks in general) are available in tab-up and tab-down configurations. The pin order on the Mag-Jack reverses between the tab-up and tab-down configurations. One of them may work better for your layout than the other (although since only four pairs are involved, this may not be a major concern). Tab-up is generally more common; tab-down parts do exist; most tab-down parts target low-profile needs in which part of the Mag-Jack connector height is hidden by a Carrier PCB cutout.
Table 7 Recommended Gigabit Ethernet Connectors with Magnetics
Manufacturer
Manufacturer P/N
Description
Bel Fuse L829-1J1T-43 Tab Up, 1:1 turns ratio, 3 LEDs, 0.950” depth
Pulse JK0-0136NL Tab Up, 1:1 turns ratio, 3 LEDs, 1.30” depth
Tyco 1840437-1 Tab Down, 1:1 turns ratio, 3 LEDs, special low profile feature
Wurth 7499111447 Tab Up, 1:1 turns ratio, 4 LED
Note that POE (Power Over Ethernet) capable jacks are slightly different – they have extra pins to bring the POE power into the system. A GBE POE jack may be used in a non-POE system, but not the other way around. A GBE POE example is given later in this Design Guide.
SMARC Design Guide 2.0 Page 75 of 119 Mar 23, 2017 ©SGeT e.V.
5.2.3 GBE LEDs
Mag-Jack LED implementations vary widely. There does not seem to be any common standard, so be aware. The SMARC GBE status LED outputs are open drain outputs that are capable of sinking a minimum of 24 mA. They may be connected directly to the cathode of GBE status LEDs as shown in the following figure. Make sure the resistors can handle the expected power dissipation.
Figure 49 GBE LED Current Sink
68 OHM
68 OHM
V_3V3
MAG JACK
Bel Fuse L829-1J1T-43 or similar
GBE_LINK_100#
GBE_LINK_1000#
Direct from
SMARC Module
GRNORG
68 OHM
V_3V3
GBE_ACT#Direct from
SMARC Module
YEL
SMARC Design Guide 2.0 Page 76 of 119 Mar 23, 2017 ©SGeT e.V.
Some integrated GBE Mag Jacks have a pair of opposing (cathode to anode) diodes, as shown in the figure below. In this case, Carrier board buffers are recommended, as the SMARC Module status LED lines can sink current but cannot source it.
Figure 50 GBE LED Current Sink / Source
MAG JACK
Bel Fuse 0826-1X1T-GH-F or similar
GBE_LINK_100#
GBE_LINK_1000#
Direct from
SMARC Module
ORGGRN
68 OHM
V_3V3
GBE_ACT#
YEL
V_3V3
V_3V3
V_3V3
Fairchild
NC7SZ125
Fairchild
NC7SZ125
68 OHM
10
K
10
K
SMARC Design Guide 2.0 Page 77 of 119 Mar 23, 2017 ©SGeT e.V.
5.2.4 GBE software-defined Pins
The Precision Time Protocol (PTP) (according to IEEE 1588) is used to synchronize clocks throughout a computer network. If it is implemented in the hardware of the Ethernet controller clock accuracy in the sub-microsecond range can be achieved. The Ethernet controller usually has several GPIO pins whereof one can be connected to the GBE_SDP pin. This pin can be used as output and distribute synchronized clocks or trigger impulses. When used as input it can synchronize the internal clock of the controller to external clocks for example from GPS receivers. Such a system could serve as a master clock. These functions depend highly on the used Ethernet controller and wiring – check with your Module vendor.
5.3 PCIe
5.3.1 General
PCI Express (or PCIe) is a scalable, point-to-point serial bus interface commonly used for high speed data exchange between a PCIe host, or root, and a target device. It is scalable in the sense that there may be link widths, per the PCIe specification, that are x1, x2, x4, x8, x16 or x32. SMARC currently calls out x1, x2 and x4 operation. Up to four PCIe x1 links may be implemented on a SMARC Module. There are three generations of PCIe defined, with each successive generation offering a speed increase, per the table below. The PCIe generation that may be supported on a particular SMARC Module is design and SOC dependent.
Table 8 PCIe Data Transfer Rates
PCIe Generation
Link Speed (x1 link)
Encoding / Overhead
Net Data Transfer Rate
1 2.5 GT/s 8b/10b 20% 250 MB/s
2 5.0 GT/s 8b/10b 20% 500 MB/s
3 8.0 GT/s 128b / 130b 1.54% 985 MB/s
PCI Express is defined in a series of documents maintained by the PCI Special Interest Group (www.pci-sig.org). The three most important documents to obtain are the Base Specification, the Card Electromechanical (CEM) Specification (which describes slot cards) and the Mini Card Electromechanical Specification (which describes the small format cards commonly referred to as Mini-PCIe cards). The four possible PCIe links on a SMARC Module are designated with net name prefixes PCIE_A_, PCIE_B_, PCIE_C_ and PCIE_D_. Each of the four has the following signal set (x in the table below designates A, B, C or D).
Table 9 SMARC PCIe Signal Summary
Signal Description Signal Type Notes
PCIE_x_TX+ PCIE_x_TX-
Data out of Module Differential pair Capacitively coupled – on Module
PCIE_x_RX+ PCIE_x_RX-
Data into Module Differential pair Capacitively coupled – off Module
PCIE_x_REFCK+ PCIE_x_REFCK-
Reference clock out of Module
Differential pair No caps needed
PCIE_x_RST# Active low output to reset the PCIE_x device
Single ended
SMARC Design Guide 2.0 Page 78 of 119 Mar 23, 2017 ©SGeT e.V.
5.3.2 PCIe x1 Device Down on Carrier
An example of a PCIe x1 “device down” on the Carrier is shown below. Coupling caps on the SMARC PCIe TX and PCIe reference clock pairs are not needed on the Carrier. Coupling caps on the SMARC PCIe RX pair (TX pair from the Carrier PCIe device) are needed. They should be placed close to the Carrier device PCIe TX pins. Use 0402 package 0.2 uF X7R or X5R dielectric discrete ceramic capacitors. Do not use a capacitor array. Place the parts in a way to preserve the symmetry of the differential pair. Usually they are placed close to the Carrier device TX pins to avoid a via transition.
Figure 51 Interfacing a PCIe x1 Carrier Board Device
SM
AR
C M
OD
UL
E
PCIE_RX+
PCIE_RX-
PCIE_REFCK+
PCIE_REFCK-
PCIE_RST#
PC
Ie d
evic
e
PCIE_RX+
PCIE_RX-
PCIE_TX+
PCIE_TX-
PCIE_REFCK+
PCIE_REFCK-
PCIE_RST#
PCIE_TX+
PCIE_TX-
SMARC Design Guide 2.0 Page 79 of 119 Mar 23, 2017 ©SGeT e.V.
5.3.3 Mini-PCIe
A SMARC Mini-PCIe implementation example is shown below. Mini-PCIe cards are defined to have pins for PCIe x1 and also a USB interface. A given card generally uses only one or the other. If you know exactly what Mini-PCIe card you plan to use, it is possible to omit either USB or PCIe. Generally, Mini-PCIe 802.11 WiFi cards use the PCIe interface and cellular modem cards use the USB interface.
Figure 52 Mini-PCIe Slot
4
3
2
1
J19
ST
Molex 47023-0001
6/2x3/2.54
6
5VCC
RESET
CLK
GND
VPP
IO
100nFC12
25V2
1
25V
C13100nF
2
1
MOD
C14
25V100nF
2
1
C15100nF25V
2
1
25V100nFC16
2
1
25V
C17100nF
2
1
V_3V3
DNI4.7KOhm
0402R2
2 1
25V100nFC18
2
1 C19100nF25V
2
1
V_3V3
DNIR95
0402
0Ohm2 1
MOD
MOD
MOD
MOD
Molex 67910-0002
52/1/2x26/0.80
J20
RA
S2S1
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1WAKE#
COEX1
COEX2
CLKREQ#
GND9
REFCLK-
REFCLK+
GND15
RSVD17
RSVD19
GND21
PERN0
PERP0
GND27
GND29
PETN0
PETP0
GND35
GND37
3.3V_AUX_39
3.3V_AUX_41
GND43
RSVD45
RSVD47
RSVD49
RSVD51
3.3V_AUX_2
GND4
1.5V_6
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP
GND18
W_DISABLE#
PERST#
3.3V_AUX_24
GND26
1.5V_28
SMB_CLK
SMB_DATA
GND34
USB_D-
USB_D+
GND40
LED_WWAN#
LED_WLAN#
LED_WPAN#
1.5V_48
GND50
3.3V_AUX_52
S1 S2
6.3V22uFC232
2
1
6.3V
C23322uF
2
1
6.3V
C23422uF
2
1
6.3V
C23522uF
2
1
V_1V5
MOD
MOD
J22
ST
S4S3
S2S1
S1 S2
S3 S4
Mini_PCIE_latchJ23
ST
DNI
S4S3
S2S1
S1 S2
S3 S4
Mini_PCIE_latch
22uFC236
6.3V2
1
V_3V3
MOD
10uF
2
1
25V
C237C20100nF
25V 2
125V100nFC21
2
1
25V
C23810uF
2
1
PCIE_A_RX_P
PCIE_A_RX_N
PCIE_A_TX_P
PCIE_A_TX_N
PCIE_A_REFCK_N
PCIE_A_REFCK_P
USBHUB5_DN_MPCIe1_P
USBHUB5_DN_MPCIe1_N
PCIE_A_RST#
PCIE_A_CKREQ#
I 2C_PM_CK_3V3
I2C_PM_DAT_3V3
V_SIM_PWR
V_SIM_PWR
PCIE_WAKE#
V_SIM_VPP
V_SIM_VPPSIM_RST
SIM_RST
SIM_DATA
SIM_DATA
SIM_CLK
SIM_CLK
Full Mini card Latch Half Mini card Latch
From USB Hub
Level translated I2C_PM bus
Mini-PCIe, R/A, SMT
SIM Card Holder, ST, SMT
SMARC Design Guide 2.0 Page 80 of 119 Mar 23, 2017 ©SGeT e.V.
5.3.4 PCIe Reference Clock buffer
The SMARC 2.0 Specification calls for three copies of the PCIe reference clock pairs to be brought out of the Module. This clock is a 100MHz differential pair and is sometimes known as a "hint" clock. The clock allows the PLL in the target PCIe device to lock faster onto the embedded clock in the PCIe bit stream. If the Carrier Board implements only three PCIe devices or slots, then the PCIe reference clock pairs from the Module may be routed directly to that devices or slots. However, if there are four PCIe devices or slots on the Carrier Board, then one of the Module's PCIe reference clock should be buffered. A device which meets the jitter requirements for the intended PCI Express generation must be used. The IDT9DB233, IDT9DB433, IDT9DB844 have two, four and eight differential output replicas of the input clock, respectively. Each target device (PCIe "device down" chip, slot, Express Card slot, Mini-PCIe device, M.2 device, PEG slot) should get an individual copy of the reference clock. Similar parts may be available from other vendors. The PCIe Clock buffers have both PLL and bypass modes. In some situations it is preferable to operate the clock buffer in bypass mode. The reference clock pairs should be routed as directly as possible from source to destination. The following notes apply to Figure 53 PCIe Clock buffer. Each clock pair is routed point to point to each connector or end device using differential signal routing rules. Each clock output pair in the example shown is terminated close to the IDT9DB433 buffer pins with a series resistor (shown as 33 ohms) and a termination to GND (shown as 49.9 ohms), per the vendor's recommendations. Other vendors may have different recommendations, particularly in regard to the source termination to GND. SMBUS software can enable or disable clock-buffer outputs. So the SMBUS pins of the clock buffer should be connected to the I2C_PM pins of the SMARC Module. Configuration resistors or alternatively the SMBUS also allow software to put the clock buffer into "Bypass Mode", which experience has shown is needed in some Carrier situations. Disable unused outputs to reduce emissions. The CLKREQ0# and CLKREQ1# should be pulled low to enable the corresponding clock buffer outputs. For applications in which power management is not a concern, these inputs may be tied low to permanently enable the outputs. SMBCLK and SMBDAT need to be connected to a 3.3V I2C bus as described in chapter 4.2.2.
Figure 53 PCIe Clock buffer
OPEN
SMBus Addres selection
Assembled part Address
R6
R5 + R6
R5
DA/DB
DC/DDD8/D9
OPEN
PLL Operating mode selection
R7 + R8
R8
ModeAssembled part
PLL 100M Lo BW
PLL 100M Hi BW
Bypass
R7
V_3V3
V_3V3
V_3V3
V_3V3
V_3V3 V_3V3
V_3V3 V_3V3
PCIE_CLK_REQ1#
PCIE_CLK_6+PCIE_CLK_6-
PCIE_CLK_1+PCIE_CLK_1-
PCIE_CLK_REQ6#
MODPCIE_A_REFCK_P
MODPCIE_A_REFCK_N
I2C_PM_SCL_3V3
I2C_PM_DAT_3V3
C310uF
C610n
C2100n
R147K
R7
10K
R6
10K
FB1
120-Ohms@100MHz
R1749.9
FB3
120-Ohms@100MHz
R13475
R5
10K
FB2
120-Ohms@100MHz
R347K
R1649.9
R12 33R11 33
R1549.9
R1449.9
R10 33R9 33
DIFFERENTIAL
CLOCK BUFFER
IDT9DB433U1
VDD5
VDD11
VDD16
VDD18
VDDA28
SRC_IN2
SRC_IN#3
SMBCLK13
SMBDAT14
IREF26
GNDA27
GND15GND4
DIF_623
DIF_16
DIF_1#7
BYP#_HIBW_LOBW12
OE1#8
PD#25
VDD24
VDDR1
DIF_29
DIF_2#10
DIF_520
DIF_5#19
DIF_6#22
OE6#21
SMB_ADR_TRI17
C510n
R247K
C4100n
C110uF
R8
10K
C710uF
SMARC Design Guide 2.0 Page 81 of 119 Mar 23, 2017 ©SGeT e.V.
5.4 SATA
5.4.1 General
Serial ATA (or SATA) is a high speed point to point serial interface that connects a host system to a mass storage device such as rotating hard drive, solid state drive or an optical drive. Data and clock are serialized onto a single outbound differential pair and a single inbound pair. Data link rates of 1.5, 3.0 and 6.0 Gbps are defined by the SATA specification. A SATA link is AC coupled, but the coupling capacitors are defined in the SMARC specification to be on the Module, for both SATA transmit and receive pairs.
Table 10 SATA SSD Form Factors
Format Notes
IC (chip level) Smallest form factor. Densities to 64GB.
mSATA MO-300
Small form factor SATA module, defined in the SATA specification (search for “mSATA” in the specification). SLC and MLC versions are generally available. The mSATA form factor is roughly 30mm x 51mm x 3.5mm (see the specification for exact dimensions).
Slim SATA MO-297
Small form factor solid-state SATA modules that use a standard SATA connector (7 pin data / GND section and 15 pin power section). The connector is compatible with the connector used on larger format (2.5”) hard drives used in PC systems. Available in SLC and MLC versions. Form factor is defined by JEDEC MO-297.
CFast Removable card format with SSD interface; similar to popular Compact Flash (parallel interface) cards. Form factor is roughly 36mmx 43mm x 3.6mm.
SSD 1.8” Solid State Disk in traditional 1.8” format that was originally used for rotating drives
SSD 2.5” Solid State Disk in traditional 2.5” format that was originally used for rotating drives
Table 11 SATA SSD Vendors
Vendor Link SATA Products
Greenliant www.greenliant.com Chip-level SLC and MLC NAND flash with SATA interface.
Innodisk www.innodisk.com mSATA / MO-300 Slim SATA / MO-297 CFast SSD 2.5”
Intel www.intel.com mSATA / MO-300 SSD 1.8” SSD 2.5”
SMART Modular www.smartm.com mSATA / MO-300 Slim SATA / MO-297 SSD 1.8” SSD 2.5”
Swissbit www.swissbit.com mSATA / MO-300 Slim SATA / MO-297 CFast SSD 1.8” SSD 2.5”
Transcend www.transcend-info.com mSATA / MO-300 Slim SATA / MO-297 SSD 1.8” SSD 2.5”
Virtium www.virtium.com mSATA / MO-300 Slim SATA / MO-297 SSD 1.8” SSD 2.5”
SMARC Design Guide 2.0 Page 82 of 119 Mar 23, 2017 ©SGeT e.V.
5.4.2 mSATA / MO-300
A popular SATA form factor for SMARC systems is the mSATA / JEDEC MO-300. This is physically the same as a mini-PCIe card, and uses the same Carrier socket, but the mini-PCIe pinout is re-purposed for SATA use. A schematic example is shown below. The pin names within the J21 connector box outline below are the mini-PCIe pin names. The net connections outside the box show the appropriate connections for mSATA / MO-300 SATA use. Coupling capacitors are not needed on the Carrier SATA TX and RX pairs. mSATA / MO-300 SATA is described in the Serial ATA Revision 3.1 specification document – search for “mSATA”.
Figure 54 mSATA / MO-300
According to the mSATA specification SATA_RX_P (positive signal) has to be connected to Pin 23 of the Mini-PCIe socket although this is used as a negative signal with PCIe. The same applies to SATA_RX_N and Pin 25 vice versa. Nevertheless SATA_TX_N and SATA_TX_P use the right polarity of the socket (Pin 31 and 33).
5.5 M.2
The M.2 form factor is a specification for mobile expansion cards and is supposed to replace the Mini PCIe cards and mSATA cards. The M.2 is a smaller form factor in both size and volume. It is a family of form factors that will enable expansion, contraction, and higher integration of functions onto a single form factor module solution. PCIe, SATA, USB 3.0 and SDIO are provided through the M.2 connector. It is up to the manufacturer of the M.2 host or device to select which interfaces are to be supported. The M.2 connector has different
MOD
R266
0402
100O
hm
21
D9
LTST-C190KGKT
12
MOD
V_3V3
100nFC22
25V2
1
25V100nFC23
2
1C24
25V100nF
2
1
100nFC25
25V2
1
100nF25V
C26
2
1
TP_SMD_35
TP1
52/1/2x26/0.80
Molex 67910-0002
J21
RA
S2S1
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1WAKE#
COEX1
COEX2
CLKREQ#
GND9
REFCLK-
REFCLK+
GND15
RSVD17
RSVD19
GND21
PERN0
PERP0
GND27
GND29
PETN0
PETP0
GND35
GND37
3.3V_AUX_39
3.3V_AUX_41
GND43
RSVD45
RSVD47
RSVD49
RSVD51
3.3V_AUX_2
GND4
1.5V_6
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP
GND18
W_DISABLE#
PERST#
3.3V_AUX_24
GND26
1.5V_28
SMB_CLK
SMB_DATA
GND34
USB_D-
USB_D+
GND40
LED_WWAN#
LED_WLAN#
LED_WPAN#
1.5V_48
GND50
3.3V_AUX_52
S1 S2
V_1V5
V_3V3
25V
C27100nF
2
1
25V
C28100nF
2
1
100nFC29
25V2
1
MOD
MOD
ST2/2x1/24.2
J24
S4S3
S2S1
S1 S2
S3 S4
Mini_PCIE_latch
MOD
SATA_TX_P
SATA_RX_P
SATA_RX_N
SATA_TX_N
SATA_ACT#
SATA_PRSNT_DET
Mini-PCIe, R/A, SMT
SMARC Design Guide 2.0 Page 83 of 119 Mar 23, 2017 ©SGeT e.V.
keying notches that denote various purposes and capabilities of M.2 hosts and modules, preventing plugging of M.2 modules into feature-incompatible host connectors. M.2 cards are available in various physical sizes, starting from 2230 wireless cards, up to 22110 SSDs. Carrier Board designers must provide a stand-off for each physical card size they would like to support. The module stand-off should be directly connected to Carrier board’s GND, as it is part of the M.2 Electrical and Thermal Ground Path.
5.5.1 B keying
M.2 Key B sockets support a wide range of add on cards, like SSDs, GPS and WiFi devices. Some high-speed interfaces like SATA and PCIe share the same pins at the M.2 Key B connector. The desired interface configuration can be decoded by CONFIG_[0-3] which are either tied to GND or left floating by the M.2 card. At the time of writing, a majority of medium-speed (SATA) SSDs implement dual-keying which allows to plug them into Key B and Key M sockets. High-End SSDs often come in a Key-M only format, as they rely on a PCIe x4 link.
Figure 55 M.2 Key B
M.2 Socket 2: Key B
10V10V16V16V
M3x0.5 Tapped2.45mm Shoulder HeightSMT
connector height: 4.2mm
16V16V
DNI
DNI
DNI
DNI
DNI
16V16V16V16V16V 16V
16V
16V
USB4-
USB4+USB4+_M2USB4-_M2
PCIE_A_REFCK+PCIE_A_REFCK-
PCIE_A_RST#
PCIE_WAKE#
I2C_GP_CKI2C_GP_DAT
I2C_ALERT#_M2GPIO8
M2_CONFIG0M2_CONFIG1M2_CONFIG2M2_CONFIG3
PCIE_A_TX+PCIE_A_TX-
SATA_TX+SATA_TX-
PCIE_A_RX+PCIE_A_RX-
SATA_RX-SATA_RX+
M2_PWROFF#
PCIE_A_RX+/SATA_RX-PCIE_A_RX-/SATA_RX+
PCIE_A_TX-/SATA_TX-PCIE_A_TX+/SATA_TX+
PCIE_A_RX+/SATA_RX-PCIE_A_RX-/SATA_RX+
PCIE_A_TX-/SATA_TX-PCIE_A_TX+/SATA_TX+
PCIE_B_TX+PCIE_B_TX-
USB2_SSTX+USB2_SSTX-
PCIE_B_RX+PCIE_B_RX-
USB2_SSRX+USB2_SSRX-
PCIE_B_RX+/USB2_SSRX+PCIE_B_RX-/USB2_SSRX-
PCIE_B_TX-/USB2_SSTX-PCIE_B_TX+/USB2_SSTX+
PCIE_B_RX+/USB2_SSRX+PCIE_B_RX-/USB2_SSRX-
PCIE_B_TX-/USB2_SSTX-PCIE_B_TX+/USB2_SSTX+
M2_CONFIG0 M2_CONFIG1 M2_CONFIG2 M2_CONFIG3
SATA_SEL
SATA_SEL
M2_CONFIG0
M2_CONFIG3
M2_CONFIG3#M2_SSIC
M2_SSIC
M2_CONFIG3
M2_CONFIG0
M2_CONFIG0#M2_USB3
M2_USB3
RESET_OUT#
M2_DEVSLP
M2_UIM_PWRM2_UIM_DATM2_UIM_CLKM2_UIM_RST
M2_UIM_PWR
UIM_VPP
M2_UIM_RST
M2_UIM_CLK
M2_UIM_DAT
I2C_CLK_M2I2C_DAT_M2
I2S2_CK M2_I2S_CKM2_I2S_SDII2S2_SDI
I2S2_SDO M2_I2S_SDOI2S2_LRCK M2_I2S_LRCK
V_3V3
V_3V3
V_3V3V_3V3
V_3V3 V_3V3 V_3V3 V_3V3
V_3V3
V_3V3 V_3V3
V_3V3 V_3V3
V_1V8
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
T1BDiodes BSS138DW-7-F
5
43
M2
STANDOFF
1
U4
Fairchild NC7SZ08
12
43
5
0402R184 0Ohm
C168100nF
C171100nF
0402R169 10kOhm
C162100nF
C163100nF
C16510nF
U1
NXP CBTL02043A
A0_P3
A0_N4
A1_P7
A1_N8
B0_P19
B0_N18
B1_P17
B1_N16
C0_P15
C0_N14
C1_P13
C1_N12
SEL9
XSD2
VD
D6
VD
D10
VD
D1
GN
D5
GN
D11
GN
D20
HP
AD
21
0402R187 0Ohm
C173100nF
C169100nF
0402R162 0Ohm
U2
NXP CBTL02043A
A0_P3
A0_N4
A1_P7
A1_N8
B0_P19
B0_N18
B1_P17
B1_N16
C0_P15
C0_N14
C1_P13
C1_N12
SEL9
XSD2
VD
D6
VD
D10
VD
D1
GN
D5
GN
D11
GN
D20
HP
AD
21
T1ADiodes BSS138DW-7-F
2
16
0402
R179
10kOhm
0402R188 0Ohm
C174100nF
C172100nF
0402
R178
10kOhm
0402R186 0Ohm
0402R191 0Ohm
C16010uF
T2BDiodes BSS138DW-7-F
5
43
FB15TDK ACM2012-900-2P-T002
1
4 3
2
0402R192 10kOhm
T3ADiodes BSS138DW-7-F
2
16
C167100nF
C166100nF
0402
R175
10kOhm
T2ADiodes BSS138DW-7-F
2
16
C170100nF
0402
R183
10kOhm
0402
R180
10kOhm
M.2 Slot B
Platform Pinout
X1
TE Connectivity 2199230-5
CONFIG_31
VCC_3p32
GND3
VCC_3p34
GND5
FULL_CARD_PWROFF#_1p8/3p36
USB_D+7
W_DISABLE_1#_3p38
USB_D-9
GPIO9_(LED1#/DAS_DSS#)_3p310
GND11
GPIO5_(AUDIO0/RFU)_1p820
CONFIG_021
GPIO6_(AUDIO1/RFU)_1p822
GPIO11_(WoWWAN#)_1p823
GPIO7_(AUDIO2/RFU)_1p824
DPR_1p825
GPIO10_(W_DISABLE_2#)_1p826
GND27
GPIO8_(AUDIO3/RFU)_1p828
PERn1/USB30_RX-/SSIC_RX-29
UIM_RESET30
PERp1/USB30_RX+/SSIC_RX+31
UIM_CLK32
GND33
UIM_DATA34
PETn1/USB30_TX-/SSIC_TX-35
UIM_PWR36
PETp1/USB30_TX+/SSIC_TX+37
DEVSLP_3p338 GND
39
GPIO0_(GNSS_SCL/SIM_DET2)_1p840
PERn0/SATA_B+41
GPIO1_(GNSS_SDA/UIM_DAT2)_1p842
PERp0/SATA_B-43
GPIO2_(GNSS_IRQ/UIM_CLK2)_1p844
GND45
GPIO3_(SYSCLK/GNSS_0/UIM_RST2)_1p846
PETn0/SATA_A-47
GPIO4_(TX_BLK/GNSS_1/UIM_PWR2)_1p848
PETp0/SATA_A+49
PERST#_3p350
GND51
CLKREQ#_3p352
REFCLKn53
PEWAKE#_3p354
REFCLKp55
MFG_DAT56
GND57
MFG_CLK58
ANTCTL0_1p859
COEX3_1p860
ANTCTL1_1p861
COEX2_1p862
ANTCTL2_1p863
COEX1_1p864
ANTCTL3_1p865
SIM_DETECT_1p866
RESET#_1p867
SUSCLK_3p368
CONFIG_169
VCC_3p370
GND71
VCC_3p372
GND73
VCC_3p374
CONFIG_275
H176
H277
0402
R181
10kOhm
0402
R1850Ohm
0402
R182
10kOhm
0402R189 22Ohm
T3BDiodes BSS138DW-7-F
5
43
0402R190 0Ohm
U3
Fairchild NC7SZ08
12
43
5
X2
Molex 788000001
VCCC1
RESETC2
I/OC7
GNDC5
VPPC6
CLKC3
SH3SH3SH2SH2SH1SH1
SH4SH4
C16410nF
C16110uF
SMARC Design Guide 2.0 Page 84 of 119 Mar 23, 2017 ©SGeT e.V.
5.5.2 M keying
M.2 Key M is intended for use with SSD Cards. The connection can either be done by PCIe x4 or a single SATA lane. In this example schematic both PCIe and SATA is connected to the M.2 socket according to the M.2 specification. The M.2 SSD decides with configuration pins, which interface should be used for this regarding SSD. It is recommended to check with your SMARC Module vendor if PCIe x4 is supported by the used SMARC Module, if PCIe x4 SSD will be connected. Other PCIe devices could only be used if a PCIe bridge is implemented on the Carrier board. Both used interfaces by the M.2 SSD and the SMARC Module must match.
Figure 56 M.2 Key M
5.5.3 E keying
M.2 Key E is intended for use with Wireless Connectivity cards, which are WiFi / Bluetooth cards in most of the cases. WiFi is utilizing either PCIe or SDIO connection to the host system. It is recommended to check with your SMARC Module vendor if SDIO could be used for WiFi devices as well. USB or UART+I2S are used to connect the Bluetooth Interface IC to the Host system. NFC capable add-in cards may also require an I2C connection. Please be aware that the I/O voltage of I2C was changed from 3.3V to 1.8V per ECN after the official M.2 specification release.
Q63
QBSS138W
2
1
3
A0-
GND_4
A1-
VDD_8
SEL
VDD_5
A1+
A0+
VDD_13
GND_14
GND_17
VDD_18
GND_19
A3+
A3-
A2-
C3+
C2-
B3+
B2-
B2+
C2+
B3-
C3-
C0-
C0+
B0-
B0+
GND_39
B1-
B1+
C1+
GND_1
A2+
GND_21
C1-
VDD_40
VDD_30
VDD_20
GND_10
GND_41
VDD_42
TH_PAD43
42
41
10
1
27
20
30
40
31
21
11
U27
28
29
25
5
6
2
26
13
14
UPI3PCIE3412
17
18
19
15
9
16
4
8
7
3
32
22
33
34
37
12
23
38
39
35
36
24
V_1V5
NC_36
DEVSLP
3V3_2
3V3_4
NC_6
NC_8
DAS/DSS#/LED1#
3V3_12
3V3_14
3V3_16
3V3_18
NC_20
NC_22
NC_24
NC_26
NC_28
NC_30
UART_RXD
NC_34
NC_40
NC_42
NC_44
NC_46
NC_48
PERST#
CLKREQ#
GND_1
GND_3
PER3_N
PER3_P
GND_9
PET3_N
PET3_P
GND_15
PER2_N
PER2_P
GND_21
PET2_N
PET2_P
GND_27
PER1_N
PER1_P
GND_33
PET1_N
PET1_P
GND_39
PER0_N/SATA_B+
PER0_P/SATA_B-
GND_45
PET0_N/SATA_A-
PET0_P/SATA_A+
GND_51
CONNECTOR_KEY_64
CONNECTOR_KEY_60
3V3_72
SUSCLK
NC_58
PEWAKE#
3V3_74
3V3_70
CONNECTOR_KEY_66
CONNECTOR_KEY_62
NC_56
GND_71
PEDET
CONNECTOR_KEY_63
CONNECTOR_KEY_59
REFCLK_N
GND_7575
GND_73
CONNECTOR_KEY_65
CONNECTOR_KEY_61
GND_57
REFCLK_P
NC_67
30
32
34
74
35
40
42
6
70
37
66
39
7
62
9
56
41
8
10
12
14
44
16
46
43
18
20
48
22
24
11
26
45
28
61
71
69
63
47
59
13
15
17
19
50
31
2
4
38
21
72
68
57
36
52
1
55
33
67
49
51
58
J34
64
53
73
65
JM2MINI_M-KEY
23
5
25
54
3
27
60
29
C10U
S0
5V
16_X
7R
10u
C385
R1%0R0S02R456
R453
R1%
10K
0S
02
R454
DN
I
R1%
10K
0S
02
R1%
10K
0S
02
R484
R1%
10K
0S
02
R460
R1%
10K
0S
02
R482
R1%
10K
0S
02
R483
R455R1%0R0S02
C411
10u
C10U
S05V
16_X
7R
C412
C10U
S05V
16_X
7R
10u
V_3V3
V_3V3_M2
V_3V3_M2
V_3V3_M2
V_3V3_M2
10u
C10U
S05V
16_
X7R
C380
R179R1%0R0S02
0R
R181R1%0R0S02
0R
R180R1%0R0S02
0R
R182R1%0R0S02
0R
RESET_OUT#
PCIE_A_REFCK_P
PCIE_A_REFCK_N
PCIE_A_RX_P
PCIE_A_RX_N
PCIE_B_RX_P
PCIE_B_RX_N
PCIE_C_RX_P
PCIE_D_RX_P
PCIE_D_RX_N
PCIE_A_TX_P
PCIE_A_TX_N
PCIE_B_TX_P
PCIE_B_TX_N
PCIE_C_TX_P
PCIE_C_TX_N
PCIE_D_TX_P
PCIE_D_TX_N-
SATA_TX_P
SATA_TX_N
SATA_RX_P
SATA_RX_N
PCIE_C_RX_N
SSD_DEEP_SLEEP
M2_CONFIG_1
M2_CONFIG_1
M2_CONFIG_2
M2_CONFIG_2
M2_CONFIG_3
M2_CONFIG_3
EN_M2_SATA_PCIE#
EN_M2_SATA_PCIE#
SATA_SW_PCIE_RX_P
SATA_SW_PCIE_RX_P
SATA_SW_PCIE_RX_N
SATA_SW_PCIE_RX_N
SATA_SW_PCIE_TX_P
SATA_SW_PCIE_TX_P
SATA_SW_PCIE_TX_N
SATA_SW_PCIE_TX_N
SATA_RX_C_N
SATA_RX_C_P
SATA_TX_C_N
SATA_TX_C_P
PCIE_A_TX_C_P
PCIE_A_TX_C_N
CLKREQ_M2#
Mounting holes for M.2
HIGH : SATA
LOW : PCIE
1 A
7
7
7
7
7
7
R4980RR1%0R0S02
C370 10n C10NS02
C368 10n C10NS02C367 10n
C10NS02
C369 10n C10NS02
DR8 DR9
DR10 DR11
C374
100n
C100N
S02V
50_X
7R
C366 100n C100NS02V50_X7R C365 100n
C100NS02V50_X7R
C406
100n
C100N
S02V
50_X
7R
C405
100n
C100N
S02V
50_X
7R
C394 10n C10NS02
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
SMARC Design Guide 2.0 Page 85 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 57 M.2 Key E
M.2 Socket 1: Key E
10V10V16V16V
M3x0.5 Tapped2.45mm Shoulder HeightSMT
connector height: 4.2mm
16V16V
DNI
16V16V 16V16V
DNI
USB4-
USB4+USB4+_M2USB4-_M2
PCIE_B_RX+PCIE_B_RX-
PCIE_B_TX+PCIE_B_TX-
PCIE_B_REFCK+PCIE_B_REFCK-
PCIE_B_RST#
PCIE_WAKE#
M2_LED1_WIFIM2_LED2_BT
SER2_TX
SER2_RTS#SER2_RX
SER2_CTS#PCIE_WAKE# UART_WAKE#
I2S2_CK
I2S2_SDO
I2S2_LRCKI2S2_SDI I2S2_SDI_M2
I2C_GP_CKI2C_GP_DAT
I2C_ALERT#_M2 GPIO8
SDIO_D0SDIO_D1SDIO_D2SDIO_D3
SDIO_D0_1V8SDIO_D1_1V8SDIO_D2_1V8SDIO_D3_1V8
SDIO_D0_1V8SDIO_D1_1V8SDIO_D2_1V8SDIO_D3_1V8
SDIO_CMDSDIO_CK
SDIO_PWR_EN
SDIO_CMD_1V8SDIO_CK_1V8
SDIO_PWR_EN_1V8 SDIO_RST#_1V8
RESET_OUT#
SDIO_RST#_1V8
SDIO_CK_1V8SDIO_CMD_1V8
SDIO_WAKE#_1V8
SDIO_WAKE#_1V8SDIO_WAKE#PCIE_WAKE#
V_3V3
V_3V3
V_3V3 V_1V8 V_3V3 V_1V8
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
M2
STANDOFF
1
C16510nF
C163100nF
M.2 Slot 1 - SDIO Pinout
K ey E
PC
Ie0
SD
IO
I2C
I2S
UA
RT
CO
MM
PC
Ie1
UIM
X11
TE Connectivity 2199230-6
GND1
VCC_3P32
USB_D+3
VCC_3P34
USB_D-5
LED1#_3P3_OD6
GND7
PCM_CLK/I2S_SCK_1P88
SDIO_CLK_1P89
PCM_SYNC/I2S_WS_1P810
SDIO_CMD_1P811
PCM_OUT/I2S_SDO_1P814
SDIO_DAT0_1P813
PCM_IN/I2S_SDI_1P812
SDIO_DAT1_1P815
LED2#_3P3_OD16
SDIO_DAT2_1P817
GND18
SDIO_DAT3_1P819
UART_WAKE#_3P3_OD20
SDIO_WAKE#_1P8_OD21
UART_TXD_1P832
SDIO_RESET#_1P823
UART_RXD_1P822
GND33UART_RTS_1P8
36
PCIE_TX0+35
UART_CTS_1P834
PCIE_TX0-37
VENDOR_DEF138
GND39
VENDOR_DEF240
PCIE_RX0+41
VENDOR_DEF342
PCIE_RX0-43
COEX3_1P844
GND45
COEX2_1P846
PCIE_REFCLK+47
COEX1_1P848
PCIE_REFCLK-49
SUSCLK_3P350
GND51
PERST0#_3P352 CLKREQ0#_3P3_OD53
W_DISABLE2#_3P354
PEWAKE0#_3P3_OD55
W_DISABLE1#_3P356
GND57
I2C_DAT_1P8_OD58
RSVD/PCIE_RX1+65
I2C_CLK_1P8_OD60
RSVD/PCIE_RX1-67
ALERT#_1P8_OD62
GND63RSVD
64
RSVD/PCIE_TX1+59
UIM_SWP/PERST1#66
RSVD/PCIE_TX1-61
UIM_PWR_SNK/CLKREQ1#68
GND69
UIM_PWR_SRC/GPIO1/PEWAKE1#70
RSVD/PCIE_REFCLK1+71
VCC_3P372
RSVD/PCIE_REFCLK1-73
VCC_3P374
GND75
C162100nF
D9DLED0603RED
0402R160 0Ohm
0402R162 0Ohm
0402R158 220Ohm
D11
DBAT54
0402
R164
0Ohm
C169100nF
C16010uF
U1
NXP NTS0104GU12
VCCA1
A12
A23
A34
A45
VCCB11
B110
B29
B38
B47
OE12
GN
D6
FB15TDK ACM2012-900-2P-T002
1
4 3
2
0402R161 22Ohm
C167100nF
C166100nF
U2
NXP NTS0104GU12
VCCA1
A12
A23
A34
A45
VCCB11
B110
B29
B38
B47
OE12
GN
D6
0402R163 0Ohm
D10
DLED0603RED
C16410nF
0402R159 220Ohm
C16110uF
C168100nF
SMARC Design Guide 2.0 Page 86 of 119 Mar 23, 2017 ©SGeT e.V.
6 MEMORY CARD INTERFACES
6.1 SD Card
The SD (Secure Digital) Card is a non-volatile memory card format used as mass storage memory in portable devices. The SD standard is maintained by the SD Card Association. SMARC Modules support SD cards over the SMARC SDIO interface. The interface may be used in a 4 bit or 1 bit mode. If used in 1 bit mode, the least significant bit (SDIO0) should be used. Most SMARC Modules offer a SDIO BCT boot and an SDIO OS boot. Since SD cards can (usually) be inserted and removed by the user, it is important to implement ESD protection on all the SD lines.
Figure 58 Micro SD Card Implementation
GND
SDIO_PWR_EN
V_3V3_SDCARD
GND
GND
GND
GND
V_3V3_SDCARD
SDIO_WP
GND
C117
10u
6V
30402
GND
V_3V3
SDIO_D[0]
SDIO_D[2]
SDIO_D[3]
SDIO_CD#
SDIO_CMD
SDIO_CLK
SDIO_D[1]
J9
2
1P1
P2
J11
S1
S2
S4
S3
10
9
1
8
7
6
5 4
3
2CD/DAT3
CMD
V_VDDCLK
VSS
DAT0
DAT1
DAT2
DETECT_SWITCH
DETECT_LEVER
S3
S4
S2
S1
GNDR130
0R
1%
0402
GND
V_3V3
V_3V3
V_3V3
100n
C116
50V
0402
0402
1%
10k
R82
R136
4k7
1%
0402
DN
I
R137
4k7
1%
0402
DN
I
0402
16V
1u
C127
0402
50V
C108
100n
GND
0402
6V
3
10u
C361
GND
V_VCC IO1
IO2
IO3
IO42
5 1
3
4
6
SRV05-4SOT23-6
U70
GND
V_VCCIO1
IO2
IO3
IO42
51
3
4
6
SRV05-4SOT23-6
U71
GND GND
0402
50V
C121
100n
GND
IN
EN1
EN2
GND
OUT1
OUT2
OC2#
OC1#
GND_PAD
2
3
4
1
7
6
5
8
9
TPS2066
U4
GND
R440
10k
1%
0402
NC
NC
SDCARD_OC#
SDCARD_OC#R44110k1% 0402
V_3V3MTP23
R4401% 0402 R450
1% 0402R4601% 0402 R470
1% 0402R4801% 0402 R490
1% 0402
R4801% 0402
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
SMARC Design Guide 2.0 Page 87 of 119 Mar 23, 2017 ©SGeT e.V.
7 CAMERA INTERFACES
7.1 General
The SMARC specification allows for up to two serial (MIPI CSI) cameras to be interfaced to the SMARC Module. The defined CSI0 interface supports up to two differential data lanes (CSI0_D[0:1]+/- signals). CSI1 may be implemented with up to four differential data lanes (CSI1_D[0:3]+/- signals) to support higher resolution cameras. The Module camera interface is at CSI voltage levels.
7.2 Camera Data Interface Formats
There are a wide variety of data formats that are used to convey camera data to a host system. A complete description of these formats is very much beyond the scope of this design guide. Briefly stated, camera data formats may be divided into two groups: “raw” and “processed”. The raw camera data formats need to be adjusted for camera and sensor specific characteristics (non-linearities, sensor pixel quirks, color corrections and so on). Using the raw format requires an additional level of software complexity that is beyond many users. Unless you have a specific need for a particular camera that outputs “raw” sensor data, it is best to stick with cameras that include a processor on the camera module that convert the camera sensor data to a standard format such as RGB or YUV, JPEG or others. The “Bayer” format is one of the numerous raw formats that you may wish to avoid. A variation on the above is that some cameras offer “raw” RGB, meaning that the pixel data is sorted into RGB elements but sensor nonlinearities are not processed in the camera IC.
7.3 Camera Sensors and Camera Module Vendors
Table 12 Camera Sensors
Vendor Link
Aptina www.aptina.com
OmniVision www.ovt.com
Exmor
Table 13 Camera Module Vendors
Vendor Link
Leopard Imaging www.leopardimaging.com
KaiLap kailaptech.com
Chicony www.chicony.com.tw
Truly Opto www.trulyopto.com
Sunny Optical Technology www.sunnyoptical.com/en/
Sharp www.sharp-world.com
e-con Systems www.e-consystems.com/
7.4 Serial Camera Interface Example
The figure below illustrates a CSI implementation on a SMARC Carrier. The OV3640 is a 3.1 Mega-pixel CMOS sensor from OmniVision which supports both serial and parallel camera interfaces. Here, the
SMARC Design Guide 2.0 Page 88 of 119 Mar 23, 2017 ©SGeT e.V.
output of the sensor is connected to CSI0 interface of the SMARC Module. I2C_CAM is the control interface used for configuring the sensor. CAM_MCK is the master clock output from the SMARC Module.
Figure 59 Serial Camera Implementation
CSI0_D0_P
CSI0_D0_N
CSI0_D1_P
CSI0_D1_N
CSI0_CK_P
CSI0_CK_N
MIPI CSI
XVCLK
SDA
SCLI2C_CAM_CK
CAM_MCK
I2C_CAM_DAT
GPIO0/CAM0_PWR PWDN
MIPI (2 Lanes)
SM
AR
C M
OD
UL
E
OV
36
40
GPIO2/CAM0_RST RESET_B
1.5V
2.8V
1.8V
7.5 Other Camera Options
SMARC systems have the option of using the dedicated SMARC camera interface pin set. For a dedicated system produced in high volume, this is likely to be the most cost effective option. However, other options exist. USB cameras are becoming very popular. They enjoy good software support and are becoming more and more cost effective as time passes. However, the bandwidth of a HS USB interface (480 Mbps) is less than what is possible with the SMARC CSI camera interfaces.
SMARC Design Guide 2.0 Page 89 of 119 Mar 23, 2017 ©SGeT e.V.
8 GPIO
8.1 SMARC Module Native GPIO
SMARC Modules support twelve general purpose I/O pins: GPIO0 to GPIO11. Each of these can be configured as an input or output pin. The SMARC specification recommends the use of GPIO0 to GPIO5 as outputs and the use of GPIO6 to GPIO11, as inputs. SMARC Modules support five dedicated GPIOs (GPIO7 to GPIO11). The other seven GPIOs are multiplexed pins supporting functions like Camera Power Enable, Camera Reset, Tachometer input, PWM output etc. SMARC Modules generally allow the GPIO to be configured to generate an interrupt. SMARC Modules use a GPIO voltage level of 1.8V.
8.2 GPIO Expansion
For a low cost, easy way to implement additional GPIO ports, see Section 4.2.5 I2C Based I/O Expanders.
SMARC Design Guide 2.0 Page 90 of 119 Mar 23, 2017 ©SGeT e.V.
9 CARRIER POWER CIRCUITS
9.1 Power Budgeting
One of the early steps in a SMARC Carrier design is to develop a power budget and a strategy for meeting that budget. All the power rails need to be identified and worst-case current consumptions listed. A spread-sheet is usually developed. The power circuits should be designed to meet the worst case numbers, but the actual system power consumption will usually turn out to be quite a bit less than the total indicated by the total worst case numbers for each individual rail. Once there is an understanding of the amount of power required, a plan can be developed for meeting the requirements. A sample power budget sheet is shown in the table below. This example is hypothetical and serves to illustrate the process. This example assumes that the SMARC Module is to be supplied by a fixed 5V DC source. A variable battery power source would result in a different sheet.
Table 14 Hypothetical Power Budget Example – Part 1
12V Current
5V Current
3.3V Current
1.8V Current
1.5V Current
Power Notes
Display Backlight 0.6A 7.2W
USB 2.0A 10.0W 4 devices
USB 3.0 1.8A 9.0W 1 device
SMARC Module 1.2A 6.0W
Mini PCIe Module 1.0A 1.0A 4.8W
Audio Circuits 0.5A 0.1A 2.7W
Misc. Carrier Circuits 0.5A 0.2A 2.0W
Current Subtotals 0.6A 5.5A 1.5A 0.3A 1.0A
Power Totals 7.2W 27.5W 5.0W 0.5W 1.5W 41.7W
The total shown is a worst case value, and power circuits should be designed to handle the worst case. However, experience shows that typical average system power consumptions are significantly less, on the order of 50% of worst case. The total above does not account for power conversion losses. These are added in a later section, when this hypothetical example is continued. Many SMARC Module vendors offer evaluation platforms, and it is worth the time and effort to roughly prototype the target system with available hardware and software. This can validate power estimates and have other benefits, such as allowing performance benchmarks to be carried out before committing to the full system design.
SMARC Design Guide 2.0 Page 91 of 119 Mar 23, 2017 ©SGeT e.V.
9.2 Input Power Sources
Table 15 Input Power Source Possibilities
Power Source Voltage Notes
3.3V Fixed 3.3V +/- 5% Possible, but not a common choice, as often there are significant power requirements for USB (5V at up to 500 mA for each external USB 2.0 port) and the display backlight supply (12V at up to 600 mA is common), requiring up (boost) conversion. Some SMARC Modules may not support 3.3V power input.
5V Fixed 5.0V +/- 5% Common choice – allows some of the higher power consuming devices (USB, SMARC Module) to be fed directly without conversion. Other, lower current devices require power conversion.
12V Fixed 12V +/- 5% Allows display backlight to be powered directly, without conversion (if the display backlight accepts 12V). Requires buck conversion of 12V to 5V for Module and for Carrier USB and other functions.
Power “Brick” Various ranges available 6V, 9V, 12V, 14V
Various output levels are available. The voltage regulation from a power brick is often not good, and it is best not to rely on the brick output to feed any circuit that needs to be supplied with a voltage regulated over a relatively tight range. Usually the brick output voltage is down converted and regulated on a Carrier board design.
Battery - Single Level Lithium Ion Cell
3.6V nominal 4.2V fully charged; 3.0V discharged. Most SMARC Modules operate directly from this range (check with your vendor).
Battery – Two Level Lithium Ion Cells
7.2V nominal 8.4V fully charged; 6.0V discharged
Battery – Three Level Lithium Ion Cells
10.8V nominal 12.6V fully charged; 9.0V discharged
Wide Range DC 10V – 30V (Typical)
Wide range input power supply is possible. Note that to handle higher voltages, parts rated for use at the higher voltages must be used.
Power Over Ethernet
48V IEEE802.3af POE standard allows 12.5W load power IEEE802.3at POE standard allows 25.5W load power The POE supply output is transformer isolated from the GBE lines, with 1500V DC isolation. POE supply output voltages are design specific – 24V, 12V and 5V outputs are common.
Automotive 12V nominal
When the engine is off, the supply battery voltage is 12V nominal. During engine cranking, the supply can dip to 6V. When the engine is running, the DC level can be up to about 16V, with a 14.4V level being typical. Transients in excess of +/- 100V are common. A user may disconnect the battery and reconnect it with the polarity reversed. All in all, it’s a harsh environment that needs careful attention. A basic strategy is to have an input network with good transient and reverse polarity protection, and then use a rugged switching supply that can handle an input range from 6V to 24V, and deliver a 5V output to the SMARC Carrier.
SMARC Design Guide 2.0 Page 92 of 119 Mar 23, 2017 ©SGeT e.V.
9.3 Power Budgeting, Continued – Fixed 5V Power Source
Once a power budget is in hand, a power architecture can be developed. Let’s assume that the input power source is to be 5V fixed, and the power budget per voltage rail is as per the hypothetical example given in Table 14 Hypothetical Power Budget Example above. Next, one has to decide how to realize the various power rails. Here we assume that switch mode power converters are used to create all rails from the 5V source. The efficiency (or inefficiency) of the power converters must be accounted for, as shown in the following table.
Table 16 Hypothetical Power Budget Example – Part 2
Voltage Rail
Current
Power Derived From
Efficiency Assumption
Power From 5V Input
Current From 5V input rail
12V 0.6A 7.2W 5V (Boost) 90% 8W
5V 5.5A 27.5W 100% 27.5W
3.3V 1.5A 5.0W 5V (Buck) 90% 5.6W
1.8V 0.3A 0.5W 5V (Buck) 90% 0.6W
1.5V 1A 1.5W 5V (Buck) 90% 1.7W
Total 43.4W 8.7A
Other factors can make the process a bit more complex than this example. If some power rails are to be created with linear supplies from a higher voltage rail, for example, then the entire current used by the lower rail needs to be added to the current budget of the higher voltage source rail. If the primary source rail varies (such as from a battery) the extremes of the source rail must be taken into account.
SMARC Design Guide 2.0 Page 93 of 119 Mar 23, 2017 ©SGeT e.V.
9.4 Fixed 5V DC Power Input Circuit Example
The power entry connector for this fixed 5V power source example is shown in the figure immediately below. There are two paths, given net names V_MOD_IN and V_CARRIER_IN. Both carry 5V in from a single bench supply. The nets are separated to allow separate current (and power) measurements of the SMARC Module and the Carrier board. If this separate measurement capability is not needed, then the separate entries could be combined into a single net.
Figure 60 5V Input Connector
The following figure illustrates a power switch used to hold off most Carrier board circuits from being powered until the Module asserts the “CARRIER_PWR_ON” signal. Some Carrier circuits, such as those involved in power management and those that are in the “Module Power Domain” as defined by the SMARC specification, may be powered whenever the Module has power, before (and after) the assertions of CARRIER_PWR_ON.
Figure 61 5V Carrier Power Switch
25V
C301100nF
2
1C34722uF25V
2
1
4/1/1x4/4.2THT
J52Molex 39303045
4
3
2
11
2
3
4
V_CARRIER_IN
10V
C357
100uF
2
1
25V
C34822uF
2
1
25V
C302100nF
2
1
V_MOD_IN
100uFC358
10V2
1
4 Pin, 0.4mm Pitch, TH
16V1uF
C363
2
1 C3641uF16V
2
1
V_5V0
100nF25V
C361
2
1C362
25V100nF
2
1
50V220pF
C365
21
TI TPS22965
U54
SON8
9
5
8
7
6
3
2
1
4VBIAS
VIN_1
VIN_2
ON
CT
VOUT_7
VOUT_8
GND
T_PAD
V_CARRIER_IN
MODCARRIER_PWR_ON
Note:Rise Time = 475 us
SMARC Design Guide 2.0 Page 94 of 119 Mar 23, 2017 ©SGeT e.V.
The following three figures illustrate buck (or step-down) switching converters that create 3.3V, 1.8V and 1.5V from the V_CARRIER_IN 5V power source. Since the power needs on these rails are modest, integrated switchers with internal power FETs are well suited to the job. They are physically small and robust. The parts shown are from Texas Instruments, although similar parts exist from other vendors. The figures show three separate enables for the three supplies, with net name designations V_3V3_EN, V_1V8_EN and V_1V5_EN. Sources for these nets are not shown. These enable pins should be driven to the “enabled” state when signal CARRIER_PWR_ON is high. They could be driven by CARRIER_PWR_ON, or by V_5V0, or by other Carrier circuitry. If the situation demands aggressive power management, it may be desirable to have Carrier I/O circuits that allow the various enables to be brought low if the power rail is not needed. If this is done, the designer should arrange that the enables do not go high before CARRIER_PWR_ON is high. The LEDs and signal FETs on the right side of the three figures are optional. The LED lights up as a status indicator when the power rail (V_3V3, V_1V8 or V_1V5) is up. The FET prevents leakage from the main power rails (V_MOD_IN and V_CARRIER_IN) when the switchers are powered down. Rail V_MOD_IN_LED ties to V_MOD_IN through a removable jumper. Removing the jumper prevents the LEDs from burning power in standby states (and in all states).
Figure 62 3.3V 2A Buck Converter
Figure 63 1.8V Buck Converter
V_MOD_IN_LED
ROHM RJU003N03T106
UMT3
Q22
3
1
2
V_CARRIER_IN
16V10uFC320
2
1
16V10uFC321
2
1
16V10uFC322
2
1
100Ohm 0402R352
21
LT
ST-C
190K
GK
T
D30
12
16V10uFC323
2
1
16V10uFC324
2
1
TI TPS63020U48
15
14
3
5
4
7
6
2
13
1
11
10
9
8
12EN
L1_8
L1_9
VIN_10
VIN_11
VINA
PS/SYNC
GND
L2_6
L2_7
VOUT_4
VOUT_5
FB
PG
PGND
1.5uH4.4A
L18 21
25V100nF
C299
2
1
562KOhm
0603 R362
21
100KOhm0402 R349
21
NXP 1N4148
D35
C A
25V100nFC300
2
1
V_3V3
0402
10KOhmR344
21
LED_3V3
PG_3V3
BUCKBOOST_3V3_SYS_L1 BUCKBOOST_3V3_SYS_L2
VINA_3V3SYS_BUCK
DIO_3V3_SYS
DIO_3V3_SYS_RC
V_3V3_EN
Vih >= 1.2VVil <= 0.4V
V_MOD_IN_LED
C32510uF16V 2
1
C32622uF6.3V
2
1
50V
C35233pF
2
1
50V100pFC337
2
1
21
0402 R363
604KOhm
232KOhm0402 R364
21
L19
3A10uH
21
V_1V8
SON10
U49
TI TPS62020
11
9
10
5
7
8
4
6
1
3
2VIN_2
VIN_3
EN
MODE
GND
SW_8
SW_7
FB
PGND_10
PGND_9
TH_PAD
LT
ST-C
190K
GK
T
D31
12
100Ohm 0402R353
21
ROHM RJU003N03T106UMT3
Q28
3
1
2
V_CARRIER_IN
GND
LED_1V8
V_1V8_EN
V_1V8_SW
FB_TPS62020
SMARC Design Guide 2.0 Page 95 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 64 1.5V Buck Converter
Many LCD backlights require a 12V power source. If the system power source is a fixed 5V supply, or a battery supply well under 12V, then a boost converter circuit is needed. An example is shown here:
Figure 65 12V Boost Converter for Backlight Power
V_MOD_IN_LED
100Ohm 0402R350
21
LT
ST-C
190K
GK
T
D28
12
L16
9.6A1uH
21
25V100nFC295
2
1
R356
0402
2.67KOhm
21
V_1V5
100pF
C336
2
1
20Ohm0402R355
2 1
50V2.2nF
C34021
R357
0402
4.02KOhm
21
R359
0402
57.6KOhm
21
0402
4.02KOhm
R358
21
100nF25V
C296
2
1
50V2.2nF
C341
21
16V1uFC312
2
1
22uF25V
C342
2
1
25V22uFC343
2
1
25V22uFC344
2
1
25V22uFC345
2
1
22uF25V
C346
2
1
V_3V3
TI TPS53310
U46
QFN16
9
10
3
4
7
6
5
17
16
15
11
12
8
2
1
14
13VIN_13
VIN_14
EN
SYNC
PS
VDD
AGND
PGND_15
PGND_16
TH_PAD
SW_5
SW_6
SW_7
VBST
PGD
FB
COMP
V_CARRIER_IN
ROHM RJU003N03T106UMT3
Q20
3
1
2
LED_1V5
TPS53310_FB
V_1V5_EN
PS_R
PG_1V5
TPS53310_COMP
V_1V5_SW
V_CARRIER_IN
0402
0Ohm
R335
21
DNI0Ohm
R336
0402
21
C3562.7nF50V2
1
TI TPS61087DRC
U51
VSON10
11
10
1
2
7
6
5
4
9
8
3 EN
IN
FREQ
AGND
PGND
SW_6
SW_7
FB
COMP
SS
THERM_PAD
0402
154KOhmR368
21
L21
6.8uH
21
DNI 0402R337
0Ohm
21
R338
0Ohm0402
21
R369
040233.2KOhm
21
25V
C3321uF
2
1C349
25V22uF
2
1
0402 R370
17.8KOhm
21
V_CARRIER_IN
100nF25V
C306
2
1
C327
25V10uF
2
1C32810uF25V
2
1
10uFC329
25V2
1C33010uF25V
2
1
V_12V0
Vishay SS23-E3/52T
D38
12
V_12V_FREQ
V_12V_EN
V_12V_FB
TPS61087_COMP
TPS61087_SS
V_12V_SW
SMARC Design Guide 2.0 Page 96 of 119 Mar 23, 2017 ©SGeT e.V.
9.5 Power Hot Swap Controller
Hot swap controller circuits can be used to control the system power supply rise time. This may be desirable when plugging circuits in live to low impedance sources, such as a battery. The figure below illustrates a high-side protection controller circuit using TI LM5060. The N-Channel MOSFET isolates the input supply (V_BRD_IN) from rest of the board (V_HTSWP_OUT). The circuit limits the in-rush current and provides a power good signal once the output voltage reaches the input voltage. An option is provided to enable LM5060 (HTSWAP_EN) from a CPLD as well as using a switch / jumper.
Figure 66 Hot Swap Controller
V_BRD_IN
E-Switch 400MSP1R1BLKM7QESW4
2
3
1
SC70
TI SN74AHC1G00U52
3
5
4
2
1
TI LM5060
U53
MSOP10
6
7
8
9
10
5
3
4
2
1SENSE
VIN
UVLO
OVP
EN
GATE
OUT
nPGD
TIMER
GND
R371
0402
3.6KOhm
21
Q27
D S
G
10Ohm 0402R372
21
6.8KOhm
0402 R373
21
10nF50VDNI
C359
2
1
C36068nF16V 2
1
V_HTSWP_OUT
R3
39
0O
hm
0402
21
R374
0402
7.5KOhm
21
50V
C335100nF
2
1
V_BRD_IN
R375
0402
49.9KOhm
21
10K
Ohm
0402
21
R348
V_3V3_PWRUP
V_3V3_PWRUP
R354
04021KOhm
2 1
0402R340 0Ohm
21
FCI 77311-118-02LF
J50
2/1x2/2.54ST
2
11
2
0402
DNI0OhmR341
21D40
12
C307100nF25V
2
1
C308100nF
25V 2
1
R37647KOhm 0
603
21
R37747KOhm 0
603
21
100nF25V
C309
2
1
V_3V3_PWRUP
100nFC310
25V2
1
100nF50V
C479
2
1
V_3V3_PWRUP
C478
25V22uF
2
1
TI LM9036
U76
SOIC8
7
6
5
1
3
2
4
8VIN
NC_4
GND_2
GND_3
VOUT
NC_5
GND_6
GND_7
D39
12
HTSWP_PGD#
HTSWP_EN
PWR_SWITCH_STATE
HTSWP_EN_HOLD#
3V3 Power Up Supply
UVLO : @ 9.3VOVP : @ 33.5 V
SUM40N10-30-E3Vishay/Siliconix
Note :
SMARC Design Guide 2.0 Page 97 of 119 Mar 23, 2017 ©SGeT e.V.
9.6 High Voltage LED Supply
Some LCD panels have multiple sets of series LED strings that are to be driven by a high voltage LED supply. Vendors such as TI and Analog Devices provide the ICs for these supplies. A schematic example using a TI / National high voltage LED supply is given below. The LED brightness can be controlled either using PWM control (if the IC VDDIO pin is set LOW) or by I2C (if VDDIO is HIGH). A level translator needs to be used for signals VSYNC and PWM.
Figure 67 LP8545 LED Backlight Power
ROHM RJU003N03T106
Q23
3
1
2
0Ohm0402
R329
2 10Ohm
0402R330
2 1
21L20
15uH
31.6KOhm
0402R365
21
04
02
10KOhmR345
21
C303100nF25V
2
1
0402 R346
10KOhm
21
V_1V8
V_CARRIER_IN
25V
C304100nF
2
1
0402
10KOhmR347
DNI
21
MOD
V_3V3
0402
R3310Ohm
21
V_1V8
V_31V9_BKLT
MOD10uFC353
50V2
1
U45
TI SN74AVC2T244DQ
1
2 7
6
54
8
3 A2
VCCB
OE# GND
B2
B1A1
VCCA
V_1V8
Vishay SI2305CDS-T1-GE3
Q26
3
2
1
DNIR3320Ohm 210OhmR333DNI
21
C354
10uF50V
21
1uF25V
C331
2
1
10uF50V
C355
2
1
0402
0Ohm
R33421
V_1V8
DiodesInc DFLS230L
D37
CA
50V
C338100pF
2
1
50V
C339100pF
2
1
0603R366
120KOhm
21
25V100nF
C30521
16V1uF
C31321
1KOhm 0402R327
21
R367
0402
470KOhm
21
V_5V0U50National LP8545
25
1
9
15
7
6
22
18
17
16
14
13
12
4
2
11
10
5
3
20
19
8
23
24
21FB
SW
VIN
VDDIO
VSYNC
FILTER
ISET
FSET
SCLK
SDA
PWM
EN
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
VLDO
GD
FAULT
GND_L
GND_S
GND_SW
TH_PAD
I2C_GP_DAT
I2C_GP_CK
LCD_BKLT_EN
LCD_VS
LCD_BKLT_PWM
LCD_VS_3V3
LCD_BKLT_PWM_3V3
BKLT_I2C_SDA_R
BKLT_REF_SEL
BKLT_REF
BUFFER5_OE#
LCD_CA6
LCD_CA5
LCD_CA4
LCD_CA3
BKLT_SW
FSET
LCD_CA2
LCD_CA1
VSYNC
FILTER
BKLT_I2C_SCL_R
ISET
(7-bit format)I2C Address : 0x2C
1 I2C
0 PWM
Logic State Function
Optional
1.25MHz,100mA@33V
SMARC Design Guide 2.0 Page 98 of 119 Mar 23, 2017 ©SGeT e.V.
9.7 3.0V to 5.25V Power Input Example
The circuits shown below illustrate buck-boost switching converters that generate 5V and 3.3V from the V_CARRIER_IN power source (3.0V to 5.25V). Since the power needs on these rails are modest, integrated switchers with internal power FETs are well suited to the job. They are physically small and robust. The parts shown are from Texas Instruments, although similar parts exist from other vendors. The figures show separate enables for the 5V and the 3.3V supplies, with net name designations V_5V0_EN and V_3V3_EN. Sources for these nets are not shown. These enable pins should be driven to the “enabled” state when signal CARRIER_PWR_ON is high. They could be driven by CARRIER_PWR_ON, or by V_CARRIER_IN, or by other Carrier circuitry. If the situation demands aggressive power management, it may be desirable to have Carrier I/O circuits that allow the various enables to be brought low if the power rail is not needed. If this is done, the designer should ensure that the enables do not go high before CARRIER_PWR_ON is high.
Figure 68 5V, 2A Buck-Boost Converter
Figure 69 3.3V 2A Buck-Boost Converter
V_MOD_IN_LED
3
1
2
ROHM RJU003N03T106UMT3
Q21
V_CARRIER_IN
C297
25V100nF
2
1C31410uF16V2
1C31510uF16V2
1C31610uF16V2
1C31710uF16V2
1
L17
8.4A3.3uH
21
R360
0402
1.82MEGOhm
21
R343
0402
10KOhm
21
V_5V0
TI TPS63020U47
15
14
3
5
4
7
6
2
13
1
11
10
9
8
12EN
L1_8
L1_9
VIN_10
VIN_11
VINA
PS/SYNC
GND
L2_6
L2_7
VOUT_4
VOUT_5
FB
PG
PGND
D36
NXP 1N4148
C A
R361
0402
200KOhm
21
C298
25V100nF
2
1
C31810uF16V2
1
R328
0402
0OhmDNI
21
C31910uF16V2
1
100Ohm 0402R351
21
LT
ST-C
190K
GK
T
D29
12
LED_5V0V_5V0_EN
DIO_5V0_SYS
DIO_5V0_SYS_RC
BUCKBOOST_5V0_SYS_L2
PG_5V0
BUCKBOOST_5V0_SYS_L1
VINA_5V0_SYS_BUCK
V_MOD_IN_LED
ROHM RJU003N03T106
UMT3
Q22
3
1
2
V_CARRIER_IN
16V10uFC320
2
1
16V10uFC321
2
1
16V10uFC322
2
1
100Ohm 0402R352
21
LT
ST-C
190K
GK
T
D30
12
16V10uFC323
2
1
16V10uFC324
2
1
TI TPS63020U48
15
14
3
5
4
7
6
2
13
1
11
10
9
8
12EN
L1_8
L1_9
VIN_10
VIN_11
VINA
PS/SYNC
GND
L2_6
L2_7
VOUT_4
VOUT_5
FB
PG
PGND
1.5uH4.4A
L18 21
25V100nF
C299
2
1
562KOhm
0603 R362
21
100KOhm0402 R349
21
NXP 1N4148
D35
C A
25V100nFC300
2
1
V_3V3
0402
10KOhmR344
21
LED_3V3
PG_3V3
BUCKBOOST_3V3_SYS_L1 BUCKBOOST_3V3_SYS_L2
VINA_3V3SYS_BUCK
DIO_3V3_SYS
DIO_3V3_SYS_RC
V_3V3_EN
Vih >= 1.2VVil <= 0.4V
SMARC Design Guide 2.0 Page 99 of 119 Mar 23, 2017 ©SGeT e.V.
9.8 12V Input
There are many choices for switching power supply circuits to step a 12V input down to lower voltages for SMARC use. An integrated switcher possibility from TI is shown in the following figure.
Figure 70 12V Step Down Switcher
100KOhm0402 R570
21
25V
C579100nF
21
50V
C5841nF
2
1
1.5KOhm
R583
040221
6.8uH13.5A
L2421
R582
3.01Ohm
0402
DNI
21
25V100uFC583
2
1
100uF
2
1
25V
C582
25V100uFC581
2
1
25V
C580100uF
2
1
71.5KOhm0402
R581
21
71KOhm0402
R580
21
10KOhm0402 R579
21
R57810KOhm0
402
21
V_12V0
TI TPS53318U81
QFN22
23
11
10
9
8
7
6
3
18
17
16
15
14
13
12
5
1
4
2
22
21
20
19VDD
MODE
TRIP
RF
EN
VBST
VFB
ROVP
VIN_12
VIN_13
VIN_14
VIN_15
VIN_16
VIN_17
VREG
PGOOD
LL_6
LL_7
LL_8
LL_9
LL_10
LL_11
GND
0402
0Ohm
R573
2 1
R577 619KOhm0402
21
0402200KOhmR575 21
R574 DNI0402
200KOhm
21
21 0402DNIR572
0Ohm
C576
16V1uF
2
1
4.7uF25V
C570
2
1
C578
25V100nF
21
470pF
DNI
C577
50V
2
1
0402
1uFC575
16V
2
1
V_12V0
0402 R571
100KOhm
21
C574
25V
22uF
2
1 C573
25V
22uF
2
1
22uF
25V
C572
2
1
22uF
C571
25V2
1
V_12V0
V_5V0
R5760402
210KOhm21
LL_5V_REG
FB_5V_REG
ROVP_5V_REG
PG_SWITCHER
LL_5V_REG_R2
LL_5V_REG_R1
RF_5V_REG
TRIP_5V_REG
MODE_5V_REG
VREG_5V_REG
VBST_5V_REG VBST_5V_REG_C
SMARC Design Guide 2.0 Page 100 of 119 Mar 23, 2017 ©SGeT e.V.
9.9 Wide Range Power Input
In some applications it is desirable to allow for a wide range power input. This is the case in certain industrial and automotive settings. Since SMARC systems operate at low voltages (5V and under, apart from LCD backlight considerations), it is straightforward to implement a wide range buck converter. The figure below shows an example implemented with the Linear Technologies LTC3879. Similar parts are available from other vendors. The Texas Instruments TPS40170 is another part to consider for this application. The TPS40170 allowable input range spans 4.5V to 60V. If you are targeting the higher input ranges, be sure that components exposed to the input voltage are adequately rated for that high voltage.
Figure 71 Wide Range Power Input Switcher
If the load on the Carrier 3.3V is high, it may be worth having a second wide input range switcher per the above figure, configured for the 3.3V output.
9.10 Power Monitoring
The SMARC specification document defines a VIN_PWR_BAD# input. Its use is optional. If VIN_PWR_BAD# is held low by a Carrier or power supply circuit, the Module assumes that the source power is not ready and does not boot. VIN_PWR_BAD# is typically generated by a power monitor / reset generator IC, such as those shown in the figure below. This figure shows two of them, although this is not really necessary if the Module and the Carrier circuits are powered by a single source and you don’t want to keep them separate.
V_IN_10-30V
V_IN_10-30V
V_IN_10-30V
C538
4.7uF50V
2
1
10KOhm
R524
0402
2
1
0402 R552
40.2KOhm
2
1
D553
1
C539
50V4.7uF
2
1
50V
C540
4.7uF
2
1
0402
210KOhmR553
2
1
C541
50V4.7uF
2
1
4.7uH
L22
17A
21
LFPAK
Renesas RJK0451DPBQ48
123
5
4
R556
DNI
0402
20KOhm
2
1
20KOhm
R558
04022 1
50V820pFC547
2
1
22uFC549
50V2
1
Renesas RJK0451DPB
Q51
LFPAK
123
5
4
1210
1OhmR560
21
D57
CA
0Ohm0402
R530
21
47pF50V
C556
2
1
10V47uFC557
2
1 C55847uF10V
2
1
47uFC559
10V2
1
1.5KOhm
R562
0402
2
1
25V
C562220nF
2
1
R549
0402
1.82MEGOhm
21
0402R519
100KOhm2 1
C504100nF50V
2
1
V_INTVCC_5V0
V_INTVCC_5V0
10V
C5644.7uF
2
1
C505100nF
50V 2
1
R564
0402
2.2Ohm
21
V_5V0
47uFC560
10V2
1
C522
100nF
21
LT LTC3879
QFN161053-6883
U80
17 13
2
8
16
15
14
12
11
9
6
3
5
4
1
7
10VIN
ION
TRACK/SS
MODE
ITH
VRNG
SGND
RUN
INTVCC
BG
SW
TG
BOOST
VFB
PGOOD
PGNDTH_PAD
47uF
DNI
C561
10V2
1
COG50V
22pFC566
2
1
11KOhm 0402R567
2
1
Note :Route the VFB line away from noise sources,such as the inductor or the SW line.
Note:Place CIN, COUT,MOSFETs,DBand inductor all in one compact area.
SMARC Design Guide 2.0 Page 101 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 72 Power Monitor - Incoming Power
60.4KOhm 0603
R456
21
47KOhm 0603
R455
21
U68
SC70-5
2
1
3
5
4VDD
SENSE
RESET
NC
GND
TPS3803-01
SC70-5
U69
2
1
3
5
4VDD
SENSE
RESET
NC
GND
TPS3803-01
DNI4.7KOhm
0402 R453
21
R4514.7KOhmDNI0
402
21
0603
R45060.4KOhm
21
04020Ohm
R454
2 1
0Ohm
R4520402
2 1
C451100nF25V2
1
25V100nFC450
2
1
V_CARRIER_IN
V_MOD_IN
V_MOD_IN
V_MOD_IN
R457
0603
47KOhm
21
VIN_PWR_BAD
V_CARRIER_SNS
V_MOD_SNS
V_3V0-5V25_PG
V_5V0_DCIN_PG
SMARC Design Guide 2.0 Page 102 of 119 Mar 23, 2017 ©SGeT e.V.
9.11 Power Over Ethernet
Power may be delivered to a SMARC system over the Gigabit Ethernet cabling, cohabiting with the GBE data traffic. The 48V DC power is extracted from the isolated GBE cabling by a diode bridge and a specialized transformer isolated switching power supply. POE is defined by the IEEE 802.3af and IEEE 802.3at standards. The 802.3af payload power is limited to 12.5W and the 802.3at to 25.5W. Many semiconductor vendors offer POE solutions. Designing a POE power supply is a little trickier than designing your average switching supply, as the POE supply is transformer coupled, there are isolation requirements to meet, and some sort of DC isolated feedback mechanism must be incorporated. If your product volume is high, it may be worth the trouble of implementing your own Carrier-down circuit. See Texas Instruments and Micro-Semi for POE IC solutions. Even if you don’t go for the do-it-yourself approach, there are some very instructive Application Notes available from these vendors In many cases it is more straightforward to make use of a POE module, available from various vendors. One attractive POE module line comes from Silver Telecom (www.silvertel.com). IEEE 802.at compliant modules with output voltage options of 24V, 12V or 5V are available. The sample circuit below uses a Silvertel module with a 12V output. The 12V output cannot be fed directly to a SMARC Module – a step down converter would be needed. However, many SMARC systems incorporate LCD displays that utilize 12V backlights – hence the POE output option of 12V may make sense. If not, then the 5V POE output option could be considered (and the 5V POE module output can be fed directly to the SMARC Module). Note that for POE use, a particular type of GBE jack is required, to get access to the DC power coming in over the isolated GBE lines. The example shown here uses a Pulse Electronics JXK0-0190NL GBE POE Mag-Jack. Similar parts are available from Bel-Fuse, Tyco and others – but beware of differing PCB footprints.
SMARC Design Guide 2.0 Page 103 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 73 GbE with PoE
U58
FAIRCHILD NC7SZ125
SOIC8
GND
IN
OE#
VCC
OUT
V_3V3
D13
Comchip CDBHD2100-G
4
3
2
1
+
-
AC
AC
C2411mFAL12.5x13.52
1
Littelfuse SMAJ58CAD15
Comchip CDBHD2100-G
D14
4
3
2
1
+
-
AC
AC
V_12V0
R273
150O
hm
0402
21
MODR97
0402
0Ohm
21
Silvertel AG9330
PS1
8
5
14
13
10
12
11
9
7
6
4
3
2
1AUX1-
AUX1+
VIN+
NC
VIN-
AUX_DC_7-
-VDC_9
ADJ
+VDC_12
-VDC_10
+VDC_13
AUX_DC+
AT-DET
AUX_DC_8-
Sharp PC817X1NIP0F
U23
PDIP4
3
4
2
1
MOD
0402
R271
1KOhm
21
25V
C34
100nF
2
1
C35
100nF
25V2
1
V_3V3
R272
0402
1KOhm
21
MOD 0402R27468Ohm 21
25V
C36
100nF
2
1
V_3V3
25V
C37
100nF
2
1
25V
C38
100nF
2
1
25V
C39
100nF
2
1
25V
100nFC40
2
1
1uFC157
16V 2
1
MOD
68Ohm
R275
040221
V_3V3
MOD
MOD
MOD
MOD
MOD
MOD
MOD
Pulse JXK0-0190NL
J28
RA20/1PORT
22
2115
16
20
19
18
17
9
7
8
2
1
3
5
6
4
10
12
11
14
13GREEN_A
GREEN_K
MD1+
MDCT1
MD1-
MD2+
MDCT2
MD2-
MD3+
MDCT3
MD3-
MD4+
MDCT4
MD4-
VDC1+
VDC1-
VDC2+
VDC2-
DLED_16
DLED_15 SHIELD_21
SHIELD_22
MOD
MOD
SOIC8
U57
FAIRCHILD NC7SZ125
GND
IN
OE#
VCC
OUT
GBE_MDI3_P
GBE_MDI0_P
GBE_MDI0_N
GBE_MDI1_N
GBE_MDI1_P
GBE_MDI2_N
GBE_MDI2_P
GBE_MDI3_N
GPIO11
V_POE2_N
V_POE2_N
V_POE2_P
V_POE2_P
V_POE1_N
V_POE1_N
V_POE1_P
V_POE1_P
T2P_CLASSIFICATION#
V_POE_IN_P
V_POE_IN_N
GBE_CTREF
GBE_LINK1000_BUF_R#
GBE_LINK_ACT#
GBE_LINK100_BUF#
GBE_LINK1000_BUF#
GBE_LINK_ACT_R#
GBE_LINK100#
GBE_LINK1000#
RJ45 with Magnetics/POE, R/A, TH
SMARC Design Guide 2.0 Page 104 of 119 Mar 23, 2017 ©SGeT e.V.
9.12 Li-ION Battery Charger
9.12.1 General
Caution: improper battery charging can be a serious safety hazard. This section serves as a brief introduction to what is involved in designing a battery management system, but it is not enough to go on. Other source materials, from IC companies, battery vendors and the technical literature will be necessary for you to implement a safe and effective system. Lithium Ion batteries have a fully charged cell voltage of 4.2V, nominal cell voltage level of 3.7V, and a depleted voltage of 3.0V. They are used in series combinations and parallel combinations. The voltages for various series combinations are shown in the following table.
Table 17 Lithium- Ion Battery Cell Voltages
Series Cells Nominal Voltage Fully Charged Fully Depleted
1 3.7V 4.2V 3.0V
2 7.4V 8.4V 6.0V
3 11.1V 12.6V 9.0V
4 14.8V 16.8V 12.0V
Battery capacities are measured in Ampere-Hours (Ah). A fully charged battery with a 2Ah capacity can deliver 2A for 1 hour, or 1A for 2 hours and so on. The capacity is sometimes designated ‘C’ in battery data sheets. Lithium-ion batteries are typically charged in two phases: a constant current portion (for the deeply depleted battery) and a constant voltage portion (when the charging process nears completion). The constant current charging is typically done at a maximum constant current equal to the battery capacity – for example, a 2Ah battery is charged at a maximum charging current of 2A. The constant voltage portion is done at the cell fully charged voltage – 4.2V for a single series cell, 8.4V for two series cells, and so on. The battery data sheet and vendor’s application notes should of course be consulted for more specific recommendations that apply to the situation at hand. The battery temperature should be monitored during charging and use. The charging is disabled if the battery temperature exceeds a threshold set by the battery charger implementation.
SMARC Design Guide 2.0 Page 105 of 119 Mar 23, 2017 ©SGeT e.V.
9.12.2 Battery Charger Circuit Example
A battery charger implementation is shown in the following four figures. This example uses Texas Instruments parts. Similar devices are available from Linear Technology, Maxim integrated, Analog Devices and others. The first of the four figures shows the overall charging system in block diagram format. The actual circuit schematics are shown in the three subsequent figures. Caution: many of the component values shown here need to be adjusted to suit the details of the situation at hand – the number of series cells, the battery capacity, the battery thermistor particulars. With reference to the following four figures:
FETs Q40 and Q46 form an analog switch that the charger IC can use to gate power from the external DC adapter into the system. Charger current is sensed through RS1. The FETs are turned off if the charger voltage is too high, too low or if the current draw is excessive.
FET Q47 is turned on by the charger IC to allow battery power to be delivered to the target system.
FET Q47 is off when Q40 and Q46 are on.
The charger IC includes charge pumps to drive the N channel FET gates to a sufficiently high voltage to turn them on.
The charger IC in this example has an internal switch-mode power supply, with internal high side FET, that are used when charging the battery. The external components of this supply are L1 and D53 in the diagrams.
Battery charging current is measured through RS2.
It is important to monitor the battery temperature. Usually an NTC (negative temperature coefficient) thermistor attached to or internal to the battery is used for this. The charger IC has support for the thermistor.
A fuel gauge IC is used to collect information about battery charge levels. The gauge tracks current into and out of the battery, via sense resistor RS3. This sense resistor is in series with the battery GND terminal. The gauge has an I2C interface to the SMARC Module.
There are three status signals from the charger system to the SMARC Module: CHARGING#, BATLOW# and CHARGER_PRSNT#.
SMARC Design Guide 2.0 Page 106 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 74 Li-ION Battery Charger - Block Diagram
Battery Charger
DC Adapter
Fuel Gauge
Power Supply
I2C_PM To
SMARC Connector
1/2/3 Cell Li-Ion
or Li-Polymer
Charging
Supply
Adaptor Current
Sense path
Charging Current
Sense path
Bat-Pack
Negative
System
GND
Main Supply Path
Battery Charging
Path
Supply to the IC
Current Sense
Paths
Q40 Q46
Q47
RS1
RS2
L1
D52A
D52B
D53
RS3
Temp Sense path
Battery Temperature
Sense
SMARC Design Guide 2.0 Page 107 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 75 Li-ION Battery Charger - Schematic
QFN24
U77TI BQ24171
2
22
1
3
24
25
23
21
20
19
18
1716
15
14
13
12
11
10
9
8
7
6
5
4AVCC
ACN
ACP
CMSRC
ACDRV
STAT
TS
TTC
VREF
ISET
FB
SRN
SRPACSET
OVPSET
BATDRV#
REGN
BTST
PGND_23
AGND
SW_24
PVCC_3
SW_1
PGND_22
PVCC_2
D50
CA
10mOhm
2512
RS2
E2E1
I2I1
0805
3.9Ohm
R544
21
R543
3.9Ohm
0805
21
TI CSD16406Q3Q40
QFN-8
3
5 21
4
R5424.02KOhm0402
21
04024.02KOhm R541 21
R516
0402
100KOhm
21
22.1KOhmR540
0402
21
0402
100KOhmR515
21
0402
32.4KOhmR539
21
R538
0402
243KOhm
21
R514
0402
100KOhm
21 R513
100KOhm0402
21
2.2uFC535
50V2
1
2.2uF50V
C534
DNI2
1
100nF
C515
25V
21
1uF16V
C531
2
1
25V
C5331uF
2
1
C514100nF25V
2
1
C52710uF25V
2
1
25V
C52610uF
2
1
D53
C A
100nF
C513
25V
21
R537
10Ohm
210402
R536
1KOhm
040221
C532
47nF16V
21
1uF
C530
1 2
R512100KOhm0
402
21
D522
3
1
0402 R500
0Ohm
21
R5352.21KOhm0
402
21
25V470nF
C529
2
1
0Ohm
R526
040221
0402R534
6.81KOhm
21
10mOhmRS1
2512 E2E1
I2I1
GND_CHR
GND_CHR
R533
232KOhm0402
21
50V
C5284.7nF
2
1
R532
0402
499K
Ohm
21
0402R525
0Ohm2 1
UMT3
ROHM RJU003N03T106
Q43
3
1
2
25V10uFC525
2
1
10uF25V
C524
2
1
C512
25V100nF
2
1
25V100nFC511
2
1
25V22uFC502
2
1
ROHM RJU003N03T106UMT3
Q42
3
1
2
10KOhm
R5220402 21
C510
100nF25V
21
100nFC509
25V2
1
V_BAT
L1
3.3uH8.4A
21
V_BAT
MOD
V_BAT
0402 R511
100KOhm
21
100KOhmR510
0402
21
100KOhm
0402 R509
21
25V100nFC5082
1
GND_CHR
GND_CHR
GND_CHR
GND_CHR
GND_CHR
SON8
Q47TI CSD25401Q3
3
5
21
4
GND_CHR
GND_CHRGND_CHR
R502
1MEGOhm
040221
GND_CHR
V_BAT_CHARGE_A
R506
0402
100Ohm
21
25V22uFC501
2
1
GND_CHR
LTST-C190KGKT
D51
12
V_CARRIER_IN
V_CARRIER_IN
GND_CHR
Q46TI CSD16406Q3
QFN-8
3
521
4
R501
1MEGOhm
040221
GND_CHR
F1
21POLYFUSE
C503100nF50V2
1
RA3/1Port
J64
KYCON KLDHCX-0202-B
2
3
1 1
3
2
22uFC500
25V 2
1
Q41
ROHM RJU003N03T106
UMT3
3
1
2
BAT1_TS+
V_CHARGER_IN
CHARGING
VDD_AON
VDD_AON
VDD_AON
BQ24171_STAT
CHRG_LED
SRP
OVPSET
BQ_FB
ACN
ACP
ACDRV
CMSRC
ISET
BQ_TTC
AVCC
BATDRV
BTST
REGN
BQ_TS
CHARGER_LED
BQ24171_ACDRV_R
VDD_ACIN_RC
V_SYS_B2B
VSYS_CHGIN
BQ24171_SW
ACSET
VREF_3V3
VREF_3V3
EN_VDD_BAT
SRN
CHG_BAT
BAT_CHG_IN
5A, DC Adaptor
Route Differentially (Kelvin Routing)
LOW: CHARGINGFLOAT: CHARGE_COMPLETE/SLEEP
CHARGER STAT to CPU
Ichg = 0.4V/(20x10mOhm) = 2A
( Charging Current )
HIGH: CHARGE_COMPLETE/SLEEPLOW: CHARGING
No: of Cells Value of ResB
1 (4.2V)
2 (8.4V)
3 (12.6V) 499K
299K
100K
Charging Voltage
5V
12
16 1M
727K
243K
Value of ResA
Feedback Resistor Divider Config.Over Volt. Protection Configuration
Route Differentially(Kelvin Routing)
ResA ResB
SMARC Design Guide 2.0 Page 108 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 76 Battery Fuel Gauge
A comparator circuit such as the one shown below may be used to provide an indication to the SMARC Module that the battery charger power source is present. This circuit may be incorporated into some battery charger ICs.
Figure 77 Charger Present Detection
R5270Ohm
210OhmR528
21
V_1V8_LDO
UMT3
Q45
ROHM RJU003N03T106
3
1
2
10K
Ohm
0402
R523
21
C536
25V33nF
2
1
R545100Ohm
1206
21
R546
DNI100Ohm
1206
21
D54
OnS
em
iB
ZX
84C
5V
1LT
1G
31
V_BAT_3V_BAT_2
R547
1206
100OhmDNI
21
GND_BAT
MOD
V_BAT
MOD
R5481.82MEGOhm0
402
21
U79
TI BQ27510-G2
SON12
13
9
12
11
10
5
8
7
6
1
4
32
BI/TOUT
REG25 REGIN
BATVCC
VSS
SRP
SRN
TS
SDA
SCL
BAT_LOW/BAT_GD
TH_PAD
1
47Ohm
0402
R5502
10402
100Ohm
R5072
1
100Ohm0402
R5082
1
6.3V470nFC537
2
1
100nFC517
25V2
25V
C518100nF
2
1
C519
25V100nF
2
1
C520
25V100nF
2
1C521100nF25V
2
1
R551
0402
18.7KOhm
21
2512
RS
310m
Ohm
E2
E1
I2I1
MOD
I2C_PM_DAT
I2C_PM_CK
BAT1_TS+
I2C_PM_CK_FG1
I2C_PM_DAT_FG1
BATLOW
BQ27510_REGIN
BQ27510_VCC
BQ27510_SRN_RS
BQ27510_SRP_RSBQ27510_SRP
BQ27510_TSBQ27510_BI
BQ27510_SRN
BATLOW
(7-bit format)
I2C Address : 0x55
BAT_PACK Negative
100KOhm0402
R518
21
R517100KOhm0
402
21
Q44
3
1
2
OnSemi NCS2200SQ2T2
SC70-5
U78
2
1
5
4
3IN+
IN-
VCC
OUT
VEE
MOD
100KOhm
0402R521
2 1
25V100nF
C516
21R504
0402
1MEGOhm
21
R503
0402
1MEGOhm
21
V_BAT V_CHARGER_IN
V_1V8_LDO
BATTERY_IN
CHARGER_IN
CHARGER_PRSNT
CHARGER_PRSNT
SMARC Design Guide 2.0 Page 109 of 119 Mar 23, 2017 ©SGeT e.V.
10 THERMAL MANAGEMENT
10.1 General
SMARC Modules generally have modest power dissipations. In a production environment, heat-sinking is usually necessary to keep the Module electronics die temperatures within limits, at the higher operating temperatures.
10.2 Heat Spreaders
Heat spreaders are available from SMARC Module vendors. Their purpose is to present a uniform thermal interface that is the same across various Module designs. A heat spreader is not a full heat sink – the heat spreader top surface is meant to be in contact with a system specific heat sink, such as the wall of an enclosure or other heat sink. The figure below diagrams a typical heat spreader suitable for an 82mm x 50mm SMARC Module. The diagram plan view shows the heat spreader surface that the Module interfaces to. “TIM” is an abbreviation for “Thermal Interface Material” - a thermally conductive, compliant material to bridge the small gap between the heat-spreader surface and the surface of the system SOC. The Module is 82mm x 50mm, but the heat spreader is sized at 82mm x 42mm to allow the Module edge fingers to mate to the Carrier board MXM3-style socket. The heat spreader top, or “far side” surface, is 6mm above the Module PCB surface.
SMARC Design Guide 2.0 Page 110 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 78 Heat Spreader Example – 82mm x 50mm Module
Table 18 Heat Spreader Hole Types
Figure Notation Hole / Standoff Type Notes
Holes marked ‘A’ Clearance holes for M2.5 screws; 3mm tall clearance standoffs
These holes coincide with the SMARC mounting holes for 82mm x 50mm Modules
Holes marked ‘B’ Module design specific holes and standoffs X-Y locations of these holes are also Module design specific. The TIM location is design specific.
Holes marked ‘C’ M3 thread in heat spreader These holes allow either a heat sink to be attached to the heat spreader, or they can allow the heat spreader (and the SMARC Module / Carrier assembly) to be secured to an enclosure wall or other heat-sinking structure.
SMARC Design Guide 2.0 Page 111 of 119 Mar 23, 2017 ©SGeT e.V.
10.3 Heat Sinks
The figure below shows a heat sink that can be added to the heat spreader described in the figure above. This add-on heat sink attaches to the heat spreader through the ‘C’ holes marked on the heat spreader drawing above. A thermal interface material – thermally conductive paste, grease, or a gap pad – is needed between the heat spreader and the add-on heat sink, on the heat spreader “far” side.
Figure 79 Heat Sink Add-On to Heat Spreader
The best thermal transfer characteristics are usually obtained by a stand-alone heat sink. An example is shown in the following figure. The heat sink is secured to the SMARC Module through two design – specific interior holes (and design specific standoffs) that are straddling the TIM (the TIM in the figure is the square piece of foam that contacts the SMARC SOC). The four corner holes and standoffs coincide with the four SMARC Module holes (for 82mm x 50mm Modules). M2.5 screws pass through the heat-sink corner holes and standoffs, and pass through the SMARC Module, and catch the threads in the corresponding Carrier board hardware. Check with your SMARC Module vendor for the heat sinks that they offer.
Figure 80 Stand-Alone Heat Sink
SMARC Design Guide 2.0 Page 112 of 119 Mar 23, 2017 ©SGeT e.V.
10.4 Thermal Resistance Calculations
It is easy to estimate the thermal performance of a SMARC system if you have thermal resistance data from the vendors. The vendor sources can include silicon vendors, SMARC Module and Carrier board vendors and heat sink vendors. Thermal resistance is a simple concept, analogous to Ohm’s law and electrical resistance. Thermal resistance is expressed in degrees Celsius per Watt (0C/W). If a particular thermal interface has a thermal resistance of 8 0C/W and the source device dissipates 4W, then there will be a temperature rise of 8 * 4 = 32 0C across that interface. Some hypothetical thermal parameters are given in the table below, followed by some sample calculations for various situations. The calculations are just estimates, which can be useful for design guidance. The estimates should be followed up by measurements on physical samples. It may be useful to use thermal CAD simulations as well – after the “back of the envelope” calculations and before building hardware.
Table 19 Hypothetical Thermal Parameters
Parameter Symbol Value (Hypothetical)
Max SOC junction Temperature(Tj) TJ-MAX 90 0C
Thermal Resistance, CPU Junction to ambient (θJA) θJA 12 0C/W
Thermal Resistance, CPU Junction to case (θJC) θJC 0.4 0C/W
TIM interface (CPU to heat spreader or sink) θTM1 0.5 0C/W
Heat Spreader θHS 0.1 0C/W
TIM interface (heat spreader to add-on heat sink) θTM2 0.4 0C/W
Add-on Heat Sink - still air (natural convection) θHS1 4 0C/W
Stand-alone Heat Sink – still air (natural convection) θHS2 3 0C/W
SOC maximum power dissipation WSOC-MAX 5W
Maximum Environmental Temperature TOP-MAX To be calculated
Sample Calculations Using Hypothetical Thermal Parameters
No heat sink at all
TOP-MAX = TJ-MAX – θJA * WSOC-MAX = 90 – 12 * 5 = 30 0C
Heat Spreader + Add-On Heat Sink
TOP-MAX = TJ-MAX – (θJC + θTM1+ θHS + θTM2+ θHS1) * WSOC-MAX = 90 – (0.4 + 0.5 + 0.1 + 0.4 + 4 ) * 5 = 63 0C
Heat Spreader + Stand-alone Heat Sink
TOP-MAX = TJ-MAX – (θJC + θTM1+ θHS2) * WSOC-MAX = 90 – (0.4 + 0.5 + 3 ) * 5 = 70.5 0C
SMARC Design Guide 2.0 Page 113 of 119 Mar 23, 2017 ©SGeT e.V.
11 CARRIER PCB DESIGN RULE SUMMARY
11.1 General – PCB Construction Terms
The Table and Figure below serve to define and illustrate some terms used in describing PCB construction and in trace impedances
Table 20 PCB Terms and Symbols
Term / Symbol Definition
Stripline
Outer layer traces routed a fixed distance above an internal plane layer
Asymmetric Microstrip
Inner layer signal traces, mounted a fixed distance to a Primary Reference Plane (H1 or H3 in the figure below) and mounted a larger distance to a Secondary Reference Plane (H2 or H4 in the figure)
H Distance (or “height”) of a trace to the reference plane(s) – H0, H1, H2 etc. in the figure
W The width of the trace. Outer layer traces generally need to be a bit wider than inner layer traces to meet the same impedance. It is best to arrange that all inner layer traces for a given impedance class have the same width.
T The thickness of the trace. Inner layer traces are generally thinner than outer layer traces.
G The gap (or space) between two traces that are part of an edge-coupled differential pair.
P The pitch (or center-to-center distance) between two traces that are part of an edge-coupled differential pair. P = G + W for a given differential pair. A fairly common mistake in PCB design and fabrication is to get the pitch and the gap confused.
Clearance (Not shown in the figure) The distance to “other” traces and features (vias, holes, pours) on the same layer
The dielectric constants of the materials used in the PCB construction
Zo Trace impedance
SE Single Ended – trace that is single ended, not part of a differential pair
DE Differential Ended – trace pair that are used for differential signaling
SMARC Design Guide 2.0 Page 114 of 119 Mar 23, 2017 ©SGeT e.V.
Figure 81 PCB Cross Section – Striplines and Asymmetric Microstrips
PLANE
PLANE
Trace Trace
Trace
H1
H2
G
P
W
T
H3
H4
Trace Trace
Trace Trace
H0
Stripline Traces
Asymmetric Microstrip Traces
Trace
L1 - copper
L2 - copper
L3 - copper
L4 - copper
L5 - copper
L6 - copper
Prepreg - Dielectric
Prepreg - Dielectric
Prepreg - Dielectric
Core - Dielectric
Core - Dielectric
11.2 Differential Pair Cautions
Modern high speed interfaces (CSI, GBE, HDMI, LCD LVDS, PCIe, SATA and USB) must be routed as differential pairs over a ground plane. They should be routed as a pair on the same layer (edge-coupled pairs) and not as pairs on different layers (known as broad-side coupled pairs) that follow the same X-Y path. There should be a minimum of layer transitions – ideally, just two (SMARC connector to internal layer, and internal layer to the destination connector or IC). For edge coupled differential pairs, there are several parameters of interest:
Differential impedance: the impedance of the trace pair as seen by a differential driving source.
Single impedance: the impedance of one of the traces in the pair, if it were removed from the pair and driven by a single ended source.
Gap: the inside edge to inside edge spacing between the traces in a differential pair. Labeled ‘G’ in the figure above.
Pitch: the center-to-center distance between the pairs in a differential pair. Labeled ‘P’ in the figure above.
It is fairly common for people to mix up the Gap and the Pitch. Make sure you don’t make this mistake.
SMARC Design Guide 2.0 Page 115 of 119 Mar 23, 2017 ©SGeT e.V.
11.3 General Routing Rules and Cautions
High speed differential signals must be routed as differential pairs. o Keep the pairs symmetrical o Stubs are not allowed o Avoid tight (right angle) bends o Match the pair lengths, on each layer used
Routing with reference to a GND plane is preferred: o If GND plane referencing is not possible, then routing against a well bypassed power
plane will have to suffice.
Do not route over plane splits.
Layer transitions should be minimized. Ideally, there are a maximum of two vias per net: a transition at the SMARC connector to get to an inner layer, and a transition at the destination device, to get to the device pins.
If a layer change is made and the layer change results in a reference plane change, then the two reference planes should be tied together in the same vicinity as the trace layer via. If the two reference planes are at different potentials, then they should be tied together through a “stitching capacitor”. The stitching cap isolates the DC potential between the planes but allows the high speed return currents associated with the trace. If the two reference planes are at the same potential, then they should be tied together with a “stitching via” – a seemingly useless via, except that it allows the high frequency trace return currents to flow between the reference planes. Following this advice results in lower EMI (as “loop area” is reduced) and better signal integrity.
Controlled impedance design must be used: o All traces have a single ended (SE) impedance. o Differential pair traces have a SE impedance, and the pair has a differential (DE)
impedance. o Recommended SE and DE impedances are given in the following sections of this Design
Guide.
Differential pairs have pair matching requirements (the two traces that make up a pair need to be matched to a certain tolerance). There are also group matching requirements: if more than one pair is needed for the function, then there are group matching requirements as well (for example LVDS[0]+/- needs to match LVDS[1]+/1 and LVDS[2]+/- and so on).
The propagation speed of inner layer traces and outer layer traces is different.
Differential pairs that are part of a common group (for example, the four LVDS data pairs in a 24 bit LVDS implementation) should be routed such that each pair in the group has the same per-layer routing length as the others.
Routing on inner layers may reduce EMI. It is said that good EMI characteristics may be obtained by careful outer layer routing as well.
Routing high speed traces across plane splits should be avoided. If it cannot be avoided, then stitching caps to bridge the split should be used.
Cross-talk effects result from traces running in parallel, too close and for too long, either side by side on the same layer, or directly above / beneath each other on adjacent inner layers. For the same layer case, the mitigation is to increase the spacing to other traces. For the adjacent layer case, the traces on the adjacent layers should not run in parallel. Ideally, they are routed orthogonal to each other. If orthogonal routing is not possible, they should be at least 30 degrees off from each other.
IC power pins need to be properly bypassed, as close as possible to the power pin.
SMARC Design Guide 2.0 Page 116 of 119 Mar 23, 2017 ©SGeT e.V.
11.4 Trace Parameters for High-Speed Differential Interfaces
Routing rules for high speed differential traces are summarized in the table below. Some notes on the table:
The “Max Symbol Rate” in the chart below is not the data transfer rate. It is the maximum transition rate on a single differential pair of the link, including the link encoding overhead.
o For example: 24 bit LCD LVDS is packed into four lanes. Including the control bits, there are actually 28 bits packed into the four LVDS lanes. There is no encoding overhead in LCD LVDS – it is just raw data – because there is a separate LVDS clock. So the “symbol rate” on an LVDS differential data pair, for a 40 MHz LVD clock, is (28 bits x 40 MHz / 4 lanes) = 280 Mbps.
The “Sym Width” is the width of the pair Symbol, in ps. It is the inverse of the Max Symbol Rate. o Recall that the propagation speed of a micro-strip (outer layer) trace signal is about 150
ps / inch, and for a stripline (inner layer) trace signal, about 180 ps / inch. o The differential pair length mis-match, when expressed in units of time, needs to be small
compared to the Symbol Width.
Lengths are shown in mils (thousandths of an inch, or 0.0254 mm). The American convention for the decimal point and comma meaning is used. The 5,000 mil max length is 5.0 inches or 127 mm.
“Pair Match” refers to the length matching of the two parts of the differential pair.
Group Match refers to the length matching of the different pairs in a group.
N/A means “Not Applicable”.
“TX/RX Match” means the length matching between the TX and RX pairs.
Table 21 High-Speed Differential Trace Parameters
Interface Max Symbol Rate
(approximate) Sym Width (ps)
Zo Diff (ohms)
Zo SE (ohms)
Max Length (mils)
Pair Match (mils)
Group Match (mils)
TX / RX Match (mils)
PCIe 8 Gbps (Gen 3) 5 Gbps (Gen 2) 2.5 Gbps (Gen 1)
125 200 500
85 (+-15%)
50 5,000 10,000 12,000
< 5 N/A < 2000
SATA 6 Gbps (Gen 3) 3 Gbps (Gen 2) 1.5 Gbps (Gen 1)
167 333 667
85 (+-20%)
50 (+-15%)
3,000 6,000 8,000
< 5 N/A < 2000
HDMI 3.4 Gbps (HDMI 1.3) 1.6 Gbps (HDMI 1.2) 1.6 Gbps (HDMI 1.1) 1.6 Gbps (HDMI 1.0)
294 625 625 625
90 45 5,000 < 10 < 830 N/A
CSI
1 Gbps (CSI-2) 208 Mbps (CSI)
1000 4808
90 45 9,000 < 100 < 100 N/A
LVDS 770 Mbps (24b 110 MHz) 280 Mbps (24b 40 MHz)
1299 3571
100 (+-20%)
50 6,750 < 20 < 20 N/A
USB 2.0 480 Mbps (HS) 12 Mbps (FS)
2083 23333
90 45 10,000 < 100 N/A N/A
USB 3.0 5 Gbps N/A 85 (+-10%)
50 (+-15%)
4,500 < 5 N/A N/A
GBE 250 Mbps N/A 100 50 4,000 < 5 < 30 N/A
DP++ 8.1 Gbps N/A 85 (+-10%)
50 (+-10%)
3,200 < 5 < 1000 N/A
Reference Plane: GND is preferred Clearance to other traces: 20 mil or more
SMARC Design Guide 2.0 Page 117 of 119 Mar 23, 2017 ©SGeT e.V.
Max Vias: Three maximum; two or less preferred
11.5 Trace Parameters for Single Ended Interfaces
Table 22 Single Ended Trace Parameters
Interface Zo SE (ohms)
Max Length (mils)
General 50 12,000
SD Card 50 4,000
SMARC Design Guide 2.0 Page 118 of 119 Mar 23, 2017 ©SGeT e.V.
11.6 PCB Construction Suggestions
PCB construction suggestions with trace width and gap parameters are given in the following three tables for four, six and eight layer PCBs. These are meant as a starting point. It is wise to plan ahead with your PCB fabricator and get their input. Four layer construction is difficult since the high speed signals should be referenced against a GND plane, and the four layer construction offers only a single trace layer that is GND referenced.
Table 23 PCB Construction Example - 4 Layers
Layer Use Layer
Thickness (mils)
Copper (ounces)
Plane Ref
SE 50 Ohm W (mils)
Diff 90 Ohm W / G (mils)
Diff 92.5 Ohm W / G (mils)
Diff 100 Ohm W / G (mils)
SM 0.8
L1 Sig Cu 1.6 0.5 + plating L2 4.5 4.6 / 6.4 4.5 / 6.5 4.4 / 10
Prepreg 2.9
L2 PWR Cu 1.2 1.0
Core
50.0
L3 GND Cu 1.2 1.0
Prepreg 2.9
L4 Sig Cu 1.6 0.5 + plating L3 4.5 4.6 / 6.4 4.5 / 6.5 4.4 / 10
SM 0.8
Finished Thickness: 63.0 mil Impedance tolerance: +/- 10%
Table 24 PCB Construction Example - 6 Layers
Layer Use Layer
Thickness (mils)
Copper (ounces)
Plane Ref
SE 50 Ohm W (mils)
Diff 90 Ohm W / G (mils)
Diff 92.5 Ohm W / G (mils)
Diff 100 Ohm W / G (mils)
SM 0.8
L1 Sig Cu 1.6 0.5 + plating L2 4.5 4.6 / 6.4 4.5 / 6.5 4.4 / 10
Prepreg 2.9
L2 PWR Cu 1.2 1.0
Core 3.0
L3 Sig Cu 0.6 0.5 L2/L5 4.0 4.0 / 6.5 4.0 / 6.5 3.5 / 8.0
Prepreg
42.0
L4 Sig L6 0.6 0.5 L5/L2 4.0 4.0 / 6.5 4.0 / 6.5 3.5 / 8.0
Core 3.0
L5 GND Cu 1.2 1.0
Prepreg 2.9
L6 Sig Cu 1.6 0.5 + plating L5 4.5 4.6 / 6.4 4.5 / 6.5 4.4 / 10
SM 0.8
Finished Thickness: 62.2 mil Impedance tolerance: +/- 10%
SMARC Design Guide 2.0 Page 119 of 119 Mar 23, 2017 ©SGeT e.V.
The eight layer example below shows an 80 mil (2mm) PCB thickness. This is often desirable for Carrier boards, and can be arranged for the four, six or eight layer versions. The thicker PCB makes for a more rugged system: the stiffness of a sheet of material (PCB or other sheet material) is proportional to the cube of the material thickness. The eight layer construction below offers the advantage of four signal layers (L1, L2, L6, L8) that are GND referenced. This is best for high speed signals. This construction also makes power distribution very easy. The Pri/Sec notation in the Plane Ref column below means the following: the plane layer to which the signal is closest is the Primary reference plane. The further plane is the Secondary. If a high speed signal or signal pair changes reference layers (for example, L6 is referenced to L7 and L3 is referenced to L2 - so if you transition from L6 to L3, you are changing reference planes) it is recommended to put in a stitching via or via pair. The stitching vias are single net vias (GND) that tie the two reference planes together (L2 to L6) for the high frequency return signals that are trying to follow the path of the signal traces. You will have better signal integrity and fewer EMI issues if you do this. It is not necessary if reference planes are not being changed (for example, a transition from L1 to L3 keeps both referenced to L2, hence there is no reference plane transition).
Table 25 PCB Construction Example – 8 Layers
Layer Use Layer
Thickness (mils)
Copper (ounces)
Plane Ref Pri/Sec
SE 50 Ohm W (mils)
Diff 90 Ohm W / G (mils)
Diff 92.5 Ohm W / G (mils)
Diff 100 Ohm W / G (mils)
SM 0.8
L1 Sig Cu 1.6 0.5 + plating L2 4.5 4.6 / 6.4 4.5 / 6.5 4.4 / 10
Prepreg 2.9
L2 GND Cu 1.2 1.0
Core 3.0
L3 Sig Cu 0.6 0.5 L2/L4 4.0 4.0 / 6.5 4.0 / 6.5 3.5 / 8.0
Prepreg 10.0
L4 PWR Cu 1.2 1.0
Core
38.0
L5 PWR Cu 1.2 1.0
Prepreg 10.0
L6 Sig Cu 0.6 0.5 L7/L5 4.0 4.0 / 6.5 4.0 / 6.5 3.5 / 8.0
Core 3.0
L7 GND Cu 1.2 1.0
Prepreg 2.9
L8 Sig Cu 1.6 0.5 + plating L7 4.5 4.6 / 6.4 4.5 / 6.5 4.4 / 10
SM 0.8
Finished Thickness: 80.6 mil Impedance tolerance: +/- 10%