Download pdf - Layout-Process Anitha Vlsi

8/18/2019 Layout-Process Anitha Vlsi

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Layout Process

and

Design Rules


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Intro

CMOS fabrication can beaccomplished using either of thethree technologies:

• N-well/P-well technologies • win well technolog!

• Silicon On Insulator "SOI#


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nMOS $abrication process

hin wafer cut from a single cr!stal ofsilicon

%& to '&(mm ) dia(*+mm thic,ness dopped withimpurities li,e boron

SubstrateP substrate


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hic, o.ide "'m#

Step 0: 1a!er of SiO0 is grown o2er the

substrate

Photo 3esist

Step 4: la!er of photo resist to get e2enthic,ness

P substrate

P substrate


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56 1ight

Mas,

Step +: e.posing the photo resist la!er witha mas, to the 56 light7 where channel of

transistor is going to place

Ma,es hardene.pect the placewhere di8usion isgoing to be*

P substrate


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9indow is created

Step &: tched awa! together with underl!ing silicon*

Step ;: remaining photo resist alsoremo2ed*


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Step %: again photo resist and mas,ingallows the Pol!silicon to be patterned

n t!pe di8usion are di8used to form thesource and drain

=i8usion is achie2ed b! heating thewafer to the high temperature andpassing through the gas containing the

desired n t!pe impurit!

P substrate


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Step >: thic, o.ide is grown o2er the waferagain and then mas,ed with photo resist to

e.posed selected areas of Pol!silicon gate7source and the drain* " for contact cuts#

Step ?: whole chip is then metal deposited o2erits surface*


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1a!out design rules

●Design rules are a set of geometricalspecifications that dictate the design of the

layout masks

● A design rule set provides numerical valuesoFor minimum dimensions

oFor minimum line spacings

●Design rules must be followed to insurefunctional structures on the fabricated chip

●Design rules change with technological

advances (www.mosis.org)


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●Why we use design rules

o

!nterface between designer and processengineer

o"uidelines for constructing process masks

o#anufacturing processes have inherent

limitations in accuracy.

oDesign rules specify geometry of masks which

will provide reasonable yields.

oDesign rules are determined by e$perience.


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#anufacturing problems

●%hotoresist shrinkage& tearing.

●'ariations in material deposition.

●'ariations in temperature.

●'ariations in o$ide thickness.

●!mpurities.

●'ariations between lots.

●'ariations across a wafer.


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ransistor problems

●'ariations in threshold voltage

oo$ide thickness*

oion implantation*

opoly variations.

●+hanges in source,drain diffusion overlap.●'ariations in substrate.


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Wiring problems

●Diffusion changes in doping - variations

in resistance& capacitance.

●%oly& metal variations in height& width -variations in resistance& capacitance.

●/horts and opens


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0$ide problems

●'ariations in height.

●1ack of planarity - step coverage.

metal 2metal 3

metal 3


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'ia problems

●'ia may not be cut all the way through.

●4ndersi5e via has too much resistance.

●'ia may be too large and create short.


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Design Rules

#inimum length or width of a feature on a layer is 2

λ

Why

o allow for shape contraction#inimum separation of features on a layer is 3 λ

Why

o ensure ade6uate continuity of the

intervening materials.


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Design 7ules

●ypical rules

o#inumum si5e

o#inimum spacingo Alignment , overlap

o+omposition

o8egative features


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#0/!/ /+#0/ design rules

●Designed to scale across a wide range of

technologies.

●Designed to support multiple vendors.

●Designed for educational use.

●9rgo& fairly conservative.

●http://www*mosis*com/design/rules/

http://www.mosis.com/design/rules/http://www.mosis.com/design/rules/


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1ambda design rules

●λ is the si5e of a minimum feature.

●/pecifying λ particulari5es the scalable

rules.

●%arasitics are generally not specified in

units


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ypes of Design 7ules●/calable Design 7ules (e.g. /+#0/)

o:ased on scalable ;coarse grid< - λ(lambda)

o!dea reduce λ value for each new process& but keep rule

the same

=ey advantage portable layout

=ey disadvantage not everything scales the same

o8ot used in ;real life<


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● Absolute Design 7ules

o:ased on absolute distances (e.g. >.?@m)

ouned to a specific process (details usually

proprietary)

o+omple$& especially for deep submicron

o1ayouts not portable


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9ires

metal 4;

metal 04

metal '4

pdi8/ndi8 4

pol!0

All wire widths are

multiples of


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ransistors

0

4

'

40

4


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'ias

●ypes of via metal2,diff& metal2,poly&

metal2,metal3.

B

2

B

3


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#etal C via

●ype metalC,metal3.

●7ules

ocut C $ C

ooverlap by metal3 2

ominimum spacing Cominimum spacing to via2 3


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