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Encoder-Decoder in Encoder-Decoder in Verilog Verilog
Encoder-Decoder in Encoder-Decoder in Verilog Verilog
Gookyi Dennis A. N. Gookyi Dennis A. N.
SoC Design Lab.SoC Design Lab.
July.15.2014
ContentsContents Objectives Encoder Decoder Encoder-Decoder
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Objectives Objectives Wish to design a system that encodes at one end and
decode at the other end Design a 4 to 2 encoder Design a 2 to 4 decoder Design a top level module that instantiates the
encoder and the decoder
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Block diagramBlock diagram The block diagram of the whole system is shown
below:
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4 to 2Encoder
2 to 4 Decoder
4 Bit input
4 Bit output2 Bit inout
Encoder Encoder Truth table of 4 to 2 encoder is shown below:
Output equations are as follows:out[0] = ((~in[3])&(~in[2])&(in[1])&(~in[0])) | out[0] = ((~in[3])&(~in[2])&(in[1])&(~in[0])) |
(((in[3])&(~in[2])&(~in[1])&(~in[0])))(((in[3])&(~in[2])&(~in[1])&(~in[0])))
out[1] = ((~in[3])&(in[2])&(~in[1])&(~in[0])) | out[1] = ((~in[3])&(in[2])&(~in[1])&(~in[0])) | (((in[3])&(~in[2])&(~in[1])&(~in[0])))(((in[3])&(~in[2])&(~in[1])&(~in[0])))
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In[3] In[2] In[1] In[0] Out[1]
Out[0]
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
EncoderEncoder Verilog code for encoder (submodule)
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EncoderEncoder RTL schematic
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Decoder Decoder Truth table for 2 to 4 decoder
Output equations are as follows:out[0] = (~in[0]) & (~in[1])out[1] = (in[0]) & (~in[1])out[2] = (~in[0]) & (in[1])out[3] = (in[0]) & (in[1])
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In[1] In[0] Out[3]
Out[2]
Out[1]
Out[0]
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 0 1 0 0 0
Decoder Decoder Verilog code for decoder (submodule)
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DecoderDecoder RTL schematic
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Encoder_DecoderEncoder_Decoder Verilog code
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Encoder_DecoderEncoder_Decoder RTL schematic
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Encoder_DecoderEncoder_Decoder Full testbench
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Encoder_DecoderEncoder_Decoder Waveform
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