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System Digital Encoder dan Decoder

System Digital Encoder dan Decoder

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System Digital Encoder dan Decoder. Mux/Demux Vocabulary. MULTIPLEXER (aka DATA SELECTOR)- circuit that can select one of a number of inputs and pass the logic level of that input to the output. - PowerPoint PPT Presentation

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Page 1: System Digital Encoder dan Decoder

System DigitalEncoder dan Decoder

Page 2: System Digital Encoder dan Decoder

Mux/Demux Vocabulary

MULTIPLEXER (aka DATA SELECTOR)- circuit that can select one of a number of inputs and pass the logic level of that input to the output.DEMULTIPLEXER (aka DATA DISTRIBUTOR)- circuit that depending on the status of its select inputs will channel its data input to one of several outputs.

SELECT INPUTS (aka ADDRESS LINES)- used by the mux to determine which data inputs will be switched to the output. linesselectNlinesinputif N 2

Page 3: System Digital Encoder dan Decoder

BASIC TWO-INPUT MULTIPLEXER

S OUTPUT0 Z=I01 Z=I1

DATAINPUTS

I1

I0

SSELECT INPUT

SISIZ 10

Page 4: System Digital Encoder dan Decoder

FOUR-INPUT MULTIPLEXER

S0S1

I0

I1

I2

I3 S1 S0 OUTPUT0 0 Z=I00 1 Z=I11 0 Z=I21 1 Z=I3

Page 5: System Digital Encoder dan Decoder

8-to-1 ENCODER

Page 6: System Digital Encoder dan Decoder

MULTIPLEXER LOGIC DIAGRAM

I 0

I 1

I 2

I 3

I 4

I 5

I 6

I 7

ES2 S 1 S 0

74151

MUX

DATA

INPUTS

SELECT LINES

Z_Z

• Takes one of many inputs and funnels it to an output Z.

•Take the selector lines convert to a decimal number and this is the input funneled to the output.

•Strobe is active low enable

S2 S1 S0 E Z0 0 0 0 I00 0 1 0 I10 1 0 0 I20 1 1 0 I31 0 0 0 I41 0 1 0 I51 1 0 0 I61 1 1 0 I7

Page 7: System Digital Encoder dan Decoder

MULTIPLEXER APPLICATIONS

•DATA ROUTING•PARALLEL-TO-SERIAL CONVERSION•OPERATION SEQUENCING•IMPLEMENT LOGIC FUNCTION OF A TRUTH TABLE

Page 8: System Digital Encoder dan Decoder

LOGIC FUNCTION GENERATION

C B A Z0 0 0 00 0 1 10 1 0 10 1 1 01 0 0 01 0 1 01 1 0 01 1 1 1

ES2 S 1 S 0

74151

MUX

I 0

I 1

I 2

I 3

I 4

I 5

I 6

I 7

ABCCBACBAZ

+5

Page 9: System Digital Encoder dan Decoder

FILL IN THE TABLE

S2 S1 S 0

MUX

I 0

I 1

I 2

I 3

I 4

I 5

I 6

I 7

10101010

A B C

f(ABC)

A B C F0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

TEST

Page 10: System Digital Encoder dan Decoder

FILL IN THE TABLE

S2 S1 S 0

MUX

I 0

I 1

I 2

I 3

I 4

I 5

I 6

I 7

10101010

A B C

f(ABC)

A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 11 0 1 01 1 0 11 1 1 0

TEST

Page 11: System Digital Encoder dan Decoder

FILL IN THE TABLE

I 0

I 1

P

Q

C

S 0

I 0

I 1

A

S 0

Y

I 0

I 1

I 2

I 3

LMNO

B C

S 1 S 0

A B C Y0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

TEST

Page 12: System Digital Encoder dan Decoder

FILL IN THE TABLE

I 0

I 1

P

Q

C

S 0

I 0

I 1

A

S 0

Y

I 0

I 1

I 2

I 3

LMNO

B C

S 1 S 0

A B C Y0 0 0 L0 0 1 M0 1 0 N0 1 1 O1 0 0 P1 0 1 Q1 1 0 P1 1 1 Q

TEST

Page 13: System Digital Encoder dan Decoder

WRITE A BOOLEAN EXPRESSION FOR THE CIRCUIT

I 0

I 1

I 2

I 3

1011

A B

S 1 S 0

f(AB)

ABBABA

TEST

Page 14: System Digital Encoder dan Decoder

DEMULTIPLEXER1-of-8 DECODER

Page 15: System Digital Encoder dan Decoder

DEMULTIPLEXER LOGIC DIAGRAM•Logic circuit that depending on the status of its select inputs will funnel its data input to one of several data outputs.•Separate enable inputs (useful for cascading decoders) into AND gate which must be high to enable the decoder outputs.

A 2 A 1 A 0

74138DEMUX

1-OF-8 DECODER

SELECT LINES

E1E2E3E

0O

1O

2O

3O

4O

5O

6O

7O

0 0 1 RESPOND TO INPUT CODE A2A1A01 X X DISABLED –ALL HIGHX 1 X DISABLED –ALL HIGHX X 0 DISABLED –ALL HIGH

1E 2E 3E OUTPUTS

Page 16: System Digital Encoder dan Decoder

LOGIC FUNCTION GENERATION

A 2 A 1 A 0

74138

1E

2E

3E

ABC

+5

0O

1O

2O

3O

4O

5O

6O

7O

f(ABC)

C B A f0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

A B X0 0 10 1 11 0 11 1 0

NAND- any low in gives a high out

Page 17: System Digital Encoder dan Decoder
Page 18: System Digital Encoder dan Decoder

LAB 35. A SECURITY MONITORING SYSTEM

Page 19: System Digital Encoder dan Decoder

TEST

NAME THE CIRCUIT

A 2 A 1 A 0

1E

2E

3E

0O

1O

2O

3O

4O

5O

6O

7O

Page 20: System Digital Encoder dan Decoder

TEST

NAME THE CIRCUIT

ES2 S 1 S 0

I 0

I 1

I 2

I 3

I 4

I 5

I 6

I 7

Page 21: System Digital Encoder dan Decoder

TEST

STATE THE BOOLEAN EXPRESSION

ES 2 S 1 S 0

74151

MUX

I 0

I 1

I 2

I 3

I 4

I 5

I 6

I 7

+5

A B C

A B C F0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

C AB BC A CBA

Page 22: System Digital Encoder dan Decoder

TEST

STATE THE BOOLEAN EXPRESSION

A B C F0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

A 2 A 1 A 0

74138

1E

2E

3E

CBA

+5

0O

1O

2O

3O

4O

5O

6O

7O

f(ABC)

ABC BC A CBA