Spectral Design & Test Inc.
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EDA Challenges of 3D Chip Integration
7/17/2012
Dr. Michael L. Bushnell
Principal, Spectral Design & Test, Inc.
Board of Trustees Research Fellow
and Professor of ECE
Rutgers University
Piscataway, New Jersey
www.spectral-dt.com
Spectral Design & Test Inc.
Biography
BS from MIT, MS & PhD from Carnegie Mellon
Fellow of the IEEE
Presidential Young Investigator of NSF
Co-Founder of Spectral Design and Test, Inc.
Memory Instance Design
Design For Test Solutions
> 115 papers in digital & analog test, physical design
Current research interests:
3D chip stacking (just started)
Circuit test and fault-tolerance
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Spectral Design & Test Inc.
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Agenda
Problems of 3D Silicon Integration
Need Contactless Testing Capability for Interposers
Major Assembly Problems
Power Consumption
Severe Test Complexity
Severe Complexity of Fault-Tolerant Routing
Aggravates Hardware Verification Problems
Solutions from an EDA Perspective
More Design Automation for Physical Design & Test
3D Stack Interconnect Routing Fault Tolerance
Better Delay and Power Characterization
Summary 7/17/2012
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Spectral Design & Test Inc.
Need for More EDA
Handheld appliance design now very labor intensive
Cannot afford a NRE design cost increase
3D Chip Stacking Requires New EDA Tools for:
Contactless Testing and Test Design Automation
Power Estimation
Interconnect Fault Tolerance
Partitioning for Synthesis
System Verification
Presently outsource DFT insertion to cut costs
Without more automation, Design Costs of 3D
Stacks will be prohibitive 7/17/2012
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Spectral Design & Test Inc.
3D Chip Stack Technology
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TSV – through substrate via on chip
Self-Assembly Technologies with High-Precision Chip Alignment and Fine-Pitch
Microbump Bonding for Advanced Die-to-Wafer 3D Integration, T. Fukushima,
Y. Ohara, M. Murugesan, J.-C. Bea, K.-W. Lee, T. Tanaka, and M. Koyanagi,
Proc. Electronic Components and Technology Conf., IEEE, p 2050, 2011.
Spectral Design & Test Inc.
SEM Photographs of Chip Stacks
3D Chip Stack Technology Using Through-Chip Interconnects, P. Benkart, A. Kaiser,
A. Munding, M. Bschorr, H.-J. Pfleiderer, E. Kohn, A. Heittmann, H. Huebner, and U.
Ramacher, Design & Test of Computers, IEEE, p 515 , Nov-Dec, 2005. 7/17/2012
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Stack with one thinned chip
soldered in back-to-face
technology
Stack with two thinned chips
soldered in back-to-face
technology
Spectral Design & Test Inc.
4 Chip Stack with Side Metallization
An Efficient Edge Traces Technique for 3D Interconnection of Stack Chip, S.-R.
Kima, Ah-Young Parka, C. D. Yooa, Jae Hak Lee, J.-Y. Song and S. S. Lee, Proc.
Electronic Components and Technology Conf., IEEE, p 1811, 2011.
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Computer tomography image of
stacked chip
SEM micrograph of stacked chip
Spectral Design & Test Inc.
Contactless Testing of Interposers
New EDA Tools required for any contactless solution:
Physical design of interposers and through-substrate vias
Physical design of reconfigurable fault-tolerant interconnect
Spectral analysis tool is needed to analyze test data from
irradiating interposers and chips using contactless testing
Interposers & chips need physical design/test rule checkers
Methods to detect missing solder bumps in stack:
X-ray luminography
Ultrasonic tests
Measuring local thermal deformation to estimate local
surface deformation
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Spectral Design & Test Inc.
Example of Contactless Test
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Shield
Flying
Detector
Background
Detector
Stimulus source – radiation, UV
light, ultrasound, visible light,
X-ray, heat, laser Fixed or flying
Shield
Interposer
Shield
Flying
Detector
Spectral Design & Test Inc.
Better Power Estimation & Distribution
Present-day chip power estimation is still difficult
Intimately tied with delay estimation and knowledge of
temperature hot spots
Conflict between accuracy vs. fast simulation of vectors
3D Chip Stacking is even harder, because:
Thermal analysis is now 3D, not 2D – need new algorithms
Power dissipation is even more severely impacted by
partitioning and routing decisions during synthesis
Need automated design of power distribution method
(including decoupling capacitors) for 3D chip stack
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Spectral Design & Test Inc.
Design of Fault-Tolerant Interconnect
Easier than designing fault-tolerant random logic
Must support electrical and/or optical interconnect in
network-on-chip (noc) environments
Handle both permanent and intermittent faults
Requires new EDA tools:
Place spare TSVs to guarantee reconfigurability
Testing of fault-tolerant interconnect using BIST
Reconfiguration hardware design – hot standby-sparing vs.
cold standby-sparing, fault masking, active vs. passive
redundancy
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Spectral Design & Test Inc.
Test Design Automation for 3D Stack
Test debug is already very difficult:
Often requires PhD-level expertise -- expensive
Need more test design automation
Projecting fault coverages of different 3D routing
configurations in the design space
Automated synthesis of fault-tolerant BIST & interconnect
test controllers for 3D chip stack
Fault-tolerant modules for on-the-fly reconfiguration of
interconnect to fix transient faults
Need much better test data compression solutions
Reduce already voluminous test data
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Spectral Design & Test Inc.
System Verification & Signal Integrity
Customary to verify modified design against golden
design after each hardware synthesis step
Necessary to identify CAD tool errors, designer errors, etc.
Done after logic synthesis, scan & DFT hardware insertion,
physical design, etc.
Even more important for 3D chip stack
EDA Needs Are:
Faster verification tools
Incremental verification tools
Tools to design for signal integrity of 3D chip stack
CPU efficient tools to generate signal integrity tests
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Spectral Design & Test Inc.
Main 3D Chip Stacking EDA Difficulties
Current EDA tools/flows are close to limit of
complexity that the designer can understand
Too many variations of essentially the same file format
Even for so-called standard interchange formats
Unnecessarily complex options and design choices
Extraordinarily complex flows at large companies for design
and test insertion for 100 to 250 M gate chips (1-2 B trans.)
Couples test, fault tolerance, signal integrity, power
distribution, cooling, physical design, & signal routing
CAD algorithms for each optimization are too fragile
Can no longer optimize each of these separately
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Spectral Design & Test Inc.
Design Space Couplings
Fault tolerance affects chip stack delay, signal
integrity, physical design, and test
On-the-fly reconfiguration to handle intermittent faults in
interconnect causes more test problems
Power distribution and cooling affects signal integrity,
physical design, & test because of hot spots in stack
Physical design & signal routing affects everything
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Spectral Design & Test Inc.
Need Multi-Criterion Optimization
Use mathematical programming -- better stability than
simulated annealing, gradient descent, genetic, etc.
Linear
Integer linear
Quadratic 0-1
Non-linear
For coupled design tradeoffs (e.g., fault tolerance &
test), optimize both simultaneously with optimizer
Combine constraints from both into one cost function
Use tournament structure (of genetic algorithms),
without crossover & mutation operations
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Spectral Design & Test Inc.
Example -- Spectral EntropyTM Product
First Design-for-Testability (DFT) tool that can make
an extremely untestable circuit testable
Uses a very sophisticated multi-criterion optimizer
Circuit:
High-volume, very difficult-to-test industrial circuit
2,679,067 logic gates, 123,582 flip-flops, 4,464 latches
120 memories
Result from optimizers (still running & improving):
Simple: 1.716% test hardware overhead, 55.77% test cov.
Multi-crit.: 1.579% test hardware overhead, 92.50% test cov.
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Spectral Design & Test Inc.
Solutions
Restrict designers’ choices in design space
Standardize clock gaters, edge detectors, scan chains, etc.
Need more Design Automation:
If we increase design difficulty even more with 3D chip
stacking, it is too costly to design
Only the highest-volume devices can afford it (mproc.
arrays, memory, cell phone modulators, graphics
processors, digital TV, etc.)
Build in all Testing (even RF) -- control costs
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Summary
Need technological breakthrough in contactless
testing of chips and interposers for 3D integration
Need new EDA tools with creative, original
approaches and better algorithm stability
Old ones are very apt to break on 3D chip stacks
Tools best developed as joint research projects
between EDA companies and large design houses
Need academic involvement for creative ideas and theory
Need EDA company to make a robustly programmed tool
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