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A Seminar on
I ntroduction to Double Gate Transistors
By:
Shekhar Yadav
(2010 VLSI16)
ABV I ndian I nsti tute of I nformat ion Technology and Management ,
Gwalior, 474010, India
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OUTLINE Introduction
Challenges of Sub-100 nm technology
Multi Gate Transistors
Industry need
Double Gate Transistors
Planner Double Gate MSOFET.
Vertical Double Gate MOSFET(VDGM)
Conclusion
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INTRODUCTION (MOORES LAW AND
SCALING CHALLENGES) Moores Law: The number of transistors on a chip roughly
doubles in every one and half year.
Challenges to achieve sub 100 nm MOSFET:
Short channel effects (SCE)
Gate oxide thickness limitation
Fig:1 Growth of VLSIAccording to Moores law
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INTRODUCTION (MULTI GATE
TRANSISTORS: A SOLUTION TO SCE) Multi Gate Transistors: A multigate device or multiple gate field
effect transistors refers to a MOSFET which incorporates more than
one gate into a single device.
MuGFET (multiple gate field effect transistors )
MiGFET (multiple independent gate field effect transistors)
Fig 2: Structures of var iousMult igate Transistors
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INTRODUCTION (I NDUSTRY NEED AND
INTEGRATION SPECIFICATIONS) Industry need: In digital VLSI system design space, considerable
attention has been given to the design of low power, high-
performance and high density microprocessors.
Specifications for nonconventional transistors are:
Low leakage current High driving current
Small in size
More ideal characteristics
Some other considerations are:
To fabricate the multigate device by existing fabrication resource.
Fabrication process of non planner devices must utilize
conventional fabrication chain.
Fabrication process must not be very costly.
Material used in the device structure should be easily available.
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DOUBLE GATE TRANSISTORS
(I NTRODUCTION) Double gate transistors are first to multigate transistor
family.
MOSFETs containing two different gates placed opposite
side of body such that a Gate-oxide-Body-Oxide-Gatestack is formed are called Double Gate MOSFETs.
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DOUBLE GATE TRANSISTORS
(ADVANTAGES) As seen from the structure ofDouble Gate MOSFETs the gate area is
doubled, which provide better controlling of channel by gateelectrode(s).
Double gate structure provides some common advantages: Higher drain current
Higher gate to channel coupling
Lower short channel effects
Better scaling possibility
Fig. 4: General Double Gate St ructure
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DOUBLE GATE TRANSISTORS (PLANNER
DOUBLE GATE MOSFET) Short channel effects arise when control of the channel region by
the gate is affected by electric field lines from source and drain.
In a fully depleted SOI (FDSOI) device, most of the field lines
propagate trough the buried oxide (BOX) before reaching
the channel region (Fig. 5.B). Short channel effects in FDSOIdevices may be better
Fig. 5: Bulk
and FDSOIMOSFETstructure
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DOUBLE GATE TRANSISTORS (PLANNER
DOUBLE GATE MOSFET) Short channel effects can be reduced in FDSOI MOSFETs by
using a thin buried oxide and an underlying ground plane.
This approach, however, has the inconvenience of increased
junction capacitance and body effect.
In a double gate structure electric field lines from source and
drain underneath the device terminate on the bottom gate
electrode and cannot reach the channel region (Fig. 6.D)
Fig. 6: FDSOIwit h groundplane and DGMOSFET st ructure
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DOUBLE GATE TRANSISTORS
(ADVANTAGES OF PLANNER DG MOSFET) Some of the advantages of Planner DG MOSFET are:
Double Gate structure provides better immunity against
short channel effects.
Planner DG MOSFET fabrication is compatible with
conventional fabrication process chain.
DG structure provides approximately double drive current
than conventional single gate MOSFET.
Transconductance of DG MOSFET is found to be higher than
conventional single gate MOSFET.
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DOUBLE GATE TRANSISTORS (RECENT
ADVANCEMENTS) Various device design engineerings have been provided in
recent years to further improve the performance of DG
MOSFET, these are:
Channel engineering Gate engineering
Gate stack engineering
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DOUBLE GATE TRANSISTORS (CHANNEL
ENGINEERING) Channel engineering includes non-uniform doping of
channel region of substrate, a highlow doping profile is
shown in the figure.
Fig.7: Graded channelDouble Gate MOSFET
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DOUBLE GATE TRANSISTORS (CHANNEL
ENGINEERING) Advantages of Channel Engineering are:
Reduces threshold-voltage roll-off
Reduces hot-electron degradation
Reduces peak electric field at drain end Provides high drain current and high transconductance
Copy of Fig.7: Graded channelDouble Gate MOSFET
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DOUBLE GATE TRANSISTORS (GATE
ENGINEERING) Gate Engineering involves use of two (or more) different
metals, having different work functions as Gate
electrode.
Fig.8: Dual Metal GateDouble Gate MOSFET
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DOUBLE GATE TRANSISTORS (GATE
ENGINEERING) Advantages of Gate Engineering are:
High output impedance of the device
Lower peak electric field near drain region
High drain break down voltage High drain current and high transconductance
Copy of Fig.8: Dual Metal GateDouble Gate MOSFET
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DOUBLE GATE TRANSISTORS (GATE
STACK ENGINEERING) Gate Stack engineering involves use of different
dielectric material as gate insulator. A combination ofmore then one dielectric material is used for betterperformance.
Fig.9: Gate stacked Double Gate MOSFET
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DOUBLE GATE TRANSISTORS (VERTICAL
DOUBLE GATE MOSFET) Another member in double gate MOSFET device family is
Vertical Double Gate MOSFET (VDGM)
The VDG structure contains vertical channel rather than
horizontal as in planner DG MOSFET, both gates are placed
at opposite sides parallel to the channel while gate oxide
provides isolation between gates and body.
Fig.10: Vert icalDouble Gate MOSFET
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DOUBLE GATE TRANSISTORS (VERTICAL
DOUBLE GATE MOSFET) Advantages of vertical DG MOSFETs
The gate length is controlled by non-lithographic methods; this
allows the fabrication of sub-100nm channel length devices with
relaxed photolithography rules, reducing costs.
Better control of the substrates depletion region, in thin fully
depleted architecture dual gate pillars reduces the short channel
effects.
Vertical channel structure allows high device density, hence suitable
for high density ICs.
Both the gate terminal lies in the same plane, this makes controlling
and routing of the device easier.
Vertical DG MOSFET shows lower leakage current than DG MOSFET,
makes the device more power efficient and suitable for battery
operated VLSI systems.
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DOUBLE GATE TRANSISTORS (VERTICAL
DOUBLE GATE MOSFET) Recent Advancements
Recently I. Saad and P. Divya have presented a paper on
Vertical DG MOSFET using dielectric pocket and have shown
significant performance improvement in the device.
Fig.11: Vert icalDouble Gate MOSFETWith Di elect r ic Pocket
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DOUBLE GATE TRANSISTORS (VERTICAL
DOUBLE GATE MOSFET) Advantages of VDG MOSFET using Dielectric Pocket:
Use of dielectric pocket reduces the charge sharing problem
in Vertical DG MOSFET.
Dielectric pocket also reduces the electrical bulk
punchthrough effect.
DIBL effect is observed to be lower in DP device.
Drive current in DP Vertical DG MOSFET is shown to be
higher than typical Vertical DG MOSFET.
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CONCLUSION Multigate Transistors comes into existence to overcome
the roadblock made by Short Channel Effects in device
scaling.
Unique structures of Planner Double Gate MOSFET andVertical Double Gate MOSFET were presented.
Both device structures presented in this work have
separate advantages in terms of performance and
immunity against Short channel effects. Thus Double
gate transistors are proved to be more suitable for sub-100 nm technology.
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REFERENCES
1. J.P. Col inge, FinFETs and Other Mul ti -Gate Transistors, SpringerPublication, pp.1-37.
2. A. Amara, O.rozeau Planar Double-Gate Tr ansistor f rom technology to
circuit, Springer Publication, pp.1-20.
3. N. Mohankumar, B. Syamal, "Influence of Channel and Gate Engineer ing
on the Analog and RF Per formance of DG M OSFETs," IEEE Transaction
Electron Devices, vol 57, no. 4, Apri l 2010.
4. I . Saad, N. Bolong, Performance Design and Simulati on Analysis of
Ver ti cal Double Gate MOSFET (VDGM), UK Sim 13th Internati onal
Conference on M odel l ing and Simulation, 2011.
5. R. K. Sharma, M. Gupt a, and R. S. Gupta, TCAD Assessment of Device
Design Technologies for Enhanced Per formance of NanoscaleDG
MOSFET, IEEE Tr ansacti ons on Electr on Devices, vol. 58, no. 9,
September 2011.
6. http://www.intel.com/technology/mooreslaw/index.htm
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