F. A. CERN/EP 1
ANALOGUE CIRCUITS
TECHNIQUES
April 16th , 2002F. ANGHINOLFI
CERN
Part I
F. A. CERN/EP 2
Outline
• 1- Introduction to analogue circuit• 2- Active elements in Integrated Circuit• 3- The bipolar transistor
From “active” components available in modern IC
technologies, to the examples of amplifiers design
used for High Energy Physics applications
F. A. CERN/EP 3
Outline
• 4- Basic of amplifier• 5- Differential amplifier• 6- OTA• 7- Two-stage differential amplifier• 8- Other amplifiers circuits• 9- Cascode circuits• 10- Charge Preamplifier• 11- Transimpedance Preamplifier• 12- Preamplifiers conclusions
F. A. CERN/EP 4
1- Introduction to analogue circuit
We will NOT talk about :
• A lot of different circuit configurations used for applications in HEP, or outside of HEP (broadband telecommunications, HF, audio, etc …)
• A lot of parameters which may widely influence a final circuit design (like DC operating point, offsets, internal noise sources, sensitivities to external sources, components non-uniformities, etc …)
We will MAINLY talk about :
• Some major aspects of linear amplifier design : building blocks, amplifier stability, amplifier gain, signal bandwidth
• Two examples of signal amplifiers circuits developed for detector front-end
F. A. CERN/EP 5
1- Introduction to analogue circuit
REFERENCES:
books
IC technology “Physics in Semiconductor Devices”S. M. Sze, Wiley
Amplifier design “Analog Integrated Circuits”Paul. R. Gray, Robert. G. Meyer, Wiley
httphttp://www.prenhall.com/howe3/microelectronics/
Detector Amplifierdesign
“Low-Noise Wide-band Amplifiers in Bipolar and CMOS technologies”Z. Y. Chang, Willy M.C. Sansen, Kluwer Academic Publishers
F. A. CERN/EP 6
1- Introduction to analogue circuit
Id
Gnd
Vdd
R
Vin
Vout
Id
Gnd
Vdd
Vin
VoutN
P
Vin=Gnd (0) or Vdd (1)Vout = Vdd(1) or Gnd(0)
NON LINEAR SYSTEM
Digital circuit
Analog circuit
Vout=f(Vin)Vin and Vout can take any value
between Vdd and GndLINEAR SYSTEM
F. A. CERN/EP 7
1- Introduction to analogue circuit
Digital circuit
Analog circuit
Highly non linear
High noise immunity*
Immune to power supply variations*
Carries only one bit of information
Highly linear
Sensitive to noise (… pickup, crosstalk …)
Sensitive to power supplies
Carries n bits of information **
* = up to certain limits ! ** = function of max. signal range versus noise level
threshold
threshold
F. A. CERN/EP 8
2- Active Components in Integrated Circuit
MOS TRANSISTOR BIPOLAR TRANSISTOR
Surface effect conduction under the control of the gate potential
Volume effect conduction under the control of the junctions potential
IE
Ic
IB
npn
Id
NVg
F. A. CERN/EP 9
2- Active Components in Integrated Circuit
MOS TRANSISTOR BIPOLAR TRANSISTOR
TBE UVIsIc /exp.=( )20 .. VtVgs
LW
KId −=
qTk
UT⋅
=
Ko=f(mobility, gate capacitance, T, …)
Vt=f(dopant, gate capacitance, fixed charges, …)
W/L=transistor aspect ratioOnly “fundamental” quantities
(k= Boltzman constant, T= Temp., q= electron charge)
F. A. CERN/EP 10
3- The Bipolar Transistor
FIRST SOLID STATE TRANSISTOR(1947)
BARDEEN, BRATTAIN AND SHOCKLEY
F. A. CERN/EP 11
3- The Bipolar Transistor
A pn-junction in Silicon is the abutment of two Si volumes with free carriers of opposite polarities
• Majority carriers diffuse from regions of high to regions of low concentration
• An electric potential is created, which counteracts the diffusion current (drift current)
• In equilibrium there is no net flow of carriers in the diodeP N
Holes (+) Electrons (-)
φ
Depletion region
p-n junction
F. A. CERN/EP 12
3- The Bipolar Transistor
CathodeAnode
n+
p-substrate
Al SiO2
Cathode
Anode
n+
p
+ ++ +
--- - φο
+
-
Diffusione
h
h
e
Drift
Depletion region
p-n junction
F. A. CERN/EP 13
3- The Bipolar Transistor
• Under zero bias there is a built-in potential across the junction
• The built-in potential is:
⋅⋅=
2ln0
inDNAN
TUφ
K300 @ mV 26 °≅⋅
=qTk
UT
ni = × °15 1010. cm for silicon @ 300 K-3
p-n junction
F. A. CERN/EP 14
3- The Bipolar Transistor
• For V>φT (forward bias)
• For V<0 (reversed bias)
-0.2 0 0.2 0.4 0.6 0.810-18
10-16
10-14
10-12
10-10
10-8
10-6
10-4
10-2
Bias voltage (V)
Dio
de c
urre
nt (
A/µ
m2 )
Ideal
Reverse biasleakage current
TUVsF eII /⋅≅
I IR s≅ −
p-n junction
F. A. CERN/EP 15
3- The Bipolar Transistor
Base-EmitterJunction is forward biased
Collector-BaseJunction is reverse biased
Barrier is lowered : more electrons (min. carriers) diffuse to the base, may reach the opposite junction, and contribute to the current of the reverse_biased BC junction
E
B
Cn p n
Minority carriers (electrons diffusion into the base)
No Bias
B-E maj. carriers flow (holes)
Bias applied
F. A. CERN/EP 16
3- The Bipolar Transistor
0 + ++Base-Emitter
Junction is forward biasedCollector-Base
Junction is reverse biased
n p n
E
B
Cn p n
e
h e
h
h
e
F. A. CERN/EP 17
3- The Bipolar Transistor
Conduction mechanism in a bipolar transistor is made of the MINORITY CARRIERS flowing through the base region
Currents are flowing through semiconductors junctions, within the crystalline structure. Not a surface effect.
F. A. CERN/EP 18
3- The Bipolar Transistor
E
B
Cn p n
A B
No Bias
Forward biased Base-EmitterJunction
Higher « reverse »current in reverse
biasedCollector-Base
Junction
Bias applied
F. A. CERN/EP 19
3- The Bipolar Transistor
• Currents in junctions A and B are almost equal.
• B-E junction (A) is forward biased (low impedance)
• C-E junction (B) is reverse biased (high impedance)
Why is bipolar effect an « amplifying »device ?
The collector node being high impedance (current source). It can be loaded with large resistors RhighThe output power is Rhigh.I2
The emitter node is low impedance. The power at emitter node is Rlow.I2
The output power (at collector) is higher than the input power (at emitter)
F. A. CERN/EP 20
3- The Bipolar Transistor
Minority carriers concentration at x=0
Np0 is the intrinsec minority carrier concentration in the base and
K is the boltzmann constantq the electron chargeT is temperature
= 26mV at 300K
( )T
BEpp U
Vnn exp0 0=
qkT
UT =
qkT
UT =
(diffusion carrier density equation)
F. A. CERN/EP 21
3- The Bipolar Transistor
The collector current is the result of the minority carrier concentration in the base crossing the B-E junction due to the electrial field direction
A is cross section of the emitterDn is the diffusion constant for electrons (the minority carriers in NPN device)
With the equation of np(0)
np0 is the intrinsec minority carrier concentration in the base
( )B
pn W
nqADIc
0=
T
BE
B
pn
UV
W
nqADIc exp0=
F. A. CERN/EP 22
3- The Bipolar Transistor
Both IC and IB depend on the same term :
The ratio Ic/Ib is called « forward current gain » :
T
BE
D
i
P
P
B
pBB U
VNn
LqADn
qAWI exp21 2
0
+=
τ
T
BE
UV
exp
D
i
P
P
B
pB
B
pn
Nn
LqADn
qAW
W
nqAD
20
0
21
+=
τ
β
The base current IB is the result of two current (holes in case of NPN) contributions (namely diffusion current in emitter and recombination current within the base):
F. A. CERN/EP 23
3- The Bipolar Transistorβ, the current gain between collector and base :
By maximizing NA/ND ratio,and minimizing WB, the base width, it is possible to reach values of β=50-200
IE
Ic
IBnpn
Transconductance :
D
A
p
B
N
P
BN
B
NN
LW
DD
DW
+=
τ
β 2
21
1
TBE UVIsIc /exp.=
BIIc β=
BBE IIIcI )1( +=+= β
TBE
UIcVIc
/=∆∆
F. A. CERN/EP 24
3- The Bipolar Transistor
Exp. Increase
Ic vs. VCE Characterisitc
Ic
IE
IBnpn
VCE
TBE UVIsIc /exp.=
TBE
UIcVIc
/gm =∆∆
=vbe
ic
Zogm.vbe(∆Vbe)
(∆Ic)
Zi
Small signal model
(note : in all transparencies, explicit “-” sign is ignored)
F. A. CERN/EP 25
Reminder : The MOS Transistor
Power 2 Increase
Id vs. Vds Characteristics
vgs
id
Zogm.vgs(∆Vgs)
(∆Id)
Zi
Small signal model
Id
NVgs
( )20 .. VtVgs
LW
KId −=
dod I
LW
KVgsI
..2gm =∆∆
=
F. A. CERN/EP 26
Linear models for Bipolar or MOS Transistor
v
i
Zogm.v(∆V)
(∆I)
Zi
Small signal model
For most linear applications, both MOS or bipolar are represented by similar model elements
Values inside the model are different :
Process dependentMax.gmHigh RHigh RZo
High CLow RZiMOSBipolar
F. A. CERN/EP 27
4- Basic of amplifier
Ic
IE
IB npn
Gnd
Vcc
R
The simplest amplification circuit
Vbe
co IRVccV .−=
UtVbesc eII /.=
The collector of the npn transistor behaves as a current source : delivery of current “Ic”from a high impedance node
The voltage gain is given by Vo variation vs.Vbe variation
Vo
F. A. CERN/EP 28
4 - Basic of amplifier
Ic
IE
IB npn
Gnd
Vcc
R
Vbe
The voltage gain is given by Vo variation vs.Vbe variation
co IRVccV .−= co IRV ∆=∆ .
UtVbesc eII /.=
UtI
eIUtVbe
I cUtVbes
c ==∆∆ /..
1Vo
F. A. CERN/EP 29
4 - Basic of amplifier
Ic
IE
IB npn
Gnd
Vcc
R
Vbe
The voltage gain is given by Vo variation vs.Vbe variation
UtI
VbeI cc =
∆∆
Is called the transconductance ‘gm’
UtI
RVbeV co .=
∆∆
R.gm=∆∆VbeVo
Vo
F. A. CERN/EP 30
4 - Basic of amplifier
Ic
IE
IB npn
Gnd
Vcc
R
Vbe
R.gm=∆∆VbeVo
Typical values :
UtIc=gm
CdemVqkTUt .25@26==
mAIc 1=
KohmsR 1=
mS5.38gm =
5.83=∆∆VbeVo
Vo
F. A. CERN/EP 31
4 - Basic of amplifier
Ic
IE
IB npn
Gnd
Vcc
R
Vbe
npn
vbe
ic
Can be represented by a “small-signal model”
vbe
ic
Rogm.vbe(∆Vbe)
(∆Ic)
Ri
Ri, Ro represent the input and output impedances of the non-idealtransistor
Vo
F. A. CERN/EP 32
4 - Basic of amplifier
Ic
IE
IB npn
Gnd
Vcc
Z
Vbe
“small-signal model”
vbe voRo//ZGm.vbe(∆Vbe) (∆Vo)
Ri
Ri, Ro represent the input and output impedances of the non-idealtransistor
Vo
F. A. CERN/EP 33
4 - Basic of amplifier
Ic
IE
IB npn
Gnd
Vcc
R
Vbe
vbe vo
Ro
Gm.vbe(∆Vbe) (∆Vo)
Ri
Vo
A very simple Gain-Bandwidth calculation model
C
R C
Usually Ro (output impedance of transistor) is much higher than R. The output stage has one single pole created by the resistive load (which defines gain) and the capacitive load.
)
sC1
R
sC1
R.( . gm
vv
i
0
+=
F. A. CERN/EP 34
4 - Basic of amplifier
Ic
IE
IB npn
Gnd
Vcc
R
Vbe
Vo
C
The circuit gain at low frequency is : gm.R (as expected)
The circuit transfer function has one pole at τ =RC
The circuit bandwidth limit (Gain >1) is at :
)sRC11
R.( . gmvv
i
0
+=
C . gm -1=cτ
F. A. CERN/EP 35
4 - Basic of amplifier
Ic
IE
IB npn
Gnd
Vcc
R
Vbe
Vo
C
C . gm -1=cτ
Gm.R1
Gm.R2
1/τ(log scale)
Gain (vo/vi) dB
1/R1.C 1/R2.C0
1/τc
The maximum bandwidth of gain circuit with one pole is given by the input device transconductance and capacitive load.
Example : gm = 10-2, C=1pF, τc=100ps, fc=1.6GHz
F. A. CERN/EP 36
4 - Basic of amplifier
The simplest amplification circuit with a MOS transistor instead of a bipolar one.
dddo IRVV .−=
( )20 .. VtVgs
LW
KId −=
The drain of the MOS transistor behaves as a current source : delivery of current “Id”from a high impedance node
The voltage gain is given by Vo variation vs.Vgs variation
Id
Gnd
Vdd
R
Vgs
Vo
F. A. CERN/EP 37
4 - Basic of amplifier
The voltage gain is given by Vo variation vs.Vgs variation
do IRV ∆=∆ .
VgsIL
WKI dod ∆=∆ ...2
( )20 .. VtVgs
LW
KId −=
Id
Gnd
Vdd
R
Vgs
Vo “gm” transconductance of MOS device
F. A. CERN/EP 38
4 - Basic of amplifier
The voltage gain is given by Vo variation vs. Vgs variation
R.gm=∆∆VgsVo
Id
Gnd
Vdd
R
Vgs
Vo
do IL
WK ..2gm =
F. A. CERN/EP 39
4 - Basic of amplifier
R.gm=∆∆VgsVo
Typical values for modern MOS technology:
mAId 1=
KohmsR 1=
mS8.7gm =
8.7=∆∆VgsVo
Id
Gnd
Vdd
R
Vgs
Vo
dod I
LW
KVgsI
..2=∆∆
260 /10.150 VAK −= 100=
LW
F. A. CERN/EP 40
4 - Basic of amplifier
Id
Gnd
Vdd
R=rds
Vgs
Vo
The resistor load can be replaced by a transistor working as a current source.
The high output impedance (drain of PMOS) is used as the load.
VARIANT WITH “ACTIVE LOAD”
Vbias
N
P
Small signal model
vgs
ids
rdsgm.vgs
Transconductance factor
Output Impedance
P
vgs=0
vds
F. A. CERN/EP 41
4 - Basic of amplifier
VARIANT WITH “ACTIVE LOAD”
vgs
ids
rdsgm.vgs
Transconductance factor
Output Impedance
D
S
Vds
Ids
∆ids/∆vds is small -à Equivalent output resistance is high (usually 50K to 1Mohms)
F. A. CERN/EP 42
4 - Basic of amplifier
Id
Gnd
Vdd
Vgs
Vo
VARIANT WITH “ACTIVE LOAD”
Vbias
N
P
vgs rdsNgm.vgs
Transconductance factor
Output Impedance
rdsP
R=rdsP
gm.rdsG = rdsN//rdsPrds =
rds is usually large (>50K-1M ohms). Gain G reaches ~100 (40dB)
and
F. A. CERN/EP 43
4 - Basic of amplifier
Id
Gnd
Vdd
R
Vgs
Vo
• Output is sensitive to Vdd/Gnd fluctuation (poor Power Supply Rejection)
• Output DC is related to input DC levels (no Common Mode Rejection)
SINGLE-ENDED STRUCTURE
F. A. CERN/EP 44
5- Differential Amplifier
Gnd
Vdd
Vi2
Id1
R
Id2
R
2*Id
Vi1
Vo1 Vo2
Vc
Because of the weaknesses of the single-ended structure (common-mode and power supply sensitivity), the differential amplifier is usually a preferred structure
F. A. CERN/EP 45
5 - Differential Amplifier
From MOS transistor equations :
Formulate :
Vcm 2Vid Vi1 +=
Vcm 2Vid- Vi2 +=
Gnd
Vdd
Vi2
Id1
R
Id2
R
2*Id
Vi1
Vo1 Vo2
Vc
Vid is the differential signal at inputVcm the input signal common modeVc the voltage to transistor source
2Vt)-VcVcm2Vid(.LW
k0. Id1 −+=
2Vt)-VcVcm2Vid(-.LW
k0. Id2 −+=
F. A. CERN/EP 46
5 - Differential Amplifier
Small signal Formulation, diff. Input variation :
Gnd
Vdd
Vi+
Id1
R
Id2
R
2*Id
Vi-Vo1 Vo2
Vc
Vid is the differential signal at inputVcm the input signal common modeVc the voltage to transistor source
2VidVt).-Vc-(Vcm.LW
k0. .2id1 =
2VidVt).-Vc-(Vcm.LW
2.k0.- id2 =
id1)-R(id2Vo1Vo2? Vo =−=
Vt).Vid-Vc-Vcm.(LW
2.R.k0. ? Vo =
Differential Gain :
F. A. CERN/EP 47
5 - Differential Amplifier
Gnd
Vdd
Vi+
Id1
R
Id2
R
2*Id
Vi-Vo1 Vo2
Vc
Vid is the differential signal at inputVcm the input signal common modeVc the voltage to transistor source LWko.
IdVt)-Vc-Vcm( =
Vid..IdLW
k0.2.R. ? Vo =
.IdLW
k0.2. gm =Is the input transistorstransconductance
We end up with the differential gain expressed as :
R.gm=G
F. A. CERN/EP 48
5 - Differential Amplifier
Gnd
Vdd
Vi+
Id1
R
Id2
R
2*Id
Vi-Vo1 Vo2
Vc
Vid is the differential signal at inputVcm the input signal common modeVc the voltage to transistor source
Small signal Formulation, Common Mode Input variation :
Common Mode Gain :
)v-Vt).(v-Vc-(Vcm.LW
k0. .2id1 ccm=
)v-Vt).(v-Vc-(Vcm.LW
k0. .2id2 ccm=
If the tail current source is perfect (very high Z) :
0id2id1 =+ 0id2 and 0id1 ==
Vo outputs are insensitive to common mode input
F. A. CERN/EP 49
5 - Differential Amplifier
Gnd
Vdd
Vi+
Id1
R
Id2
R
2*Id
Vi-Vo1 Vo2
Vid is the differential signal at inputVcm the input signal common modeVc the voltage to transistor source
Common Mode Gain :
If the tail current source has impedance Rss
Rss
2gmRss1R.gm
vv
cm
o
+=
This is the common mode gain, which is much less than the differential gain, approx. by the factor R/(2Rss).
The ratio of the differential gain to the common mode gain, is called the Common Mode Rejection Ratio (CMRR). In our case :
2gmRssCMRR ≅(CMRR easily reaches 1000 (60db))
F. A. CERN/EP 50
5 - Differential Amplifier
Gnd
Vdd
Vi+
Id1
R
Id2
R
2*Id
Vi-Vo1 Vo2
Vc
By similar reasoning, it can be shown that the differential structure can provide :
• High Common Mode Rejection
• High Power Supply Rejection
The other features are :
• Differential gain formulation as for single-ended
• Constant power consumption
F. A. CERN/EP 51
5 - Differential Amplifier
Gnd
Vdd
Vi+
Id1
R
Id2
R
2*Id
Vi-Vo1 Vo2
Vc
Drawback: Noise increase by factor 2
Id
Gnd
Vdd
R
Vgs
Vo
When noise level is critical, as in case of small detector signals, the single-ended option is the preferred choice.
It is at the cost of higher sensitivity to common-mode and power supply noise.
F. A. CERN/EP 52
• Limited “open loop” gain
• Open-loop Gain, DC point and Output Impedance are correlated by R
• “one-pole” system assumes stability
5 - Differential Amplifier
Gnd
Vdd
Vi+
Id1
R
Id2
R
2*Id
Vi-Vo1 Vo2
Vc
Typical Example :
R.gm=G
10KR10gm 3
== −
!10=G
F. A. CERN/EP 53
• The resistive load “R” is replaced by an active device (transistor) of transconductance gm2
•The amplifier is only made of complementary transistors (Pmos, Nmos).
• “MOS-only” circuit makes it compatible with most standard digital process.
6 - Active Load ; OTA
Gnd
Vdd
Vi+
rds2
2*Id
Vi-Vo1 Vo2
Vc
gm1.rdsG =
gm1,rds1
VbiasVbias
rds1//rds2rds =
100≥G
F. A. CERN/EP 54
In this configuration, the current in the output branch (ido) is the difference between the two currents variations in the two input devices :
6 - Active Load ; OTA
Gnd
Vdd
Vi-
id1
2*Id
Vi+Vo
Vc
id1
Current MirrorID = Ko.W/L.(Vgs-Vt)2
)gm1.(viid1 +=)gm1.(viid2 −=
)vigm1.(ido ∆= (∆vi being the differential input voltage)
id2id0
Thus the output voltage variation vo is given by
viRout.gm1.Rout.ido vo ∆==
rds2
gm1,rds1
F. A. CERN/EP 55
This amplifier configuration is the typical circuit of amplification stages in CMOS technology
• It provides differential inputs to single-ended output
• It has high “DC” gain (opamp) as it is shown in next transparencies
• “one-pole” system (stable)
6 - Active Load ; OTA
Gnd
Vdd
Vi-
2*Id
Vi+Vo
Vc
id1
Current Mirror
id2id0
A-
+rout.gm1G =
What is rout ?
id1rds2
gm1,rds1
F. A. CERN/EP 56
6 - Active Load ; OTA
Gnd
Vdd
Vi-
2*Id
Vi+Vo
Vc
id1
Current Mirror
id2id0
rout.gm1G =
routgm1.∆vi
ids
∆vi
The output impedance is the equivalent impedance seen from the output node, i.e. :
routrds1//rds2 =
The output impedance is usually high (50K to 500K), thus one-stage gain is high (gm=1mS, rout= 500K -à G=500 !)
rout calculation
id1rds2
gm1,rds1
F. A. CERN/EP 57
6 - Active Load ; OTA
Gnd
Vdd
Vi-
id1
2*Id
Vi+
Vo
Vc
id1
Current Mirror
id2id0
rout.gm1GDC =
routgm1.∆vi∆vi
This amplifier behaves as an opamp. Large gm gives high DC gain. Main pole is fixed by the output (rout.CL )time constant.
Gm1.rout
1/τ(log scale)
Gain dB
1/rout.CL0
1/τc
CL
CL
Unity Gain BWat gm-1.C
F. A. CERN/EP 58
6 - Active Load ; OTA
Gnd
Vdd
Vi-
id1
2*Id
Vi+Vo
Vc
id1
Current Mirror
id2id0
Drawback of this circuit : its limited open-loop DC gain G . If used with a feedback gain β, the output impedance is given as :
N.A. : G=500, β=0.1 -à Zout = 10K ohms
It is not suitable for resistive load (50 to 1Kohms range).
.G1
.routZout OL β≈
It fits well for application with pure capacitive load, where low output impedance or large current are not required (many examples in switched capacitor circuits, SC filters).
F. A. CERN/EP 59
7 - Two Stage Differential Amplifier
Gnd
Vdd
Vi-
id1
2*Id
Vi+
Vo
Vc
id1 id2
Add single-ended second stage
gm1
gm2
Io
2nd stage can draw a large current (gm2 large)
2.1GGDC G=
gm1.rout1G1 =gm2.rout2G2 =
N.A : gm1 = 0.5mS gm2 = 3mSrout1 = 1M rout2= 200K
=è GDC=30000 (90 dB)
Output impedance. : G=30000, β=0.1 -à Zout = 66 ohms
F. A. CERN/EP 60
7 - Two Stage Differential Amplifier
Gnd
Vdd
Vi-
id1
2*Id
Vi+
Vo
Vc
id1 id2
There are two poles
gm1
gm2
Io
First pole : rout1.CL1
Second pole : rout2. CL2
G(dB)
1/τ(log scale)1/R1.CL1 1/R2.CL2
0
-20dB/dec
INSTABILITY
CL2
CL1
Due to very high gain, the gain at the two pole is above 0dB
(closed loop gain)
F. A. CERN/EP 61
7 - Two Stage Differential Amplifier
Gnd
Vdd
Vi-
id1
2*Id
Vi+
Vo
Vc
id1 id2
Miller Capacitance Cf
gm1
gm2
Io
The Cf capacitance is seen by first stage as load of value (Miller effect)
First pole : rout1.CMSecond pole : rout2. CL2
G(dB)
1/τ(log scale)1/R1.CM 1/R2.CL2
0
CL2
CL1
(closed loop gain)
Cf
Cfgm2.rout2.CM ≈
The 2nd pole is below 0dB
STABILITY
(without Cf)
F. A. CERN/EP 62
7 - Two Stage Differential Amplifier
Gnd
Vdd
Vi-
id1
2*Id
Vi+
Vo
Vc
id1 id2
gm1
gm2
Io
Cf
This circuit has the characteristics to behave as a “good” operational amplifier
High Input Impedance (Capacitive only)
High DC Gain (70-90dB)
Low output impedance
N.A. : G=30000, β=0.1 -à Zout = 66 ohms
Widely used circuit. Lot of variations exist (improved output stage, Gain enhancement etc …)
Stability should always be considered carefully(also depends on feedback and load)
F. A. CERN/EP 63
7 - Two Stage Differential Amplifier
Gnd
Vdd
Vi-
id1
2*Id
Vi+
Vo
Vc
id1 id2
gm1
gm2
Io
Cf
We did not considered other parameters which have equally large influence on the amplifier design aspects :
In the preceding discussion we considered only one (main) aspect of the amplifier design (gain and stability)
• DC operating point
• Noise figure & dynamic range (S/N ratio)
• Mismatch & Offsets
• Slew rate, large signal behavior
• Power budget
F. A. CERN/EP 64
7 - Two Stage Differential Amplifier
• DC operating point : The condition in which each transistor is biased to satisfy its “small signal model”
• Noise figure & dynamic range (S/N ratio) see figure
• Mismatch & Offsets : how technological or geometrical discrepancies between two identical components affect DC or AC characteristics
• Slew rate, large signal behavior : absolute limits given by DC conditions
• Power budget : increasing speed (BW) usually means increasing current (gm ~ funct(I))
Max signal swing, limits by DC op. conditions
Noise levelnoise sources
F. A. CERN/EP 65
8 - Other amplifier circuits
Id
Gnd
Vdd
Vgs
Vo
• High Input Impedance
• Voltage gain
• High ouput impedance
Common Source
Vbias
rout.gm1GDC =
routrds1//rds2 =
∞=Rinrds2
rds1gm1
F. A. CERN/EP 66
8 - Other amplifier circuits
Id
Gnd
Vdd
Vbias1Vo
• Low Input Impedance
• Voltage gain
• Unity current gain
• High ouput impedance
Common Gate
Vbias2
rout.n.gm1GDC =
routrds1//rds2 =
1(n.gm1)Rin −=
Vin
(n is a factor specific to the technology, between 1 and 1.5)
rds2
rds1gm1
F. A. CERN/EP 67
8 - Other amplifier circuits
Gnd
Vdd
Vbias1Vo
• High Input Impedance
• (close to) Unity Voltage gain
• “low” output impedance
Common Drain(Source Follower)
Vin
gm21rout ≈
∞=Rinrds2gm2
rds1
F. A. CERN/EP 68
9 – Cascode circuit
Gnd
Vdd
Vgs
Vo=gm1.rout
Vbiasrds2
rds1gm1
Gnd
Vdd
Vgs
Vbiasrds2
rds1gm1
Vcasrdscgmc
Vo=gm1.rout
Cp
Miller effect
CPC
Low impedance node (1/gmc)CP
Single ended, without cascode Single ended, with cascode
The cascode element provides isolation of input to output
F. A. CERN/EP 69
9 – Cascode circuit
Gnd
Vdd
Vgs
Vbiasrds2
Vcasrdscgmc,
CPC
(1/gmc)CP
rds1gm1,
Impedance seen from output node toward Gnd is : rds1.(1+gmc.rdsc)
Voltage gain is given as :
G=gm1.rout
With rout=rds2//rds1.(1+gmc.rdsc)
As gmc.rdsc is large (50 to 100)
gm1.rds2GDC ≈
F. A. CERN/EP 70
9 – Cascode circuit
Gnd
Vdd
Vgs
Vbiasrds2
Vcasrdsc1gmc1,
CPC
(1/gmc)CP
rds1gm1,
Impedance seen from output node toward Gnd is : rds1.(1+gmc1.rdsc1)
With rout = rds2(1+gmc2.rdsc2) //rds1.(1+gmc1.rdsc1)
DC gain can be very large in one stage (>60db)
gm1.routGDC =
Impedance seen from output node toward Vdd is : rds2.(1+gmc2.rdsc2)
rdsc2gm2c,
F. A. CERN/EP 71
9 – Cascode circuit
Impedance seen from output node is rds3//rds1.(1+gmc.rdsc)
rout=rds3//rds1.(1+gmc.rdsc)
gm1.routGDC ≈
The folded cascode circuit
Gnd
Vdd
Vgs
VbiasPrds2
rdscgmc,
(1/gmc)
rds1gm1,
VbiasN
Vcas
Out
rds3
F. A. CERN/EP 72
9 – Cascode circuit
The folded cascode circuit
Gnd
Vdd
Vgs
VbiasPrds2
rdscgmc,
(1/gmc)
rds1gm1,
VbiasN
Vcas
Out
This circuit arrangement has virtually many advantages :
• High DC gain
• One pole system (2nd pole is at very high frequencies). Stability improves if capacitive load is increasing.
• DC operating points at input and outputs are similar
One drawback :
• Limited output voltage swing
rds3
F. A. CERN/EP 73
9 – Cascode circuit
The folded cascode circuit
Gnd
Vdd
Vgs
VbiasPrds2
rdscgmc,
(1/gmc)
rds1gm1,
VbiasN
Vcas
Out
This circuit is the basic one used for charge preamplifier design in
detector readout
gm1.routGDC ≈ rout=rds3//rds1.(1+gmc.rdsc)
Gm1.rout
1/τ(log scale)
Gain dB
1/rout.CL0
1/τc
Unity Gain BWat gm-1.C
rds3
F. A. CERN/EP 74
End of First Part
What we have presented:
The Bipolar device as an amplifying component
Basic amplifiers schemas (Bipolar or MOS components)
General purpose two stage amplifier
Differential vs. Single-Ended
What we will do in 2nd part:
Look at two detector signal preamplifier configurations(charge sensitive amplifier and transimpedance amplifier)