AMD Quad Core Barcelona MPU
August 31, 2007August 31, 2007
Don ScansenDon Scansen
Technology AnalystTechnology Analyst
Semiconductor InsightsSemiconductor Insights
2Barcelona Die – Close-up on Two Cores
Core 1Core 1Core 1 Core 2Core 2Core 2
3
Core 1 Core 2
Core 4Core 3
DDR2 /DDR3
Nort
hbridge
L3 Cache
Barcelona Architecture
4
L1 data
cacheL1 instruction cache
L2
128 bit FPU
L2 control
Instruction
fetch and decodeCode
execution
Load and
store
Processor Core Design
5
Quad Core Die Architecture
•AMD’s Advantage
– Native quad core for faster CPU without scaling technology
– Affordable solution
– Large L3 cache is shared, optimizing memory use
– Northbridge memory controller on die
•Intel’s Advantage
– Intel set to launch 45nm dual core Penryn line
– Intel will package two dual cores together as they do now to offer a “quad” device
6
AMD 65nm Transistor Structure
Nickel
silicide
Tensile stress liner
Poly gateSidewall
spacers
Channel
Contact
NFET
7
Dislocation Defect
Dislocation between silicon
atomic planes
8
L2 and L3 6T SRAM unit cell:0.54µm X 1.47µm = 0.79µm2
SRAM Cache Design
9AMD and Intel Head-to-Head (before Penryn Launch)
8.25MB4.5MBTotal Memory Cache
65nm Bulk DSL, e-SiGe, 8M Cu
65nm SOI DSL, e-SiGe, 11M Cu
Process
0.72µm20.79 µm2Cell Size
284mm2 (142 X 2 die)284mm2Die Size
Intel Quad Core Kentsfield
AMD Barcelona Native Quad
Core
10
After Intel’s Penryn Launches
?
11
What’s next?
• Will AMD’s success come down to core on die versus core in package?
• When will Intel produce a quad die?
• Will Intel stay ahead by leveraging its manufacturing prowess and packaging multiple MPU dies within a single package?