Xilinx Advanced Products Division Virtex-4 Overview Version 2.1 March 2005

Xilinx Advanced Products Division

Virtex-4 Overview

Version 2.1March 2005

Virtex-4 Overview Module 2

4th Generation Virtex

Built on a Solid Foundation of Success


Most Advanced Process Technology

• Advanced 90-nm process

• 11-layer copper metallization

• New Triple-Oxide technology– Enables lower quiescent power

consumption

• Exclusive benefits:– Best cost– Greatest performance– Lowest power– Highest density

Enables 2x performance, 2x capacity, ½ power, ½ costEnables 2x performance, 2x capacity, ½ power, ½ costEnables 2x performance, 2x capacity, ½ power, ½ costEnables 2x performance, 2x capacity, ½ power, ½ cost


The Most Advanced Parallel I/O Interfacing Capability

• Universal connectivity– Support for 26 electrical standards– ChipSync™ technology– XCITE DCI

• Extreme performance– Up to 1 Gbps LVDS– Up to 600 Mbps single-ended

• Widest set of supported standards– PCI, PCI-X, SFI-4, HSTL, SSTL,

LVCMOS, LVTTL…


Breakthrough ChipSync™ Technology

• Pre-Engineered source synchronous logic– Embedded in All I/O

• Key advantages– Easier design– Higher performance– Resource savings DDRDDR

MemoryMemoryDDRDDR

MemoryMemory

SPI 4.2SPI 4.2SPI 4.2SPI 4.2

Pre-

Desig

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Built-

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SIO

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Pre-

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Built-

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IO SERDESIO SERDESIO SERDESIO SERDES• Frequency division• Serialize/Deserialize

Precision DelayPrecision DelayPrecision DelayPrecision Delay• Bit/Word Align, DPA

IO ClockingIO ClockingIO ClockingIO Clocking• I/O clocks• Regional clocks• Clock-capable I/Os


XCITE Digitally Controlled Impedance

• 3rd generation DCI– Series, parallel, differential

termination– Temperature / voltage

compensation• Fewer resistors on-board• Easier PCB design• Termination at

source or load• Works in conjunction with I/O

standards – Examples: HSTL, SSTL, etc.

Many Many Selectable Selectable

OptionsOptions

Many Many Selectable Selectable

OptionsOptions


SONETSONET

• Virtex-4 RocketIO™ transceivers– Full-duplex serial transceiver blocks

with integrated SERDES and Clock and Data Recovery (CDR)

• 622 Mbps to >10 Gbps operation– Widest Range of Operation

• Compatible with Virtex-II Pro• Supports chip-to-chip, backplane,

chip-to-optics

The Most Advanced Serial I/O


SupportSupport

NetworkingNetworkingNetworkingNetworking

TelecomTelecomTelecomTelecom

ComputingComputingComputingComputing

StorageStorageStorageStorage

VideoVideoVideoVideo

0.622 1.0 2.0 3.0 5.0 10.0 11.0

OC-12OC-12OC-48OC-48

GbEGbE XAUIXAUI10GbE10GbE

CEI (OIF)CEI (OIF)

SATA3SATA3SATA2SATA2SATASATA

1GFC1GFC 2GFC2GFC

PCIEPCIE

HD-SDIHD-SDI

SATASATA

GbEGbE

1.45

1.25 2.5

1.5 3.0

0.622

2.488

3.1251.25 6.25

1.5 3.0 6.0

1.06 2.1210GFC10GFC

6.0

10.519

SATA2SATA2

Rate (Gb/s)

CEI (OIF)CEI (OIF)

4GFC4GFC4.25

8GFC8GFC8.5

Serial I/O Challenges

10.313

11G

OBSAIOBSAI0.768-1.5 CPRICPRI

0.622 - 2.5

PCIE Gen2PCIE Gen25-6

Virtex-4 Serial I/O Solution


Smart RAM Memory Hierarchy

Required Memory Capacity


Fast and Flexible BRAM

• Enhanced architecture for higher performance– 500 MHz performance

• Optional programmable FIFO logic – Saves logic resources– 500 MHz FIFO performance

• Tunable Block Structure– Scalable and efficient

memory utilization– Design compatible with Virtex-II Pro


World-Class Clocking

• High-performance– Up to 500 MHz system clock– Up to 700 MHz source

synchronous clock

• Powerful DCM clocking– Zero-delay buffer– Phase-shift control– Frequency synthesis

• More resources– Up to 20 DCMs– 32 global clocks


Virtex-4 Clock Management: Powerful Solutions

• Simplified system design– Abundant resources– Application-targeted features– Comprehensive software support

• Increased system performance– Lower jitter and duty cycle distortion – 500 MHz clock generation and control

Clocking features, performance, and flexibility Clocking features, performance, and flexibility unmatched by any other FPGAunmatched by any other FPGA

Clocking features, performance, and flexibility Clocking features, performance, and flexibility unmatched by any other FPGAunmatched by any other FPGA


Next Generation

• Optional accumulator / adder– Multiply add, multiply accumulate, or

complex multiply• Optional pipeline registers

– 2x-10x the performance of alternative solutions

• Cascadable– Combine DSP Slices at Full Speed

• Highest DSP performance– Up to 500MHz True 18-bit x 18bit

MACC Performance


Next Generation

4848

48

Subtract

P

RSTA

18

PCIN

0

PCOUT

C

BCOUT

BCIN

B

CarryIn

0

072

RSTM

A:B 36

Y

Z

OpMode7

18

48

48

17-bit shift

17-bit shift

48

1

0

0

1

36

36

18

X

CEM

CE

MREG

D Q

RSTP

CEP

CE

PREG

D Q

CEB CE

BREG

D Q

CEA CE

AREG

D Q

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2-Deep

2-Deep


Achieve DSP Efficiency in Virtex-4

• Virtex-4 XtremeDSP – Performance

• 512 XtremeDSP slices at 500MHz• 256 GMACCs/s DSP bandwidth

– Power efficiency• 5.7mW/100MHz scalable power efficiency• 1/7 the power of previous FPGA solutions

– Flexibility • Operate the XtremeDSP slice in over 40 different modes

– Efficiency• Highest DSP bandwidth per dollar solution available


Integrated PowerPC 405 World’s Most Popular Embedded Processor Architecture

• High-performance– 680 DMIPS@ 450MHz

• Low power– 0.29mW/MHz

• 2nd generation FPGA with PowerPC 405– Preserves HW and SW IP– CoreConnect™ bus architecture– Full array of system-level IP

• New APU interface– Provides direct access from FPGA fabric to

PowerPC core– Easy microcontroller and coprocessor support


Complete Processor Support Environment

GNUGNU

http://www.gnu.org/graphics/agnuhead.html


New Tri-Mode Ethernet MAC

• Fully integrated Ethernet Media Access Controller (EMAC)– 10/100/1000 Mbps– 2 or 4 cores per Virtex-4 FX device

• UNH-Compliant• Use with PowerPC or stand-alone• Key benefits

– Saves up to 4000 logic cells per Ethernet MAC

– Implement single-chip 1000 Base-X Ethernet

– Great for network management or remote FPGA monitoring

Processor Processor BlockBlock

Phy Phy InterfaceInterface

Phy Phy InterfaceInterface

ClientClientInterfaceInterface

ClientClientInterfaceInterface

Statistics InterfaceStatistics Interface

Statistics InterfaceStatistics Interface


Virtex-4 Secure Chip AES Provides Maximum Design Security

• Bitstreams encrypted with 256-bit AES algorithm

• Cryptographic keys automatically erased upon malicious tampering

• Part of standard design flow

Among FPGA vendors, only Xilinx meets U.S. Among FPGA vendors, only Xilinx meets U.S. Government standards for secure module designGovernment standards for secure module design

Among FPGA vendors, only Xilinx meets U.S. Among FPGA vendors, only Xilinx meets U.S. Government standards for secure module designGovernment standards for secure module design


Three Virtex-4 Platforms

ResourceResource

14-200K LCs14-200K LCsLogic

Memory

DCMs

DSP Slices

SelectIO

RocketIO

PowerPC

Ethernet MAC

LXLX FXFX SXSX

0.9-6Mb0.9-6Mb

4-124-12

32-9632-96

240-960240-960

23-55K LCs23-55K LCs

2.3-5.7Mb2.3-5.7Mb

4-84-8

128-512128-512

320-640320-640

12-140K LCs12-140K LCs

0.6-10Mb0.6-10Mb

4-204-20

32-19232-192

240-896240-896

0-24 Channels0-24 Channels

1 or 2 Cores1 or 2 Cores

2 or 4 Cores2 or 4 Cores

N/A

N/A

N/A

N/A

N/A

N/A

Choose the Platform that Best Fits the ApplicationChoose the Platform that Best Fits the ApplicationChoose the Platform that Best Fits the ApplicationChoose the Platform that Best Fits the Application


Virtex-4 LX: Platform for Xtreme Programmable Logic Design

• Highest logic capacity ever– Up to 200K LCs

• Widest capacity range– 8 LX devices ranging

from 14K-200K LCs


Virtex-4 FX: Platform for Xtreme System Design

• Additional advanced system functions– >10 Gbps RocketIO– PowerPC cores– 10/100/1000 Ethernet

MAC cores• Rich memory mix

– Up to nearly 10Mbits BRAM/FIFO

• Six FX devices ranging from 12K to 140K LCs


Virtex-4 SX: Platform for Xtreme Signal Processing Design

DSPSlices

DeviceCost

512

192

160

128

96

64

32 FX20FX40

FX60

FX100

LX40LX80

LX100

LX25

LX15

FX140

LX160 LX200

FX12

LX60

• 256 GMAC/s: Highest DSP 256 GMAC/s: Highest DSP performance in the industryperformance in the industry• Lowest DSP cost / performance ratioLowest DSP cost / performance ratio

• 256 GMAC/s: Highest DSP 256 GMAC/s: Highest DSP performance in the industryperformance in the industry• Lowest DSP cost / performance ratioLowest DSP cost / performance ratio

SX25

SX35

SX55


Increased Functionality with Dramatic Power Reduction

Frequency

Power Consumption

50%130 nm FPGAsVirtex-4 cuts power by 50%

• Measured 40% lower static power with Triple-Oxide technology

• 90-nm: 50% lower dynamic power – Lower core voltage + less capacitance

• Up to 10x lower dynamic power with integrated hard IP – Fewer transistors per function

ChallengesChallenges- Static power (leakage) grows exponentially with process generations- Dynamic power grows with frequency (P = cv2f)

ChallengesChallenges- Static power (leakage) grows exponentially with process generations- Dynamic power grows with frequency (P = cv2f)


Packaging Engineered for Signal & Power Integrity

• Improved signal integrity & power integrity– Minimizes package & PCB inductances

– Reduces noise by 2/3

• Designed & verified with extensive simulation

• No additional costs– Use same number of PCB layers as previous

generations

VccoGNDVccintVccaux

The best approach for high pin-count 90nm FPGAsThe best approach for high pin-count 90nm FPGAsThe best approach for high pin-count 90nm FPGAsThe best approach for high pin-count 90nm FPGAs


Lowest-Cost, High-Performance FPGA

*Based On Logic Cell Count

• System BOM cost– Integrated features allows elimination

of discrete devices and simplified PCB design

• Packaged Device Cost – 17 Virtex-4 devices to choose from– Optimized feature ratios– Increased device migration within

each package

• Die Cost– Leading edge 90-nm technology – 300mm wafers


• Unmatched Density

• Highest Performance

• Powerful Feature Set

• Best Cost Structure

Thank You !

Documents

Xilinx Advanced Products Division Virtex-4 Overview Version 2.1 March 2005