PIC18F46J50 FAMILY

Pin Diagrams (Continued)

1011

23

6

1

18 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 3916 17

2930313233

232425262728

36 3435

9

PIC18F4XJ50

37

RA

3/A

N3/

VRE

F+/C

1IN

BR

A2/A

N2/

VRE

F-/C

VRE

F-/C

2IN

BR

A1/

AN

1/C

2IN

A/P

MA

7/R

P1R

A0/

AN

0/C

1IN

A/U

LPW

U/P

MA

6/R

P0M

CLRN

C

RB

7/K

BI3

/PG

D/R

P10

RB

6/K

BI2/

PG

C/R

P9R

B5/

PMA

0/K

BI1

/SD

I1/S

DA

1/R

P8R

B4/

PM

A1/

KB

I0/S

CK1

/SC

L1/R

P7NC

RC

6/P

MA

5/TX

1/C

K1/R

P17

RC

5/D

+/V

PR

C4/

D-/V

MR

D3/

PM

D3/

RP2

0R

D2/

PM

D2/

RP1

9R

D1/

PM

D1/

SD

A2R

D0/

PM

D0/

SC

L2VU

SB

RC

2/A

N11

/CTP

LS/R

P13

RC

1/T1

OS

I/UO

E /R

P12

NC

NCRC0/T1OSO/T1CKI/RP11OSC2/CLKO/RA6OSC1/CLKI/RA7VSSVDDRE2/AN7/PMCSRE1/AN6/PMWRRE0/AN5/PMRDRA5/AN4/SS1/HLVDIN/RCV/RP2VDDCORE/VCAP(2)

RC7/PMA4/RX1/DT1/SDO1/RP18RD4/PMD4/RP21RD5/PMD5/RP22RD6/PMD6/RP23

VSSVDD

RB0/AN12/INT0/RP3RB1/AN10/PMBE/RTCC/RP4

RB2/AN8/CTED1/PMA3/VMO/REFO/RP5RB3/AN9/CTED2/PMA2/VPO/RP6

44-Pin TQFP(1)

RD7/PMD7/RP24 54

Legend: RPn represents remappable pins.Note 1: Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be

dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module, see Section 10.7 Peripheral Pin Select (PPS).

2: See Section 27.3 On-Chip Voltage Regulator for details on how to connect the VDDCORE/VCAP pin.

= Pins are up to 5.5V tolerant 2011 Microchip Technology Inc. DS39931D-page 7