What is New in Active-HDL 92

What’s New Presentation

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New Icon and Image

Active-HDL 9.2 - What’s New Presentation

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New icon and image brings new look to this release but continues to provide same reliability and quality tools to FPGA designers

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9.2

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Features

› Project/Design Management › Design Creation › Debugging › Graphical User Interface › Compiler and Simulator › Documentation


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User-defined Design Management


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› Separate HDL files from other types of files, e.g. schematics, text, waveform and scripts

› Easily maintain and adhere to design structure required by entire team or a company

› Create directory structure that is compatible to other synthesis and implementation tool

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Define Design Structure

› Default design structure can be accessed from menu Tools | Preferences | Design Structure

› Double click on Folder or Path column to enter information

› Folder will be created automatically if it does not exist


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Define Design Structure Cont…

› After the structure is applied, all the files created from scratch or added to design are automatically saved in defined folders

› User-defined directory structure is stored in design_structure.cfg file located in /dat folder of installation directory


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Before

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Team-based Design Structure

› design_structure.cfg file can shared by copying locally or via network(Using pre-defined variable $activehdlteamhome)

› Team-based design settings can be applied and enforced on every team-member

› Its quick and easy to deploy team-wide changes as only one settings file needs to be maintained


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Design Flow Manager

› Design Flow Manger in Active-HDL includes support for latest vendor devices and libraries

› Following versions of the vendor tools are supported in this release of Active-HDL

› Altera Quartus® II 12.0 Synthesis & Implementation

› Lattice® Diamond LSE 2.0

› Synopsys® Synplify®/Synplify Pro/Synplify Premier/Premier with Design Planner F-2012.03

› Xilinx PlanAhead 14.2

› Xilinx ISE/WebPack 14.2 XST VHDL/Verilog

› Actel/Microsemi Designer 10.0 (supports Designer 10.0 SP2)


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Features

› Project/Design Management

› Design Creation › Debugging › Graphical User Interface › Compiler and Simulator › Documentation


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Multiple Symbols - Same Unit

› Same library unit can be tied to multiple symbols

› Allows to create symbols with different shapes and colors for same entity or module

› Gives freedom to change pin location on symbol without changing the symbol definition


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entity/module

View1 View2 View3

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Multiple Symbols - Same Unit Cont..

› Increases the readability of large schematic files by allowing different shapes of symbols for the same unit

› Provides flexibility to change pin location on symbols so they fit easily and does not create clutter


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Route Optimization on Schematics

› Automatically reduces the redundant net segments from schematics

› Improves readability of the schematics by optimizing routes

› Allows to clean legacy designs or imported projects much more quickly


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Before

After

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Features

› Project/Design Management › Design Creation

› Debugging › Graphical User Interface › Compiler and Simulator › Documentation


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Waveform Viewer

› Text messages can be stamped on signal or a time ruler on waveform viewer

› Allows to trace the flow of test on the waveform viewer

› Helps find stimulus injection or output results quickly on the waveform during reviews


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Waveform Viewer Cont…


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› Add to waveform option in signal browser allows adding signal quickly

› More flexible GUI now allows adding signals from the structure tab to waveform while find window is open

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Waveform Viewer Cont…

› Special browse by comments mode to find the text messages on waveform quickly

› New macro commands to perform number of GUI operations e.g. zooming, copying, pasting, deleting, finding, grouping signals, etc


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Features

› Project/Design Management › Design Creation › Debugging

› Graphical User Interface › Compiler and Simulator › Documentation


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Mouse Strokes

› Increases productivity by allowing you to perform common task anywhere in the window

› Navigate and execute commands by simply moving the mouse

› Do not have to access menu every time, you can perform operation from anywhere on the screen


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Hold Right Click

Draw Shape

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Mouse Strokes Cont..

› User can assign right, left or mouse wheel to enable mouse strokes

› Hold right mouse(default) and draw shapes to perform common operations such as zooming, find, hierarchy pop, etc..

› Customization allows users to create easy-to-remember user-defined mouse strokes


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Open Properties

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Features

› Project/Design Management › Design Creation › Debugging › Graphical User Interface

› Compiler & Simulator › Documentation


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Compiler and Simulator

› VHDL

› Support for force and release signal assignment statements

› -unbounderror argument in asim command allows to raise the severity to error when unbound unit is detected

› Verilog/SystemVerilog

› Compilation time of case statements with thousands of conditions has been improved

› Support for array manipulation methods such as array locator, array ordering and array reduction

› Support for unpacked arrays in module parameters

› `begin_keywords and `end_keywords compiler directives are supported


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Features

› Project/Design Management › Design Creation › Debugging › Graphical User Interface › Compiler and Simulator

› Documentation


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PDF & HTML Documentation

› Export accelerated waveform files(*.awc) to PDF and HTML

› Design hierarchy is now included in exported HTML document

› Users can view structure of elaborated design in HTML docs


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Export to Graphics

› Share waveform files quickly by exporting them to graphics(.png, .jpeg, .bmp)

› No need for sharing the whole file – Time range feature allows to share exactly what is needed


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Help Articles

› Two new documents have been added to Active-HDL Help.

1. How to use Active-HDL help document (User Guide | Introduction) – how to efficiently find something you are looking for

2. Licensing guide – to explain licensing, configuration and diagnostic applications


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Summary

› User-defined Design Management – Customize directory structure to fit your project environment

› Mouse Strokes – Perform common task by simply moving mouse. Also known as Mouse Gestures

› Multiple symbols for same library unit – Create multiple variance of symbol for same VHDL entity or Verilog module

› Route optimization for schematics – Automatically optimize and reduce redundant net segment on schematics

› Annotate Waveform – Put message balloons on waveform for better debugging and documentation

› Support for latest FPGA device – Design flow manager has been updated to support latest vendor tools and libraries


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How to reach Aldec?

Aldec, Inc. Corp. Headquarters – N. America 2260 Corporate Circle Henderson, NV 89074 USA

+1.702.990.4400 [email protected] Europe [email protected]

Israel [email protected]

Japan [email protected]

China [email protected]

India [email protected]

Taiwan [email protected]

www.aldec.com News/Products/Events/Resources/Support

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www.aldec.com/products/active-hdl FPGA Design and Simulation

www.aldec.com/support/resources/multimedia Product Videos

www.youtube.com/user/aldecinc Aldec YouTube Channel


mailto:[email protected]

















http://www.aldec.com/

http://www.aldec.com/products/active-hdl



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Documents

What is New in Active-HDL 92