Aldec Active HDL 5
Aldec Active HDL 5.1 Tutorial
CSE 378 – Fall 2002
Create a subdirectory under C:\CSE378\ containing your last
name.
Start the program by double-clicking the Active-HDL 5.1 icon on
the desktop. Select Create new design and click OK.
Select Create an empty design and click Next.
Choose Synopsys FPGA Express (Xilinx) as the Synthesis tool and
Xilinx ISE 4.x as the Implementation tool. Select Xilinx 3.3
Spartan II (the second Spartan selection) as the Default Family,
and HDL as the Block Diagram Configuration. Click Next.
Type Lab1 for the design name and select your last-name
subdirectory as the location of the design folder. Click Next.
Click Finish.
Click on HDE.
Click Next.
Type Lab1
and click Next.
Click New.
Type SW.
Set Array Indexes to 1:8.
Click New.
Type BTN4.
Click New.
Click out.
Type ldg.
Click New.
Type LD.
Set Array indexes to 1:4.
Click Finish
This will generate a VHDL template with the entity filled
in.
From the menu select Design -> Add Files to Design…
Add the file mux2g.vhd that was supplied with this lab.
Right-click on mux2g.vhd and select Compile All.
Choose Lab1 as the top-level unit.
Click OK.
Click the + sign.
Right-click on mux2g and select
Copy Declaration.
Paste the component declaration in the Lab1 architecture before
the word begin.
Delete the last line that starts with for.
Add the statement
constant bus_width: integer := 4;
before the word begin.
Add the statements
ldg <= '1'; -- enable 74HC373 latch
SWmux: mux2g generic map(width => bus_width) port map
(a => SW(1 to 4), b => SW(5 to 8), sel => BTN4, y =>
LD);
after the word begin.
Select design flow.
Click functional simulation options and Choose Lab 1 as the
Top-level Unit by selecting it and clicking Add.
Click on the waveform icon.
Click on lab1
and
drag it to here.
Right-click on SW and select Stimulators.
Select Value and type in 16#A5.
Click Apply.
Click on BTN4.
Select Clock.
Click Apply.
Set the simulation time to 300 ns.
Click Run For
Print out the waveform by selecting File -> Print from the
menu bar.
