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Welcome to CS250VLSI Systems Design
8/28/09Yunsup Lee
Email: [email protected] add [CS250] in the subjectWill try to get back in a day
Sections: Friday, 2-3pm, 320 SODA
Office Hours: Friday, 3-4pm, 611 SODA
YUNSUP LEE
Caution!
NEVER post materials onlineToolsDocumentsTechnology filesMethodology scripts
What is my job?
File
Gate
Level
Netlist
Constraints
File
Formality
Std
Cell
Lib
IC Compiler (DP)
Floor
Plan
TLUplus
Files
Verification
Resuls
Timing
Area
LayoutGate
Level
Netlist
Constraints
File
IC Compiler (PAR)
Parasitics
File
IC Compiler GUI
Post Syn.
Sim
VPD Test
Outputs
DVE GUI
VCS
Post PAR
Sim
VPD Test
Outputs
VCS
DVE GUI VPD2VCD
Area
Behav
Sim
VPD Test
Outputs
Design Compiler
DVE GUI
Verilog
Source
(Behav)
Verilog
Source
(RTL)
VCS
RTL
Sim
VPD Test
Outputs
DVE GUI
Guidance Timing
VCD
PrimeTime
Power
Estimates
Design Vision GUI
Constraints
VCS
Execute Sim
Execute Sim
Execute Sim
Execute Sim
How? Three Labs
Lab 1: GCD: VLSI’s Hello World8/27 - 9/8 before class (1.5 weeks)
Lab 2: SMIPSv2 RTL Implementation + Synthesis9/8 - 9/24 before class (2.5 weeks)
Lab 3: SMIPSv2 Place and Route + Power Analysis9/24 - 10/6 before class (1.5 weeks)
Greatest Common DivisorThings that are provided
Test HarnessThings that you need to do
Write GCD RTLPush it through the whole tool flow
GoalRecap Verilog CodingGet a feeling of all the tools
Lab 1: GCD
Lab 2: SMIPSv2RTL Impl. + Synthesis
SMIPS: Stands for Simplified MIPS ProcessorThings that are provided
Test Harness (which loads programs)SMIPSv1 RTL ImplementationSMIPS ISA Simulator / SMIPS C Compiler
Things that you need to doWrite SMIPSv2 RTLSynthesize processor / Formally Verify
GoalCorrect ExecutionMaximize Clock FrequencyMinimize Post Synthesis Area
SMIPSv1 vs. SMIPSv2
SMIPSv1 (5 instructions) 1 stage pipelineLW, SW, ADDIU, BNE, MTC0
SMIPSv2 (33 instructions) 2 stage pipelineLW, SWADDIU, SLTI, SLTIU, ANDI, ORI, XORI, LUISLL, SRL, SRA, SLLV, SRLV, SRAVADDU, SUBU, AND, OR, XOR, NOR, SLT, SLTUJ, JAL, JR, JALRBEQ , BNE, BLEZ, BGTZ, BLTZ, BGEZMFC0, MTC0
No Branch Delay Slot!
Lab 3: SMIPSv2Place and Route + PowerThings that are provided
Test HarnessExample Design which uses SRAM Cell
Things that you need to doChange the magic memory to SRAM CellsModifying parts of your RTLSynthesize CorePlace and Route designEstimate Power
GoalCorrect ExecutionMinimize Area / Minimize Power
Any Questions?
Labs are 15% of your grade
Each student gets a total of four late daysYou can’t use late days for Lab 1
Everything goes into the SVN repositoryYour writeup should only be in text or PDF
Greatest Common Divisor
Euclidean AlgorithmSTART (A, B)if (A < B)
SWAP (A, B)else if (B != 0)
SUBTRACT (A-B, B)else
DONE gcd=A
START (32, 48)A<B SWAP (48, 32)B!=0 SUBTRACT (16, 32)A<B SWAP (32, 16)B!=0 SUBTRACT (16, 16)B!=0 SUBTRACT (16, 0)B=0 DONE GCD=16
GCD Port Interface
operands_rdy
operands_val
operands_bits_A
operands_bits_B
result_bits_data
result_rdy
result_val
clk reset
Let’s form groups
Make 4 groups by doinggroup # = (Birth Month + Birth Day) MOD 4
Will give you 5-10 minutes
First figure out the datapath, then control
GCD Datapath and Control
B
A_lt_B B_zero
zero? lt
A
sub
A_mux_sel
A_en
B_mux_sel
B_en
operands_val
operands_rdy
result_val
result_rdy
operands_A
operands_B
result
Figure out the transition between statesFigure out the following signals for each state
A_mux_sel, A_en, B_mux_sel, B_enoperands_rdy, results_val
FSM for valid/ready signals
WAIT
CALC
DONE
Waiting for new input operands
Swapping and subtracting
Waiting for consumer to take the result
reset
Now we’ve got the RTL Synopsys VCS (vcs-sim-rtl)
simulate RTLSynopsys Design Compiler (dc-syn)
synthesize gate-level netlistSynopsys Formality (dc-syn)
formal verificationSynopsys VCS (vcs-sim-gl-syn)
simulate post synthesis gate-level netlistSynopsys IC Compiler (icc-par)
place and route gate-level netlistSynopsys VCS (vcs-sim-gl-par)
simulate post place and route gate-level netlistSynopsys PrimeTime PX (pt-pwr)
estimate power consumption
