UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

2009-9-24John Wawrzynek and Krste Asanovic

with John Lazzaro

CS 250 VLSI System Design

Lecture 9 – Floorplanning

www-inst.eecs.berkeley.edu/~cs250/

TA: Yunsup Lee

Many-core Example Chips

1

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

2

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Intel Larrabee

3

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Sun Niagara II and Intel Larrabee are both:

Complete implementations oflong-established ISAs (SPARC, x86).

Provide a conventional shared-memory virtual-address memory model.

Micro-architecture and ISA extensions target a specific application area.

Not boutique parts - manufacturable.

Many-cores, multi-threaded cores.

4

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Sun Niagara II Target Market

Some applications inavoidably spend their lives waiting for memory.

memory machines with discrete single-thread-ed processors and coherent interconnect havetended to perform well because they exploitTLP. However, the use of an SMP composedof multiple processors designed to exploit ILPis neither power efficient nor cost-efficient. Amore efficient approach is to build a machineusing simple cores aggregated on a single die,with a shared on-chip cache and high band-width to large off-chip memory, therebyaggregating an SMP server on a chip. This hasthe added benefit of low-latency communi-cation between the cores for efficient datasharing in commercial server applications.

Niagara overviewThe Niagara approach to increasing

throughput on commercial server applicationsinvolves a dramatic increase in the number ofthreads supported on the processor and amemory subsystem scaled for higher band-widths. Niagara supports 32 threads of exe-cution in hardware. The architectureorganizes four threads into a thread group; thegroup shares a processing pipeline, referred toas the Sparc pipe. Niagara uses eight suchthread groups, resulting in 32 threads on theCPU. Each SPARC pipe contains level-1caches for instructions and data. The hard-ware hides memory and pipeline stalls on agiven thread by scheduling the other threadsin the group onto the SPARC pipe with a zerocycle switch penalty. Figure 1 schematicallyshows how reusing the shared processingpipeline results in higher throughput.

The 32 threads share a 3-Mbyte level-2cache. This cache is 4-way banked andpipelined for bandwidth; it is 12-way set-associative to minimize conflict misses fromthe many threads. Commercial server codehas data sharing, which can lead to highcoherence miss rates. In conventional SMPsystems using discrete processors with coher-ent system interconnects, coherence misses goout over low-frequency off-chip buses or links,and can have high latencies. The Niagaradesign with its shared on-chip cache elimi-nates these misses and replaces them with low-latency shared-cache communication.

The crossbar interconnect provides thecommunication link between Sparc pipes, L2cache banks, and other shared resources onthe CPU; it provides more than 200 Gbytes/s

of bandwidth. A two-entry queue is availablefor each source-destination pair, and it canqueue up to 96 transactions each way in thecrossbar. The crossbar also provides a port forcommunication with the I/O subsystem.Arbitration for destination ports uses a sim-ple age-based priority scheme that ensures fairscheduling across all requestors. The crossbaris also the point of memory ordering for themachine.

The memory interface is four channels ofdual-data rate 2 (DDR2) DRAM, supportinga maximum bandwidth in excess of 20Gbytes/s, and a capacity of up to 128 Gbytes.Figure 2 shows a block diagram of the Nia-gara processor.

Sparc pipelineHere we describe the Sparc pipe implemen-

tation, which supports four threads. Eachthread has a unique set of registers and instruc-tion and store buffers. The thread group sharesthe L1 caches, translation look-aside buffers(TLBs), execution units, and most pipelineregisters. We implemented a single-issuepipeline with six stages (fetch, thread select,decode, execute, memory, and write back).

In the fetch stage, the instruction cache andinstruction TLB (ITLB) are accessed. The fol-lowing stage completes the cache access byselecting the way. The critical path is set bythe 64-entry, fully associative ITLB access. Athread-select multiplexer determines which of

23MARCH–APRIL 2005

C M M MCC

C M M MCC

C M

C M

C M

Time saved

Singleissue

ILP

TLP (on shared

single issuepipeline)

Memory latency Compute latency

Figure 1. Behavior of processors optimized for TLP and ILP oncommercial server workloads. In comparison to the single-issue machine, the ILP processor mainly reduces computetime, so memory access time dominates application perfor-mance. In the TLP case, multiple threads share a single-issuepipeline, and overlapped execution of these threads results inhigher performance for a multithreaded application.

memory machines with discrete single-thread-ed processors and coherent interconnect havetended to perform well because they exploitTLP. However, the use of an SMP composedof multiple processors designed to exploit ILPis neither power efficient nor cost-efficient. Amore efficient approach is to build a machineusing simple cores aggregated on a single die,with a shared on-chip cache and high band-width to large off-chip memory, therebyaggregating an SMP server on a chip. This hasthe added benefit of low-latency communi-cation between the cores for efficient datasharing in commercial server applications.

Niagara overviewThe Niagara approach to increasing

throughput on commercial server applicationsinvolves a dramatic increase in the number ofthreads supported on the processor and amemory subsystem scaled for higher band-widths. Niagara supports 32 threads of exe-cution in hardware. The architectureorganizes four threads into a thread group; thegroup shares a processing pipeline, referred toas the Sparc pipe. Niagara uses eight suchthread groups, resulting in 32 threads on theCPU. Each SPARC pipe contains level-1caches for instructions and data. The hard-ware hides memory and pipeline stalls on agiven thread by scheduling the other threadsin the group onto the SPARC pipe with a zerocycle switch penalty. Figure 1 schematicallyshows how reusing the shared processingpipeline results in higher throughput.

The 32 threads share a 3-Mbyte level-2cache. This cache is 4-way banked andpipelined for bandwidth; it is 12-way set-associative to minimize conflict misses fromthe many threads. Commercial server codehas data sharing, which can lead to highcoherence miss rates. In conventional SMPsystems using discrete processors with coher-ent system interconnects, coherence misses goout over low-frequency off-chip buses or links,and can have high latencies. The Niagaradesign with its shared on-chip cache elimi-nates these misses and replaces them with low-latency shared-cache communication.

The crossbar interconnect provides thecommunication link between Sparc pipes, L2cache banks, and other shared resources onthe CPU; it provides more than 200 Gbytes/s

of bandwidth. A two-entry queue is availablefor each source-destination pair, and it canqueue up to 96 transactions each way in thecrossbar. The crossbar also provides a port forcommunication with the I/O subsystem.Arbitration for destination ports uses a sim-ple age-based priority scheme that ensures fairscheduling across all requestors. The crossbaris also the point of memory ordering for themachine.

The memory interface is four channels ofdual-data rate 2 (DDR2) DRAM, supportinga maximum bandwidth in excess of 20Gbytes/s, and a capacity of up to 128 Gbytes.Figure 2 shows a block diagram of the Nia-gara processor.

Sparc pipelineHere we describe the Sparc pipe implemen-

tation, which supports four threads. Eachthread has a unique set of registers and instruc-tion and store buffers. The thread group sharesthe L1 caches, translation look-aside buffers(TLBs), execution units, and most pipelineregisters. We implemented a single-issuepipeline with six stages (fetch, thread select,decode, execute, memory, and write back).

In the fetch stage, the instruction cache andinstruction TLB (ITLB) are accessed. The fol-lowing stage completes the cache access byselecting the way. The critical path is set bythe 64-entry, fully associative ITLB access. Athread-select multiplexer determines which of

23MARCH–APRIL 2005

C M M MCC

C M M MCC

C M

C M

C M

Time saved

Singleissue

ILP

TLP (on shared

single issuepipeline)

Memory latency Compute latency

Figure 1. Behavior of processors optimized for TLP and ILP oncommercial server workloads. In comparison to the single-issue machine, the ILP processor mainly reduces computetime, so memory access time dominates application perfor-mance. In the TLP case, multiple threads share a single-issuepipeline, and overlapped execution of these threads results inhigher performance for a multithreaded application.

Cores that focus on extracting instruction-level parallelism are wasted on these apps.

memory machines with discrete single-thread-ed processors and coherent interconnect havetended to perform well because they exploitTLP. However, the use of an SMP composedof multiple processors designed to exploit ILPis neither power efficient nor cost-efficient. Amore efficient approach is to build a machineusing simple cores aggregated on a single die,with a shared on-chip cache and high band-width to large off-chip memory, therebyaggregating an SMP server on a chip. This hasthe added benefit of low-latency communi-cation between the cores for efficient datasharing in commercial server applications.

Niagara overviewThe Niagara approach to increasing

throughput on commercial server applicationsinvolves a dramatic increase in the number ofthreads supported on the processor and amemory subsystem scaled for higher band-widths. Niagara supports 32 threads of exe-cution in hardware. The architectureorganizes four threads into a thread group; thegroup shares a processing pipeline, referred toas the Sparc pipe. Niagara uses eight suchthread groups, resulting in 32 threads on theCPU. Each SPARC pipe contains level-1caches for instructions and data. The hard-ware hides memory and pipeline stalls on agiven thread by scheduling the other threadsin the group onto the SPARC pipe with a zerocycle switch penalty. Figure 1 schematicallyshows how reusing the shared processingpipeline results in higher throughput.

The 32 threads share a 3-Mbyte level-2cache. This cache is 4-way banked andpipelined for bandwidth; it is 12-way set-associative to minimize conflict misses fromthe many threads. Commercial server codehas data sharing, which can lead to highcoherence miss rates. In conventional SMPsystems using discrete processors with coher-ent system interconnects, coherence misses goout over low-frequency off-chip buses or links,and can have high latencies. The Niagaradesign with its shared on-chip cache elimi-nates these misses and replaces them with low-latency shared-cache communication.

The crossbar interconnect provides thecommunication link between Sparc pipes, L2cache banks, and other shared resources onthe CPU; it provides more than 200 Gbytes/s

of bandwidth. A two-entry queue is availablefor each source-destination pair, and it canqueue up to 96 transactions each way in thecrossbar. The crossbar also provides a port forcommunication with the I/O subsystem.Arbitration for destination ports uses a sim-ple age-based priority scheme that ensures fairscheduling across all requestors. The crossbaris also the point of memory ordering for themachine.

The memory interface is four channels ofdual-data rate 2 (DDR2) DRAM, supportinga maximum bandwidth in excess of 20Gbytes/s, and a capacity of up to 128 Gbytes.Figure 2 shows a block diagram of the Nia-gara processor.

Sparc pipelineHere we describe the Sparc pipe implemen-

tation, which supports four threads. Eachthread has a unique set of registers and instruc-tion and store buffers. The thread group sharesthe L1 caches, translation look-aside buffers(TLBs), execution units, and most pipelineregisters. We implemented a single-issuepipeline with six stages (fetch, thread select,decode, execute, memory, and write back).

In the fetch stage, the instruction cache andinstruction TLB (ITLB) are accessed. The fol-lowing stage completes the cache access byselecting the way. The critical path is set bythe 64-entry, fully associative ITLB access. Athread-select multiplexer determines which of

23MARCH–APRIL 2005

C M M MCC

C M M MCC

C M

C M

C M

Time saved

Singleissue

ILP

TLP (on shared

single issuepipeline)

Memory latency Compute latency

Figure 1. Behavior of processors optimized for TLP and ILP oncommercial server workloads. In comparison to the single-issue machine, the ILP processor mainly reduces computetime, so memory access time dominates application perfor-mance. In the TLP case, multiple threads share a single-issuepipeline, and overlapped execution of these threads results inhigher performance for a multithreaded application.

Instead, build simple cores that are multi-threaded, and focus on maximizing throughput of a large number of threads.

5

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

KrsteNovember 10, 2004

6.823, L18--5

Simple Multithreaded Pipeline

Have to carry thread select down pipeline to ensure correct state bits read/written at each pipe stage

+1

2 Thread

select

PC1

PC1

PC1

PC1

I$ IRGPR1GPR1GPR1GPR1

X

Y

2

D$

Sun Niagara II Multithreading

Multi-threading static pipeline CPUs is simple and efficient, and goes back to the 1960s (CDC).

6

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Sun Niagara II Sizing the chip

8 threads/core: Enough to keep one core busy, given clock speed, memory system latency, and target application characteristics.

6 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 1, JANUARY 2008

Implementation of an 8-Core, 64-Thread,Power-Efficient SPARC Server on a Chip

Umesh Gajanan Nawathe, Mahmudul Hassan, King C. Yen, Ashok Kumar, Aparna Ramachandran, andDavid Greenhill

Abstract—The second in the Niagara series of processors(Niagara2) from Sun Microsystems is based on the power-ef-ficient chip multi-threading (CMT) architecture optimized forSpace, Watts (Power), and Performance (SWaP) [SWap Rating

Performance Space Power ]. It doubles the throughputperformance and performance/watt, and provides 10 im-provement in floating point throughput performance as comparedto UltraSPARC T1 (Niagara1). There are two 10 Gb Ethernetports on chip. Niagara2 has eight SPARC cores, each supportingconcurrent execution of eight threads for 64 threads total. EachSPARC core has a Floating Point and Graphics unit and anadvanced Cryptographic unit which provides high enough band-width to run the two 10 Gb Ethernet ports encrypted at wirespeeds. There is a 4 MB Level2 cache on chip. Each of the fouron-chip memory controllers controls two FBDIMM channels.Niagara2 has 503 million transistors on a 342 mm die packagedin a flip-chip glass ceramic package with 1831 pins. The chip isbuilt in Texas Instruments’ 65 nm 11LM triple- CMOS process.It operates at 1.4 GHz at 1.1 V and consumes 84 W.

Index Terms—Chip multi-threading (CMT), clocking, com-puter architecture, cryptography, low power, microprocessor,multi-core, multi-threaded, Niagara series of processors, powerefficient, power management, SerDes, SPARC architecture, syn-chronous and asynchronous clock domains, system on a chip(SoC), throughput computing, UltraSPARC T2.

I. INTRODUCTION

TODAY’S datacenters face extreme throughput, space,and power challenges. Throughput demands continue in-

creasing while space and power are fixed. The increase in powerconsumed by the servers and the cost of cooling has caused arapid increase in the cost of operating a datacenter. The Nia-gara1 processor [5] (also known as the UltraSPARC T1) madea substantial attempt at solving this problem. This paper de-scribes the implementation of the Niagara2 processor, designedwith a wide range of applications in mind, including database,web-tear, floating-point, and secure applications. Niagara2, asthe name suggests, is the follow-on to the Niagara1 processorbased on the CMT architecture optimized for SWaP.

Fig. 1 illustrates the advantages of the CMT architecture.For a single thread, memory access is the single biggestbottleneck to improving performance. For workloads which

Manuscript received April 17, 2007; revised September 27, 2007.U. G. Nawathe is with Sun Microsystems, Santa Clara, CA 95054 USA

(e-mail: umesh.nawathe@sun.com).M. Hassan, K. C. Yen, A. Kumar, A. Ramachandran, and D. Greenhill are

with Sun Microsystems, Sunnyvale, CA 94085 USA.Digital Object Identifier 10.1109/JSSC.2007.910967

Fig. 1. Throughput computing using the CMT architecture.

exhibit poor memory locality, only a modest throughputspeedup is possible by reducing compute time. As a result,conventional single-thread processors which are optimized forInstruction-Level-Parallelism have low utilization and wastedpower. Having many threads makes it easier to find somethinguseful to execute every cycle. As a result, processor utilizationis higher and significant throughput speedups are achievable.

The design of the Niagara2 processor started off withthree primary goals in mind: 1) 2 throughput perfor-mance and performance/watt as compared to UltraSPARC T1;2) 10 floating point throughput performance as comparedto UltraSPARC T1; and 3) integration of the major systemcomponents on chip. Two options were considered to achievethese goals: 1) double the number of cores to 16 as comparedto eight on UltraSPARC T1, with each core supporting fourthreads as in UltraSPARC T1; and 2) double the number ofthreads/core from four to eight and correspondingly doublethe number of execution units per core from one to two. Bothoptions would have enabled us to achieve our first goal. Thefirst option would have doubled the SPARC core area as com-pared to a lot smaller area increase with the second option.The second option was chosen as the area saved using thisoption allowed us to integrate a Floating Point and Graphicsunit and a Cryptographic unit inside each SPARC core and alsoallowed integration of the critical SoC components on chip,thus enabling us to achieve our second and third goals as well.

II. ARCHITECTURE AND KEY STATISTICAL HIGHLIGHTS

A. Niagara2 Architecture

Fig. 2 shows the Niagara2 block diagram, and Fig. 3 showsthe die micrograph. The chip has eight SPARC Cores, a 4 MBshared Level2 cache, and supports concurrent execution of64 threads. The Level2 cache is divided into eight banks of512 kB each. The SPARC Cores communicate with the Level2cache banks through a high bandwidth crossbar. Niagara2 hasa 8 PCI-Express channel, two 10 Gb Ethernet ports withXAUI interfaces and four memory controllers each controlling

0018-9200/$25.00 © 2008 IEEE

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on September 18, 2009 at 17:03 from IEEE Xplore. Restrictions apply.

Cores/chip?: The number of cores that can be put to good use is limited by the memory bandwidth available to keep all threads on all cores busy.

7

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

NAWATHE et al.: IMPLEMENTATION OF AN 8-CORE, 64-THREAD, POWER-EFFICIENT SPARC SERVER ON A CHIP 7

Fig. 2. Niagara2 block diagram.

Fig. 3. Niagara2 die micrograph.

two FBDIMM channels. These three major I/O interfaces areserializer/deserializer (SerDes) based and provide a total pinbandwidth in excess of 1 Tb/s. All the SerDes are on chip.The high levels of system integration truly makes Niagara2 a“server-on-a-chip”, thus reducing system component count,complexity and power, and hence improving system reliability.

B. SPARC Core Architecture

Fig. 4 shows the block diagram of the SPARC Core. EachSPARC core (SPC) implements the 64-bit SPARC V9 instruc-tion set while supporting concurrent execution of eight threads.Each SPC has one load/store unit (LSU), two Execution units(EXU0 and EXU1), and one Floating Point and Graphics Unit(FGU). The Instruction Fetch unit (IFU) and the LSU contain an8-way 16 kB Instruction cache and a 4-way 8 kB Data cache re-spectively. Each SPC also contains a 64-entry Instruction-TLB(ITLB), and a 128-entry Data-TLB (DTLB). Both the TLBs arefully associative. The memory Management Unit (MMU) sup-ports 8 K, 64 K, 4 M, and 256 M page sizes and has Hardware

Fig. 4. SPC block diagram.

Fig. 5. Integer pipeline: eight stages.

Fig. 6. Floating point pipeline: 12 stages.

TableWalk to reduce TLB miss penalty. “TLU” in the block dia-gram is the Trap Logic Unit. The “Gasket” performs arbitrationfor access to the Crossbar. Each SPC also has an advanced Cryp-tographic/Stream Processing Unit (SPU). The combined band-width of the eight Cryptographic units from the eight SPCs issufficient for running the two 10 Gb Ethernet ports encrypted.This enables Niagara2 to run secure applications at wire speed.

Fig. 5 and Fig. 6 illustrate the Niagara2 integer and floatingpoint pipelines, respectively. The integer pipeline is eight stageslong. The floating point pipeline has 12 stages for most opera-tions. Divide and Square-root operations have a longer pipeline.

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on September 18, 2009 at 17:03 from IEEE Xplore. Restrictions apply.

Sun Niagara II: 8 cores, 4MB L2, 4 DRAM channels

“Small” L2 cache because apps are locality-poor.Each DRAM channel: 50 GB/s Read, 25 GB/s Write BW.Crossbar BW: 270 GB/s total (Read + Write).

(Also shared by an I/O port, not shown)8

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

NAWATHE et al.: IMPLEMENTATION OF AN 8-CORE, 64-THREAD, POWER-EFFICIENT SPARC SERVER ON A CHIP 9

Fig. 9. L2 cache row redundancy scheme.

2-cycle latency. Addresses can be hashed to distribute accessesacross different sets in case of hot cache sets caused by refer-ence conflicts. All arrays are protected by single error correc-tion, double error detection ECC, and parity. Data from differentways and different words is interleaved to improve soft errorrates.

The L2 cache used a unique row-redundancy scheme. It is im-plemented at the 32 kB level and is illustrated in Fig. 9. Sparerows for one array are located in the adjacent array as opposed tothe same array. In other words, spare rows for the top array arelocated in the bottom array and vice versa. When redundancy isenabled, the incoming address is compared with the address ofthe defective row and if it matches, the adjacent array (which isnormally not enabled) is enabled to read from or write into thespare row. Using this kind of scheme enables a large ( 30%)reduction in X-decoder area. The area reduction is achieved be-cause the multiplexing required in the X-decoder to bypass thedefective row/rows in the traditional row redundancy scheme isno longer needed in this scheme.

N-well power for the Primary and L2 cache memory cellsis separated out as a test hook. This allows weakening of thepMOS loads of the SRAM bit cells by raising their thresholdvoltage, thus enabling screening cells with marginal static noisemargin. This significantly reduces defective parts per million(DPPM) and improves reliability.

Fig. 10 shows the Niagara2 Crossbar (CCX). CCX serves asa high bandwidth interface between the eight SPARC Cores,shown on top, and the eight L2 cache banks, and the non-cacheable unit (NCU) shown at the bottom. CCX consists of twoblocks: PCX and CPX. PCX (“Processor-to-Cache-Transfer”)is a 8-input 9-output multiplexer (mux). It transfers data fromthe eight SPARC cores to the eight L2 cache banks and theNCU. Likewise, CPX (“Cache-to-Processor Transfer”) is a

Fig. 10. Crossbar.

9-input 8-output mux, and it transfers data in the reverse di-rection. The PCX and CPX combined provide a Read/Writebandwidth of 270 GB/s. All crossbar data transfer requestsare processed using a four-stage pipeline. The pipeline stagesare: Request, Arbitration, Selection, and Transmission. As canbe seen from the figure, there are possiblesource destination pairs for each data transfer request. There isa two-deep queue for each source–destination pair to hold datatransfer requests for that pair.

IV. CLOCKING

Niagara2 contains a mix of many clocking styles—syn-chronous, mesochronous and asynchronous—and hence a largenumber of clock domains. Managing all these clock domainsand domain crossings between them was one of the biggestchallenges the design team faced. A subset of synchronousmethodology, ratioed synchronous clocking (RSC) is usedextensively. The concept works well for functional mode whilebeing equally applicable to at-speed test of the core using theSerDes interfaces.

A. Clock Sources and Distribution

An on-chip phase-locked loop (PLL) uses a fractional divider[8], [9] to generate Ratioed Synchronous Clocks with supportfor a wide range of integer and fractional divide ratios. Thedistribution of these clocks uses a combination of H-treesand grids. This ensures they meet tight clock skew budgetswhile keeping power consumption under control. Clock TreeSynthesis is used for routing the asynchronous clocks. Asyn-chronous clock domain crossings are handled using FIFOsand meta-stability hardened flip-flops. All clock headers aredesigned to support clock gating to save clock power.

Fig. 11 shows the block diagram of the PLL. Its architectureis similar to the one described in [8]. It uses a loop filter capac-itor referenced to a regulated 1.1 V supply (VREG). VREG isgenerated by a voltage regulator from the 1.5 V supply coming

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on September 18, 2009 at 17:03 from IEEE Xplore. Restrictions apply.

Sun Niagara II 8 x 9 Crossbar

8 ports on CPU side (one per core)

8 ports for L2 banks, plus one for I/0

4 cycle latency (715ps/cycle).

Cycles 1-3 are for arbitration.

Transmit data on cycle 4.

100-200 wires/ port (each way).

9

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

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ethodology,ratioed

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A.

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usedfor

routingthe

asynchronousclocks.

Asyn-

chronousclock

domain

crossingsare

handledusing

FIFOs

andm

eta-stabilityhardened

flip-flops.A

llclock

headersare

designedto

supportclockgating

tosave

clockpow

er.Fig.11

shows

theblock

diagramof

thePL

L.Its

architectureis

similarto

theone

describedin

[8].Itusesa

loopfiltercapac-

itorreferenced

toa

regulated1.1

Vsupply

(VR

EG

).VR

EG

isgenerated

bya

voltageregulatorfrom

the1.5

Vsupply

coming

Au

tho

rize

d lic

en

se

d u

se

limite

d to

: Un

iv o

f Ca

lif Be

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ley. D

ow

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ed

on

Se

pte

mb

er 1

8, 2

00

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:03

from

IEE

E X

plo

re. R

estric

tion

s a

pp

ly.

Sun Niagara II 8 x 9 Crossbar

NAWATHE et al.: IMPLEMENTATION OF AN 8-CORE, 64-THREAD, POWER-EFFICIENT SPARC SERVER ON A CHIP 9

Fig. 9. L2 cache row redundancy scheme.

2-cycle latency. Addresses can be hashed to distribute accessesacross different sets in case of hot cache sets caused by refer-ence conflicts. All arrays are protected by single error correc-tion, double error detection ECC, and parity. Data from differentways and different words is interleaved to improve soft errorrates.

The L2 cache used a unique row-redundancy scheme. It is im-plemented at the 32 kB level and is illustrated in Fig. 9. Sparerows for one array are located in the adjacent array as opposed tothe same array. In other words, spare rows for the top array arelocated in the bottom array and vice versa. When redundancy isenabled, the incoming address is compared with the address ofthe defective row and if it matches, the adjacent array (which isnormally not enabled) is enabled to read from or write into thespare row. Using this kind of scheme enables a large ( 30%)reduction in X-decoder area. The area reduction is achieved be-cause the multiplexing required in the X-decoder to bypass thedefective row/rows in the traditional row redundancy scheme isno longer needed in this scheme.

N-well power for the Primary and L2 cache memory cellsis separated out as a test hook. This allows weakening of thepMOS loads of the SRAM bit cells by raising their thresholdvoltage, thus enabling screening cells with marginal static noisemargin. This significantly reduces defective parts per million(DPPM) and improves reliability.

Fig. 10 shows the Niagara2 Crossbar (CCX). CCX serves asa high bandwidth interface between the eight SPARC Cores,shown on top, and the eight L2 cache banks, and the non-cacheable unit (NCU) shown at the bottom. CCX consists of twoblocks: PCX and CPX. PCX (“Processor-to-Cache-Transfer”)is a 8-input 9-output multiplexer (mux). It transfers data fromthe eight SPARC cores to the eight L2 cache banks and theNCU. Likewise, CPX (“Cache-to-Processor Transfer”) is a

Fig. 10. Crossbar.

9-input 8-output mux, and it transfers data in the reverse di-rection. The PCX and CPX combined provide a Read/Writebandwidth of 270 GB/s. All crossbar data transfer requestsare processed using a four-stage pipeline. The pipeline stagesare: Request, Arbitration, Selection, and Transmission. As canbe seen from the figure, there are possiblesource destination pairs for each data transfer request. There isa two-deep queue for each source–destination pair to hold datatransfer requests for that pair.

IV. CLOCKING

Niagara2 contains a mix of many clocking styles—syn-chronous, mesochronous and asynchronous—and hence a largenumber of clock domains. Managing all these clock domainsand domain crossings between them was one of the biggestchallenges the design team faced. A subset of synchronousmethodology, ratioed synchronous clocking (RSC) is usedextensively. The concept works well for functional mode whilebeing equally applicable to at-speed test of the core using theSerDes interfaces.

A. Clock Sources and Distribution

An on-chip phase-locked loop (PLL) uses a fractional divider[8], [9] to generate Ratioed Synchronous Clocks with supportfor a wide range of integer and fractional divide ratios. Thedistribution of these clocks uses a combination of H-treesand grids. This ensures they meet tight clock skew budgetswhile keeping power consumption under control. Clock TreeSynthesis is used for routing the asynchronous clocks. Asyn-chronous clock domain crossings are handled using FIFOsand meta-stability hardened flip-flops. All clock headers aredesigned to support clock gating to save clock power.

Fig. 11 shows the block diagram of the PLL. Its architectureis similar to the one described in [8]. It uses a loop filter capac-itor referenced to a regulated 1.1 V supply (VREG). VREG isgenerated by a voltage regulator from the 1.5 V supply coming

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on September 18, 2009 at 17:03 from IEEE Xplore. Restrictions apply.

NAWATHE et al.: IMPLEMENTATION OF AN 8-CORE, 64-THREAD, POWER-EFFICIENT SPARC SERVER ON A CHIP 9

Fig. 9. L2 cache row redundancy scheme.

2-cycle latency. Addresses can be hashed to distribute accessesacross different sets in case of hot cache sets caused by refer-ence conflicts. All arrays are protected by single error correc-tion, double error detection ECC, and parity. Data from differentways and different words is interleaved to improve soft errorrates.

The L2 cache used a unique row-redundancy scheme. It is im-plemented at the 32 kB level and is illustrated in Fig. 9. Sparerows for one array are located in the adjacent array as opposed tothe same array. In other words, spare rows for the top array arelocated in the bottom array and vice versa. When redundancy isenabled, the incoming address is compared with the address ofthe defective row and if it matches, the adjacent array (which isnormally not enabled) is enabled to read from or write into thespare row. Using this kind of scheme enables a large ( 30%)reduction in X-decoder area. The area reduction is achieved be-cause the multiplexing required in the X-decoder to bypass thedefective row/rows in the traditional row redundancy scheme isno longer needed in this scheme.

N-well power for the Primary and L2 cache memory cellsis separated out as a test hook. This allows weakening of thepMOS loads of the SRAM bit cells by raising their thresholdvoltage, thus enabling screening cells with marginal static noisemargin. This significantly reduces defective parts per million(DPPM) and improves reliability.

Fig. 10 shows the Niagara2 Crossbar (CCX). CCX serves asa high bandwidth interface between the eight SPARC Cores,shown on top, and the eight L2 cache banks, and the non-cacheable unit (NCU) shown at the bottom. CCX consists of twoblocks: PCX and CPX. PCX (“Processor-to-Cache-Transfer”)is a 8-input 9-output multiplexer (mux). It transfers data fromthe eight SPARC cores to the eight L2 cache banks and theNCU. Likewise, CPX (“Cache-to-Processor Transfer”) is a

Fig. 10. Crossbar.

9-input 8-output mux, and it transfers data in the reverse di-rection. The PCX and CPX combined provide a Read/Writebandwidth of 270 GB/s. All crossbar data transfer requestsare processed using a four-stage pipeline. The pipeline stagesare: Request, Arbitration, Selection, and Transmission. As canbe seen from the figure, there are possiblesource destination pairs for each data transfer request. There isa two-deep queue for each source–destination pair to hold datatransfer requests for that pair.

IV. CLOCKING

Niagara2 contains a mix of many clocking styles—syn-chronous, mesochronous and asynchronous—and hence a largenumber of clock domains. Managing all these clock domainsand domain crossings between them was one of the biggestchallenges the design team faced. A subset of synchronousmethodology, ratioed synchronous clocking (RSC) is usedextensively. The concept works well for functional mode whilebeing equally applicable to at-speed test of the core using theSerDes interfaces.

A. Clock Sources and Distribution

An on-chip phase-locked loop (PLL) uses a fractional divider[8], [9] to generate Ratioed Synchronous Clocks with supportfor a wide range of integer and fractional divide ratios. Thedistribution of these clocks uses a combination of H-treesand grids. This ensures they meet tight clock skew budgetswhile keeping power consumption under control. Clock TreeSynthesis is used for routing the asynchronous clocks. Asyn-chronous clock domain crossings are handled using FIFOsand meta-stability hardened flip-flops. All clock headers aredesigned to support clock gating to save clock power.

Fig. 11 shows the block diagram of the PLL. Its architectureis similar to the one described in [8]. It uses a loop filter capac-itor referenced to a regulated 1.1 V supply (VREG). VREG isgenerated by a voltage regulator from the 1.5 V supply coming

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on September 18, 2009 at 17:03 from IEEE Xplore. Restrictions apply.

Every cross of blue and purple is a pass gate with a unique control signal.

72 control signals (if distributed unencoded).

NA

WA

TH

Eetal.:IM

PLE

ME

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Fig.9.L

2cache

rowredundancy

scheme.

2-cyclelatency.A

ddressescan

behashed

todistribute

accessesacross

differentsets

incase

ofhot

cachesets

causedby

refer-ence

conflicts.All

arraysare

protectedby

singleerror

correc-tion,double

errordetectionE

CC

,andparity.D

atafrom

differentw

aysand

differentw

ordsis

interleavedto

improve

softerror

rates.T

heL

2cache

useda

uniquerow

-redundancyschem

e.Itisim-

plemented

atthe32

kBleveland

isillustrated

inFig.9.Spare

rowsforone

arrayare

locatedin

theadjacentarray

asopposedto

thesam

earray.In

otherwords,spare

rows

forthetop

arrayare

locatedin

thebottom

arrayand

viceversa.W

henredundancy

isenabled,the

incoming

addressis

compared

with

theaddress

ofthe

defectiverow

andifitm

atches,theadjacentarray

(which

isnorm

allynotenabled)

isenabled

toread

fromor

write

intothe

sparerow

.Using

thiskind

ofschem

eenables

alarge

(30%

)reduction

inX

-decoderarea.The

areareduction

isachieved

be-cause

them

ultiplexingrequired

inthe

X-decoder

tobypass

thedefective

row/row

sin

thetraditionalrow

redundancyschem

eis

nolonger

neededin

thisschem

e.N

-well

power

forthe

Primary

andL

2cache

mem

orycells

isseparated

outas

atest

hook.T

hisallow

sw

eakeningof

thepM

OS

loadsof

theSR

AM

bitcells

byraising

theirthreshold

voltage,thusenabling

screeningcells

with

marginalstatic

noisem

argin.T

hissignificantly

reducesdefective

partsper

million

(DPPM

)and

improves

reliability.Fig.10

shows

theN

iagara2C

rossbar(C

CX

).CC

Xserves

asa

highbandw

idthinterface

between

theeight

SPAR

CC

ores,show

non

top,and

theeight

L2

cachebanks,

andthe

non-cacheable

unit(NC

U)show

natthe

bottom.C

CX

consistsoftwo

blocks:PC

Xand

CPX

.PC

X(“Processor-to-C

ache-Transfer”)is

a8-input

9-outputm

ultiplexer(m

ux).Ittransfers

datafrom

theeight

SPAR

Ccores

tothe

eightL

2cache

banksand

theN

CU

.L

ikewise,

CPX

(“Cache-to-Processor

Transfer”)is

a

Fig.10.C

rossbar.

9-input8-output

mux,

andit

transfersdata

inthe

reversedi-

rection.T

hePC

Xand

CPX

combined

providea

Read/W

ritebandw

idthof

270G

B/s.

All

crossbardata

transferrequests

areprocessed

usinga

four-stagepipeline.T

hepipeline

stagesare:R

equest,Arbitration,Selection,and

Transmission.A

scan

beseen

fromthe

figure,there

arepossible

sourcedestination

pairsfor

eachdata

transferrequest.T

hereis

atw

o-deepqueue

foreach

source–destinationpair

tohold

datatransfer

requestsfor

thatpair.

IV.

CL

OC

KIN

G

Niagara2

containsa

mix

ofm

anyclocking

styles—syn-

chronous,mesochronous

andasynchronous—

andhence

alarge

number

ofclock

domains.

Managing

allthese

clockdom

ainsand

domain

crossingsbetw

eenthem

was

oneof

thebiggest

challengesthe

designteam

faced.A

subsetof

synchronousm

ethodology,ratioed

synchronousclocking

(RSC

)is

usedextensively.T

heconceptw

orksw

ellforfunctionalmode

while

beingequally

applicableto

at-speedtest

ofthe

coreusing

theSerD

esinterfaces.

A.

Clock

Sourcesand

Distribution

An

on-chipphase-locked

loop(PL

L)usesa

fractionaldivider[8],[9]

togenerate

Ratioed

SynchronousC

locksw

ithsupport

fora

wide

rangeof

integerand

fractionaldivide

ratios.T

hedistribution

ofthese

clocksuses

acom

binationof

H-trees

andgrids.

This

ensuresthey

meet

tightclock

skewbudgets

while

keepingpow

erconsum

ptionunder

control.C

lockTree

Synthesisis

usedfor

routingthe

asynchronousclocks.

Asyn-

chronousclock

domain

crossingsare

handledusing

FIFOs

andm

eta-stabilityhardened

flip-flops.A

llclock

headersare

designedto

supportclockgating

tosave

clockpow

er.Fig.11

shows

theblock

diagramof

thePL

L.Its

architectureis

similarto

theone

describedin

[8].Itusesa

loopfiltercapac-

itorreferenced

toa

regulated1.1

Vsupply

(VR

EG

).VR

EG

isgenerated

bya

voltageregulatorfrom

the1.5

Vsupply

coming

Au

tho

rize

d lic

en

se

d u

se

limite

d to

: Un

iv o

f Ca

lif Be

rke

ley. D

ow

nlo

ad

ed

on

Se

pte

mb

er 1

8, 2

00

9 a

t 17

:03

from

IEE

E X

plo

re. R

estric

tion

s a

pp

ly.

10

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

11

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Crossbar defines floorplan: all port devices should be equidistant to the crossbar.

Uniform latency between all port pairs.

Did not scale up for 16-core Rainbow Falls. Rainbow Falls keeps the 8 x 9 crossbar, and shares each CPU-side port with two cores.

Sun Niagara II Crossbar Notes

Low latency: 4 cycles (less than 3 ns).

Design alternatives to crossbar?12

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Sun Niagara II Energy Facts

8 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 1, JANUARY 2008

Fig. 7. Various threads occupying different pipeline stages.

The load-use latency is three cycles. There is a six-cycle latencyfor dependent FP operations. The ICACHE is shared betweenall eight threads. Each thread has its own instruction buffer.The Fetch stage/unit fetches up to four instructions per cycleand puts them into the thread’s instruction buffer. Threadscan be in “Wait” (as opposed to “Ready”) state due to a ITLBmiss, ICACHE miss, or their Instruction Buffer being full. The“Least-Recently-Fetched” algorithm is used to select one of“Ready” threads for which the next instruction will be fetched.Fig. 7 shows the Integer/Load/Store pipeline and illustrateshow different threads can occupy different pipeline stages ina given cycle. In other words, threads are interleaved betweenpipeline stages with very few restrictions. The Load/Storeand Floating Point units are shared between all eight threads.The eight threads within each SPARC core are divided intotwo thread groups (TGs) of four threads each. Once again,the threads could be in “Wait” states due to events such as aDCACHE miss, DTLB miss, or data dependency. The “Pick”stage tries to find one instruction from all the “Ready” threads(using the “Least-Recently-Picked” algorithm) from each ofthe two TGs to execute every cycle. Since each TG picks inde-pendently (w.r.t. the other TG), it can lead to hazards such asload instructions being picked from both TGs even though eachSPC has only one load/store unit. These hazards are resolved inthe “Decode” stage.

Niagara2’s Primary and L2 cache sizes are relatively smallcompared to some other processors. Even though this may causehigher cache miss rates, the miss latency is well hidden by thepresence of other threads whose operands/data is available andhence can make good use of the “compute” time slots, thusminimizing wastage of “compute” resources. This factor ex-plains why the optimum design point moved towards havinghigher thread counts and lower cache sizes. In effect, this canbe thought of as devoting more transistors on chip to the in-telligent “processing” function as opposed to the nonintelligent“data-storing” function.

Performance measurements using several commercial ap-plications and performance benchmarks (SpecJBB, SpecWeb,TPC-C, SpecIntRate, SpecFPRate, etc.) confirm that Niagara2has achieved its goal of doubling the throughput performance

Fig. 8. Key statistical highlights.

and performance/watt as compared to UltraSPARC T1. Most ofthe gain comes from doubling the thread count and the numberof execution units. Some of the gain comes from a higheroperating frequency. Similarly, performance measurementsusing commonly used Floating Point benchmarks confirm thatNiagara2’s Floating Point throughput performance is more thanan order of magnitude higher compared to UltraSPARC T1.Niagara2 has eight Floating Point units (FPUs), each occupyingonly 1.3 mm , against only one FPU for UltraSPARC T1.Also, the Niagara2 FPUs are within the SPCs as comparedto UltraSPARC T1 where the SPCs had to access the FPUthrough the Crossbar. Another factor that helps performance isthe higher memory bandwidth on Niagara2.

C. Key Statistical Highlights

The table in Fig. 8 lists some key statistical highlights ofNiagara2’s physical implementation. Niagara2 is built in TexasInstruments’ 65 nm, 11LM, Triple- CMOS process. The chiphas 503 million transistors on a 342 mm die packaged in aflip-chip glass ceramic package with 1831 pins. It operates at1.4 GHz @ 1.1 V and consumes 84 W.

III. MEMORY HIERARCHY, CACHES, AND CROSSBAR

Niagara2 has four memory controllers on chip, each con-trolling two FBDIMM channels. They are clocked by the DR(DRAM) clock, which nominally runs at 400 MHz corre-sponding to the FBDIMM SerDes link rate of 4.8 Gb/s. Upto eight DIMMs can be connected to each channel. Everytransaction from each controller consists of 64 data bytes andECC. Read transactions take two DR clock cycles, while Writetransactions take four DR clock cycles. This yields a Readbandwidth of 51.2 GB/s and a Write bandwidth of 25.6 GB/s.

Niagara2 has two levels of caches on chip. Each SPC has a16 kB Primary Instruction cache (ICACHE), and a 8 kB PrimaryData cache (DCACHE). The ICACHE is 8-way set-associativewith a 32 B line size. The DCACHE is 4-way set-associativewith a 16 B line size. The 4 MB shared Level2 (L2) cache isdivided into eight banks for 512 kB each. The number of banksare doubled to support the doubling of thread count as comparedto UltraSPARC T1. The L2 cache is 16-way set associative witha 64 B line size. Each bank can read up to 16 B per cycle with a

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on September 18, 2009 at 17:03 from IEEE Xplore. Restrictions apply.

16 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 1, JANUARY 2008

Fig. 21. Power consumption.

Power EM spec. For example, for a typical layout of big buffers,the worst power EM violation reduced from of 1.57with a conventional M3 power grid to of 0.93 withM3 post grid. Similarly, IR drop from M4 to devices improvedfrom 89.1 mV to 55.8 mV.

An interactive script was used for insertion of DECAPs basedon available empty space, and the placement was always assuredto be DRC/LVS clean. The width of DECAPs used in stan-dard cell blocks matched the width of the standard cells. Thechannel DECAPs were similar to DECAPs used in standard cellblocks, except that they had M4 and below embedded into theleaf DECAP cell to reduce data base size. About 700 nF of ex-plicit DECAP was added on chip (this does not include implicitDECAP due to the metal power grid and the quiet cap).

VIII. POWER AND POWER MANAGEMENT

A. Power

Niagara2’s SOC design is optimized for performance/wattand enables reduction of total power consumption and powerdensity at the chip and system level. Niagara2’s simplifiedpipeline and reduced speculation in instruction execution re-duces wasted power. A Niagara2-based system is a lot morepower efficient as compared to, for example, a system with eightsingle-core processors (on separate chips) each having theirown I/O (DRAM, networking, and PCI-Express) interfaces.Such a system will have 8 times the I/O interfaces and hencewill consume a lot more power in those interfaces. Also, extrapower will be consumed in driving the off-chip multi-processorcoherency fabric. In comparison, for Niagara2 there are onlyone set of I/O interfaces and the coherency between the eightprocessor cores is handled on chip by the crossbar, whichconsumes less than 1 W of power.

Niagara2’s total power consumption is 84 W @ 1.1 V and1.4 GHz operation. The pie-chart in Fig. 21 shows the powerconsumed by the various blocks inside Niagara2. Almost athird of the total power is consumed by the eight SPARCcores. L2 cache Data, Tag and Buffer blocks together accountfor 20% of the total. SOC logic consumes 6% while I/Osconsume 13%. Leakage is about 21% of the total power. Clocksto unused clusters are gated off to save dynamic power. Within

units, clocks to groups of flops are separated into independentdomains depending upon the functionality of the correspondinglogic. Clocks to each domain can be turned off independentlyof one another when the related logic is not processing validinstructions. This saves dynamic power.

B. Technique to Reduce Leakage Power

Niagara2 uses gate-bias (GBIAS) cells to reduce leakagepower. GBIAS cells are footprint-compatible with the corre-sponding standard- non-GBIAS versions. The only layoutdifference is that the GBIAS cell has an additional identificationlayer (GBIAS). All the transistors of any cell having this layerare fabricated with 10% longer channel length.

The table in Fig. 22 illustrates the reduction in leakage andcorresponding increase in delay as the channel length was in-creased above minimum for three different gates. 10% largerchannel length was chosen, resulting in, on an average, about50% reduced leakage on a per-cell basis with about 14% im-pact on the cell delay. High- (HVT) cells were considered aswell for leakage reduction. We did not have an unconstrainedchoice of for the HVT cells. For HVT cells using the avail-able HVT transistors, the delay impact was much larger. Asa result, approximate calculations lead to the conclusion thatusing HVT cells would have enabled substitution of only aboutone-third of the number of gates as compared to using GBIASgates with 10% larger channel length. Hence, the GBIAS optionwas chosen. This enabled about 77% additional leakage savingas compared to using HVT cells. Cells in non-timing-criticalpaths could be replaced by their GBIAS versions as long as thisdid not result in any new noise, slew, or timing violations. Be-cause of footprint compatibility, the swapping was easily doneat the end of the design cycle without any timing, noise, or areaimpact. This reduced leakage power by 10%–15%.

The swapping algorithm works as follows. The project STAtool and a set of scripts determine which cells can be swappedwithout creating new timing, noise, and slew violations. First,all cells that have timing margins larger than a set thresholdare swapped to their GBIAS equivalent. The STA tool thencomputes the timing graph and swaps back all GBIAS cells thatare on paths with less than a predefined positive slack. Then,a script evaluates all the receivers connected to the outputsof the GBIAS cells that went through timing qualification,and determines if sufficient noise margin exists. The scriptcalculates the new noise values by increasing the latest noisesnapshot by a percentage that was derived from simulationsand analysis. Once a list of cells that can be safely swappedis built, a custom program performs the swaps in the actuallayout database. A footprint-compatibility check for identicalpins and metal shapes is built into the program to maintain LVSand DRC cleanliness.

C. Power Management

Niagara2 has several power management features to managepower consumption. Software can dynamically turn threads onor off as required. Niagara2 has a Power Throttling mode whichprovides the ability to control instruction issue rates to managepower. The graph in Fig. 23 shows that this can reduce dynamicpower by up to 30% depending upon the level of workload.

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on September 18, 2009 at 17:03 from IEEE Xplore. Restrictions apply.

18IE

EE

JOU

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AL

OF

SOL

ID-STA

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Fig.24.C

lock–datarecovery

ofa

singleFB

DIM

M1.0

receivechannelw

ithinan

FSRcluster.

Fig.25.C

lock-datarecovery

ofa

singleFB

DIM

M1.0

receivechannel(expanded)

forD

TM

.

i)the

linktraining

pattern(T

S0)can

beused

toidentify

thestart

ofa

clock-bundlepair,

andhence

controlthe

generationofthe

slowbyte

clockw

ithrespectto

TS0

starttim

es;ii)

thequeue

inthe

MC

Uw

hichperform

saggregation

ofthe

datato

constructframes

needto

waitfor

theslow

estbundle,and

thereforethe

slowestlink.

Fig.25illustrates

howthe

FBD

IMM

(andsim

ilarlyPC

I-Ex-

press)channels

may

bem

anipulatedto

generateclocks

within

anacceptable

tolerancefor

synchronouscrossing

intothe

con-troller.T

hecore

clockspeed

isallow

edto

varyindependently

suchthatthe

CM

P:DR

andC

MP:I/O

clockratios

arealw

aysin-

tegersin

DT

M.In

thism

anner,theprocessorcore

clockm

aybe

sweptfrom

8sys_clk

to15

sys_clkfor

functionalat-speedtesting.

Fig.26show

sthefrequency

versusshm

ooplotat95

Cfrom

firstsilicon.As

canbe

seen,thechip

operatesat1.4

GH

zat1.1

Vw

ithsufficientm

argin.Fig.26.

versusfrequency

shmoo

plot.

Auth

oriz

ed lic

ensed u

se lim

ited to

: Univ

of C

alif B

erk

ele

y. D

ow

nlo

aded o

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epte

mber 1

8, 2

009 a

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3 fro

m IE

EE

Xplo

re. R

estric

tions a

pply

.

18 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 1, JANUARY 2008

Fig. 24. Clock–data recovery of a single FBDIMM 1.0 receive channel within an FSR cluster.

Fig. 25. Clock-data recovery of a single FBDIMM 1.0 receive channel (expanded) for DTM.

i) the link training pattern (TS0) can be used to identifythe start of a clock-bundle pair, and hence control thegeneration of the slow byte clock with respect to TS0 starttimes;

ii) the queue in the MCU which performs aggregation ofthe data to construct frames need to wait for the slowestbundle, and therefore the slowest link.

Fig. 25 illustrates how the FBDIMM (and similarly PCI-Ex-press) channels may be manipulated to generate clocks withinan acceptable tolerance for synchronous crossing into the con-troller. The core clock speed is allowed to vary independentlysuch that the CMP:DR and CMP:I/O clock ratios are always in-tegers in DTM. In this manner, the processor core clock may beswept from 8 sys_clk to 15 sys_clk for functional at-speedtesting.

Fig. 26 shows the frequency versus shmoo plot at 95 Cfrom first silicon. As can be seen, the chip operates at 1.4 GHzat 1.1 V with sufficient margin. Fig. 26. versus frequency shmoo plot.

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on September 18, 2009 at 17:03 from IEEE Xplore. Restrictions apply.

13

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Intel Larrabee

14

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Intel Larrabee Market Concept

It’s easier to program a “normal” CPU than a GPU - so let’s make a GPU out of Intel CPU cores.

But mainstream out-of-order cores provide insufficient FLOPS for graphics work.

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Larrabee: A Many-Core x86 Architecture for Visual Computing • 18:3

ACM Transactions on Graphics, Vol. 27, No. 3, Article 18, Publication date: August 2008.

Solution: Make a many-core GPU out of an in-order implementation of IA-32 that includes a 16-wide vector unit.

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Larrabee: A Many-Core x86 Architecture for Visual Computing • 18:3

ACM Transactions on Graphics, Vol. 27, No. 3, Article 18, Publication date: August 2008.

15

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Intel Larrabee: Memory BW.

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08

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Larrabee Core

Each core has a low-latency path to a 256 KB subset of the coherent L2 cache.

Stores from a core are placed in its L2 slice. Tuned code works out of the slice.

Accesses to the L2 slices of other cores go over the ring network (higher latency).

16

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Intel Larrabee: Ring Network

Bi-directional ring network.512 wires each way. For large

chips, multiple linked rings.

Ring also provides path to off-chip DRAM and to special-purpose accelerators.

Contrast with Niagara II: In Larrabee, access to different L2 banks has non-uniform latency. Acceptable, given Larrabee’s graphics focus.

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ACM Transactions on Graphics, Vol. 27, No. 3, Article 18, Publication date: August 2008.

17

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Intel Larrabee

Ring network

18

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Core + 256KB L2 Cache slice

19

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Texture filtering units (for graphics)

20

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

DRAM and I/O Interfaces

21

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Intel Larrabee: Performance

!

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18:8 • L. Seiler et al.

ACM Transactions on Graphics, Vol. 27, No. 3, Article 18, Publication date: August 2008.

August 2008: Larrabee DirectX 9pipeline, used by video games.

Good scaling with # of cores.

!

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18:8 • L. Seiler et al.

ACM Transactions on Graphics, Vol. 27, No. 3, Article 18, Publication date: August 2008.

# of cores for high frame rates is a work in progress.

22

UC Regents Fall 2009 © UCBCS 250 L9: Floorplanning

Next Week: Practical design techniques

Thursday: Design blocks

Tuesday: Micro-architecture

23