Dr.SNS RAJALAKSHMI COLLEGE OF ARTS & SCIENCE(Autonomous)

Department of information technology

Course material

COMPUTER SYSTEM ARCHTECTURE

Class: I BSc IT “a”

Prepared by

S.JEYPRIYA

Assistant professor

Computer System Architecture UNIT I: DATA REPRESENTATION : Data Types – Number Systems – Radix , Decimal, Binary, Octal, Hexadecimal – Conversion – Octal and Hexadecimal Numbers – Decimal Representation – BCD – Alphanumeric Representation – ASCII – Complements – 9’s, 10’s, 1’s and 2’s Complement – 2’s Complement Addition – 2’s Complement Subtraction – Other Binary Codes – Gray Code – BCD – Weighted Code – Excess-3 Code – EBCIDIC – Error Detection.

UNIT II: DIGITAL LOGIC CIRCUIT: Digital Computers – Introduction – Block Diagram – Logic Gates – Definition – AND, OR, NOT, NAND, NOR, XOR, X-NOR with Truth Tables – Boolean Algebra – Introduction – Boolean Expression – Basic Identities – DeMorgan’s Theorem – Map Simplification – Karnaugh Map – Introduction – Minterm – Product of Sums Simplification – Don’t Care Conditions.

UNIT III: COMBINATIONAL CIRCUITS: Introduction – Block Diagram – Half Adder – Full Adder – Binary Adder – Parallel Binary Adder - Binary Subtractor. SEQUENTIAL CIRCUITS: Flip-flops – Introduction – SR flip-flop – D flip-flop – JK flip-flop –T flip-flop – Edge triggered flip-flop – Master – Slave.

UNIT IV: DIGITAL COMPONENTS : Integrated Circuits – Introduction – Decoders – NAND Gate Decoder – Decoder Expansion – Encoder – Multiplexer – Demultiplexer – Registers – Register With Parallel Load –Shift Registers – Binary Counters – Memory Unit – Random Access Memory (RAM) – Read Only Memory (ROM)

UNIT V: INPUT-OUTPUT ORGANIZATION: Peripheral Devices – ASCII – Input Output Interface – I/O Bus and Interface Modules – I/O versus Memory Bus – Isolated versus Memory –Mapped I/O- Examples of I/O Interface – Asynchronous Data Transfer – Strobe Control – Handshaking.

TEXT BOOK1. M.Morris Mano,”Computer System Architecture”- Prentice Hall of India ,2000REFERENCE BOOKS1. V.K. Puri, “DIGITAL ELECTRONICS CIRCUITS AND SYSTEMS” - TMH. 2. William Stallings, “Computer Organization and Architecture, Designing for Performance”-PHI/Pearson Education Asia,   2004.

UNIT - I

1.1 DATA REPRESENTATION

DATA TYPES A data type is a type of data. Data type is a data storage format that can contain a specific type or range of values. Computer programs store data in variables Each variable must be assigned a specific data type. Some common data types include integers, floating point numbers, characters, strings,

and arrays.

1.1.1 NUMBER SYSTEM A number system of base (also called radix) r is a system, which have r distinct symbols

for r digits. A number is represented by a string of these symbolic digits.

Number system can be divided into three typesThey are:

Binary number Octal number Decimal number Hexa decimal number

1.2.2 DECIMAL, BINARY, OCTAL, HEXADECIMAL & CONVERSION1. DECMAL   NUMBER   SYSTEM

Decimal system is the most commonly used number system. The decimal system has a base or radix of 10. The 10 separate symbols namely 0,1,2,3,4,5,6,7,8 and 9. Also called Arabic numerals. The digit of a number system is a symbol, which represents an integral quantity. The base or radix of a number system is defined as the number of different digits, which

can occur in each position in the number system.

2. BINARY   NUMBER   SYSTEM Base is 2. Two digits symbols are used : 0 and 1. The numbers in binary system are represented as combinations of these two symbols. The binary system uses powers of 2. To distinguish between different radix numbers, the digits will be enclosed in parenthesis

and radix is inserted as a subscript. The binary digit is also referred to as Bit

A string of 4 bits is called a nibble a string of 8 bits is called a byte. A byte is the basic unit of data in computers.

The number 125 actually means 1* 102 + 2* 101 +5*100 .

3.OCTAL   NUMBER   SYSTEM

The octal number system has a base or radix as 8 Eight different symbols are used torepresent numbers. These are commonly 0,1,2,3,4,5,6,7. The first 20 octal numbers and their decimal equivalents in the table 

Decimal Octal Decimal Octal0 0 11 131 1 12 142 2 13 153 3 14 164 4 15 175 5 16 206 6 17 217 7 18 228 10 19 239 11 20 2410 12 21 25

 First 20 Octal Numbers4. HEXADECIMAL   NUMBER   SYSTEM

The hexa decimal number system has a base or radix as 16 16 possible different numbers can be represented, the digits 0 through 9 and letters A, B, C, D, E and F are also used. Hexadecimal numbers are strings of these digits. The numbers in decimal, binary and hexadecimal is shown in the table.

Binary Hexadecimal Decimal0000 0 00001 1 10010 2 20011 3 30100 4 40101 5 50110 6 6

0111 7 71000 8 81001 9 91010 A 101011 B 111100 C 121101 D 131110 E 141111 F 15

First 16 Hexadecimal Numbers

CONVERSIONS

1. BINARY   NUMBER   TO   DECIMAL   NUMBER

1. (1011)2

=1*23 +0*22+1*21 +1*20

= 1*2*2*2+0*2*2+1*2+1*1=8+  0   + 2 + 1=11(1011)2 =(11) 10

2. (10001)2  =1*24+0*23+ 0*22+0*21 + 1*20

= 1*2*2*2*2+0*2*2*2+0*2*2+0*2+1*1= 16 + 0 + 0 + 0 + 1=17(10001)2 =(17) 10

2.  BINARY   NUMBER   TO   OCTAL   NUMBER

There is a simple trick for converting a binary number to an octal number. Simply group the binary digits into groups of 3, starting at the octal point, 

BINARY OCTAL000 0001 1010 2011 3100 4101 5110 6111 7

First 8 Octal Numbers

Let us convert the binary number 011101 into octal. 

011101 = 011 101=   3 5=   (3 5) 8

3. BINARY   NUMBER   TO   HEXADECIMAL   NUMBER

To convert binary to hexadecimal, a binary number into groups of four digits and convert each group of four digits according to the preceding code. Here are some

Example:1(10111011) 2  = 1011 1011

= B B

(10111011) 2=  (B  B) 16

Example:2 (10010101) 2  = 1001 0101

= 9 5(10010101) 2 = (9   5) 16

4. DECIMAL   NUMBER   TO   BINARY   NUMBER

To convert a decimal number into binary number it requires successive division by 2writing down each quotient and its remainder. The remainders are taken in the reverse order,which is the binary equivalent of the decimal number. 

The binary equivalent for 2510 =110012

To convert decimal fractions into equivalent binary fractions repeatedly double the decimal fraction. The number (0 or 1) that appears on the left is written separately. The bits that are written in this manner are read from top to bottom with a decimal point on the left. For example if the given number is 0.0625 conversion is done in the following manner.

Therefore, 0.062510 = .00012

5. DECIMAL   NUMBER   TO   OCTAL   NUMBER

Conversion from decimal to octal can be performed by repeatedly dividing the decimal number by 8 and using each remainder as a digit in the octal number being formed. 

Therefore (200)10 = (310)8

6. DECIMAL   NUMBER   TO   HEXADECIMAL   NUMBER

One way to convert decimal to Hexadecimal is the hex dabbles. The idea is as divide successively by 

16, writing down the remainders. 

Therefore (2429)10 = (9AF)16

7.   OCTAL   NUMBER   TO   DECIMAL   NUMBER To convert an octal number to a decimal number, we use the same sort of polynomial as

was used in the binary case, except that we now have a radix of 8 instead of 2. 

Example: (1213) 8

=1*83+2*82+1*81+3*80

=512 + 128 +  8   +  3 =651

Therefore (1213)8=(651)10

8.   OCTAL   NUMBER   TO   BINARY   NUMBER

The conversion from octal number to binary number is easily accomplished. Each octal bit is converted to its three digit binary equivalent.

Example: 1(26153.7406)8

(2 6 1 5 3   .    7 4 0 6) 8

(010  110  001  101  011 .  111  100  000  110) 2

Therefore (26153.7406)8 = (010 110 001 101 011 .111 100 000 110)2

9.   OCTAL   NUMBER   TO   HEXADECIMAL   NUMBER

The method of converting octal to hexadecimal number is to convert the given octal number to binary number and then arrange the binary digits into groups of 4 starting at the binary point.

Example :1 Convert octal number 714.06 to hexadecimal.

(714.06)8 =(111 001 100.000 110)2

=0001 1100 1100 . 0001 1000= 1 C C . 1 8

The hexadecimal equivalent of (714.06)8 is (1CC.18)16

10.  HEXADECIMAL   NUMBER   TO   BINARY   NUMBER

To convert a hexadecimal number to a binary number, convert each hexadecimal digit to its 4-bit equivalent using the code. 

Example :1 (   3 0 6 .   D)16

( 0011 0000 0110 . 1101)2

9 A F Therefore (306. D)16 = (9AF) 2

Example :2As another example, C5E2

C 5 E 2

1100 0101 1100 0010

Therefore (C5E2)16 = (1100 0101 1100 0010) 2

11. HEXADECIMAL   NUMBER   TO   OCTAL   NUMBER

The conversion of Hexadecimal number to octal  number involves two steps. First themethod suggests to go from hexadecimal to binary numbers and second from binary to octalnumbers  Convert the hexadecimal into binary by writing 4 bits binary value for each bit inhexadecimal number and then arrange the binary digits into groups of three starting at the binarypoint.

Example:1 Convert Hexadecimal (1E.C)  to octal conversion

(1E.C)16 = (0001 1110.1100)2= (011 110.110)=36.6

The octal equivalent of (1E.C)16  is (36.6)8

12.   HEXADECIMAL   NUMBER   TO   DECIMAL   NUMBER

The conversion of Hexadecimal to decimal is straightforward but time consuming. InHexadecimal number system each digit position corresponds to a power of 16. The weights ofthe digit positions in a hexadecimal number are as follows: For instance, BB representsExample:1

BB=B*161 +B*160

=11*16+11*1=176+11=187

BINARY ADDITION AND SUBTRACTIONBinary addition is performed in the same manner as decimal addition. The complete table for binary addition is as follows:

‘Carry over’ are performed in the same manner as in decimal arithmetic. Since 1 is the largest digit in the binary system, any sum greater than 1 requires that a digit be carried. Examples:

Subtraction is the inverse operation of addition. To subtract, it is necessary to establish a procedure for subtracting a larger from a smaller digit. The only case in which this occurs with

binary numbers is when 1 is subtracted from 0. It is necessary to borrow 1 from the next columnto the left. This is the binary subtraction table.

0-0=01-0=10-1=1 with a borrow of 11-1=0

Examples:

1.1.3 DECIMAL REPRESENTATION

BINARY CODE:

A binary coed is a group of n bits. A set of four elements can be codeed by a 2 bit code with any one of following bit combination: 00

01 10 11.

BINARY CODED DECIMAL

Most popular decimal code Bcd is different from converting a decimal number to binary number

1.1.4 APLHANUMERIC REPRESENTATION

Character

An alphanumeric character set is a set of elememts that includes the 10 decimal digits, 26 letters of the alphabet and number of special character such as +,- etc.

A set contains between 32 and 64 elements with both upper & lower case.

ASCII

Standard alphanumeric binary code is the ASCII(american standards code for information interchange)

Binary codes are required since registers can hold binary information only.

1.1.5 COMPLEMENTS

Complements are used to represent negative numbers in digital computers for simplifying the  subtraction operation and logical manipulation. 

There are two types of complements for each base –1 system.1.   The r’s Complement2.   The (r-1)’s Complement

When the value of the base is substituted the two types receive the names 2’s and 1’s complement for binary number or 10’s and 9’s complement for decimal numbers. 

The r’s complement is sometimes called as “True Complement”  The (r-1)’s complement as “Radix minus  one’s complement”.

1. The   (r-1)’s   complement Given a positive number N in base r with an integer part of N digits and a fraction part of

m digits, then (r-1)’s complements can be defined as rn   -   r m - N. 

The (r-1)’s complement in decimal  system is 9’s complement and 1’s complement in case of binary. 9’s complement of a decimal number is formed simply by subtracting every digit by 9. The 1’s complement of a binary number is even simpler to form, the 1’s are changed to 0’s and 0’s are changed to 1’s.

Example:  The 9’s complement of 52510 is

(105 -1) –52510

=99999-52510=47489

The 9’s complement of 0.3266 is

=(1-10-4 ) – 0.3266

=0.9999 – 0.3266=0.6733

The 9’s complement of 25.638 is

=(102 – 10-3 ) –25.638

=99.999-25.638=74.361

Examples of 1’s complement is as follows:Example:

The 1’s complement of 101100 is

=(26 – 1)-101100

=(1000000 – 1) – 101100=111111-101100=010011

The 1’s complement of (0110) is= 1001

2. The   r’s   complement

Given a positive number N in base r with an integer part of n digits the r’s complement of

N is defined as rn- N for N  0 and 0 for N=0. 

The r’s complement in decimal system is 10’s complement and 2’s complement in case of binary system.

2’s complement of 101101 is obtained from the 1’s complement 010010 by adding 1 togive 010011.

10’s complement can be formed by forming 9’s complement and then adding a 1 to theleast significant digit.

1.1.6 9’S , 10’S , 1’S AND 2’S COMPLEMENTSome numerical examples of 10’s complement is as follows:Example:

The 10’s complement of (52510)10 is

=105 –52510

=47490

The 9’s complement of 326 is=999-326=673

The 10’s complement of 25.63810 is

=102 –25.638

=74.362 TWO'S COMPLEMENT

The two's complement of a binary number is obtained by:1. Replacing all the 1's with 0's and the 0's with 1's. This is known as its one's complement.2. Adding 1 to this number by the rules of binary addition.

Now you have the two's complement.Example:The decimal subtraction 29 - 7 = 22 is the same as adding (29) + (-7) = 22

1. Convert the number to be subtracted to its two's complement:

00000111 (decimal 7)11111000 (one's

complement)+

00000001(add 1)

11111001 (two's complement)

2. 11111001 now represents -7.

3. Add

29

00011101

+- 7

11111001

22

(1)00010110

Note that the final carry 1 is ignored.

The r’s complement can be obtained from the (r-1)’s complement after the addition of rto the least significant digit.

1.1.7 COMPLEMENTS ADDITION AND SUBTRACTION1. Binary subtraction using 1’s complement method:

Step1: Find 1’s complement of the number to be subtracted(subtra hend).Step2: Perform binary addition of this 1’s complement number with the given first number(minuend).Step3: Any end-around carry found, add to the least significant bit.

Example :

11001 11001-10110 = + 01001

1 00010 (end-carry is added to the least significant bit) 1

------------Ans: = 00011

------------2. Binary subtraction using 2’s complement method:

Step1: Find 2’s complement of the number to be subtracted(subtra hend).Step2: Perform binary addition of this 2’s complement number with the given first number(minuend).Step3: Any end-around carry found, drop it.

Example :

11011 11011-11001 = + 00111 ----------------- 1 00010 (carry is dropped). ------------------ Ans: = 00010.

2’s Complement Arithmetic

1. 47 + 23

    Since 47 and 23 are not negative integers, we don't have to use two's complement for addition.      47 = (32 + 8 + 4 + 2 + 1) = 101111     23 = (16 + 4 + 2 + 1) = 10111

     1 1 1 1 1    carry row     1 0 1 1 1 1+         1 0 1 1 1

   1 0 0 0 1 1

1000110 = 70

Notice that no sign bit is added in this instance, nor is the leftmost bit to be interpreted as a negative.

2. 56 + (-19)    56 = 111000 = 0111000   (Did you forget the sign bit?)    19 = 0010011

       Two's complement of 0010011 = 1101101

     1 1 1        carry row     0 1 1 1 0 0 0  +   1 1 0 1 1 0 1     1 0 1 0 0 1 0 1

       After truncating the overflow '1', we get the positive number 0100101, which equals 37.

3. 72 + (-100)    72 = 01001000     100 = 01100100, and the two's complement of 01100100 = 10011100.

                      1 1       carry row     0 1 0 0 1 0 0 0   + 1 0 0 1 1 1 0 0      1 1 1 0 0 1 0 0

There is no overflow, and the leftmost digit is a 1, indicating that the result is a negative number.  First use 2's complement to convert 11100100 to 00011011, then convert 00011011 to decimal representation and take the negative. The answer is -28.

4. (-35) + (-58)     -35 = -00100011 = 11011101 (two's complement of 35)     -58 = -00111010 = 11000110 (two's complement of 58)

    1   1 1 1       carry row     1 1 0 1 1 1 0 1 +   1   1 0 0 0 1 1 0

  1 1 0 1 0 0 0 1 1

1.2 OTHER CODES: 1.2.1 GRAY CODE

Digital systems can process data in discrete form only.  Many physical systems supply continuous output data. The data must be converted into digital 

form before they can be used by a digital computer.  Continuous, or analog information is converted into digital form by means of an analog  to

digital  converter.   The  reflected  binary  or  gray  code is  shown  in  the  table  is sometimes used for the 

converted digital data. The advantage of the gray code over straight binary numbers is that the gray code changes by only one bit as it sequences from one number to the next.  In other words, the change from any number to the next in sequence

 is recognized by a change of only one bit from 0 to 1 data is represented by the continuous change of a shaft position.

The shaft is partitioned into segments with each segment assigned a number.

Gray Code Decimal Equivalent Gray Code Decimal Equivalent0000 0 1100 80001 1 1101 90011 2 1111 100010 3 1110 110110 4 1010 120111 5 1011 130101 6 1001 140100 7 1000 15

4 Bit Gray Code

1.2.2 BINARY CODED DECIMAL

In BCD number system a group of binary bit is used to represent each of 10 decimaldigits. For instances, an obvious and natural code is a simple weighted binary code as shown inable.

BINARY CODE DECIMAL DIGIT0000 00001 10010 20011 30100 40101 5

0110 60111 71000 81001 9 Binary Coded Decimal

This is known as a binary coded decimal 8421 code or simply BCD. Notice that 4 binarybits are required for each decimal digit and each bit is assigned a weight;  for instance the rightmost bit has a weight of 1, and the leftmost bit in each  code group has a weight of 8.  By

adding the weights of the positions in which 1’s appear, the decimal digit represented by a code group may be derived. 

For the decimal number 1246 to be represented, 16 bits are required: 1 2 4 6

0001  0010  0100  0110Examples:

Convert decimal 4019 to BCD4 0 1 9

0100 0000 0001 1001The BCD equivalent of (4019) 10 is 0100 0000 0001 1001

Convert BCD number 0001 1001 0000 0111 to decimal

0001 1001 0000 01111 9 0 7

BCD numbersare useful wherever decimal information is transferred into a computer.  The pocket calculator is one of the best examples for the application

of BCD numbers. Other examples of BCD system are electronic counters, digital voltmeter and digital clocks.

1.2.3 WEIGHTED CODE Each position of the number has a specific weight. Some example code are 8421, 2421, and 5211. Ith bits are multiplied by the weights indicated and the sum of the weighted bits ghives decimal

digits Example: 1101 using 2421 code

= 2*1+4*1+2*0+1*1=2+4+0+1=7

1.2.4 EXCESS – 3 CODE The Excess-3 code is a decimal code that has been used in older computers. 

This is an un-weighted code. Its binary code assignment is obtained from the corresponding BCD equivalent binary number after the addition of binary 3 (0011).

DECIMAL BCD EXCESS 3 CODE0 0000 00111 0001 01002 0010 01013 0011 01104 0100 01115 0101 10006 0110 10017 0111 10108 1000 10119 1001 110010 0001 0000 0100 001111 0001 0001 0100 0100

Excess – 3 code

1.2.5 EBCDIC CODE

Extended BCD interchange code It is a alphanumeric code Same character symbols as ASCII but the bit assignment to characters are different It is used for business oriented purpose.

1.2.6 ERROR DETECTION AND ERROR CORRECTION An error detection code is a binary code that detects digital errors during transmission Detected errors cannot be corrected but there is indicated Common error detection code is used in parity bit Parity bit is an extra bit included with a binary message to make the total number of 1’s either

odd or even. If an additional bit is added to make the total number of 1’s an odd number. Then it is called an

odd parity The total number of 1’s in the resulting code is even then it is called an even parity. Additional parity bit is normally placed on the left of the MSB Example:

Parity bit

Data Odd parity total number

1 101010 5

10 110101

15

1 0100100

3

0 1010010

3

Resulting code has one parity and seven data bits. It forms an eight bit word which is transmitted to the receiver.

Parity bit

Data Even parity total number

1 1101011

6

0 1011111

6

1 1001001

4

0 1001000

2

Example: 11010101 are received as 11010111 due to error because of some failure.

QUESTIONS:

1) ___________ called as cyclic or reflected code. a) BCD Code b) Excess-3 Code c) Gray Code 4) Alphanumeric Code

2) Nibble represents the _____________. a) 4 digit number b) 3 digit number c) 8 digit number 4) 16 digit number

3) Convert 11011 to the 1’s complement a) 00100 b) 01001 c) 00101 d) 11100

4) For detecting error we use________________ a) Parity Method b) Hamming Code Method c) Radix Method d) None

5) Convert 1011110000 to its equivalent decimal number a) 752 b) 758 c) 975 d) 684

6) Convert the Octal number 724 to its equivalent decimal number a) 468 b) 486 c) 846 d) 648

7) Convert Hexadecimal number A1BE to equivalent decimal number a) 4542 b) 4242 c) 4545 d) 4142

8) Convert 12 to its equivalent BCD number a) 0010 0001 b) 1010 1000 c) 0001 0010 d) 0001 1010

9) Convert BCD number 1101 1111 0000 to its equivalent decimal number a) 13 15 0 b) 15 12 0 c) 14 15 0 d) 15 11 0

10) Convert the 14 into Excess-3 code a) 0100 0111 b) 1000 0111 c) 1010 1111 d) 1111 1010

11) Convert 33 to Excess-3 Code a) 1001 1001 b) 0110 0110 c) 1000 0110 d) 1010 1111

12) Convert 1111001100 to Grey Code a) 1000101010 b) 1000101110 c) 1111000111 d) 1111100000

13) Convert 0011001111 to Grey Code a) 0010101011 b) 0010111100 c) 0011101000 d) 0010101000

14) Convert the 10101001 to 1’s Complement a) 01010110 b) 01010111 c) 10101001 d) 011110111

15) Convert 2468 to 9’s Complement a) 0111 0101 1100 0001 b) 0111 0101 0011 0001 c) 1000 1110 1111 0000 d) none

UNIT II

2.1 DIGITAL LOGIC CIRCUIT: DIGITAL COMPUTERS

Digital computer is a digital system that performs various computational tasks. Digital means it is information that represents the values A digital computer has two digits 0 and 1. A binary digit is called a bit Information is represented in digital computer in a group of bits.

The input-process-output concepts of the computer are:

Input: The computer accepts input data from the user via an input device like keyboard. The input data can be characters, word, text, sound, images, document, etc.

Process: The computer processes the input data. For this, it performs some actions on the data by using the instructions or program given by the user of the data. The action could be an arithmetic or logic calculation, editing, modifying a document, etc. During processing, the data, instructions and the output are stored temporarily in the computer’s main memory.

Output: The output is the result generated after the processing of data. The output may be in the form of text, sound, image, document, etc. The computer may display the output on a monitor, send output to the printer for printing, play the output, etc.

Storage: The input data, instructions and output are stored permanently in the secondary storage devices like disk or tape. The stored data can be retrieved later, whenever needed.

2.1.1 LOGIC GATES :

Gates:

Gates are logic circuits that performs the manipulation of binary information with one or more inputs and a single output

Gates are hardware that produce signals of binary 1 or 0 It has distinct symbols and its operation can be described by means of logical expression

Truth table:

A truth table is a table that describes the behavior of a logic gate It lists the value of output for every possible combination of the inputs

2.1.2 DEFINITION AND gate:

AND gate has two or more inputs and only one output If both inputs are high the output is high If any one of the input is low the output is low

Symbol:

OR gate:

OR gate has two or more inputs and only one output If one or more of its input is high the output is high If both the inputs are low the output is low

NOT gate or INVERTER:

An inverter or not gate has only a single input and a single output signal

It inverts or complements the given input

NAND gate: (NOT- AND)

NAND gate has two or more inputs but only one output It produces the complement of AND output The output is high when any of the inputs are low and the output is low when all of its inputs are high

NOR gate: (NOT- OR)

NOR gate has two or more inputs but only one output. It produces the complement of OR The output is high only when all inputs are low and the output is low if any of the input is high

EXCLUSIVE OR gate ( XOR) :

XOR gate has two or more inputs but only one output Output is high if one, and only one, of the inputs to the gate is high If both inputs are low or both inputs are high the output is low An encircled plus sign ( ) is used to show the EOR operation.

Symbol :

EXCLUSIVE NOR gate (XNOR):

XOR gate has two or more inputs but only one output It produces the complement or inverse of XOR output Output is high  if both of the inputs are the same The XOR gate with inputs A and B implements the logical expression A . B +

A . B Symbol

Truth table

2.2 BOOLEAN ALGEBRA :

Boolean algebra is used to solve the logic problems by expressing the statements and functions as symbols and then manipulating them to arrive at a result

It is a switching algebra that deals with binary variables and logical operations.

Consider A+A’ = 1A.A’ = 0

ie (A+B)+(A+B)’=1 AND (A+B).(A+B)’=0 (A+B)+(A’.B’)=1 AND (A+B).(A’.B’)=0

2.2.1 BOOLEAN EXPRESSIONS Consider the following Boolean expressions

1. Simplify the Boolean expressionXY′Z′+XY′Z′W+XZ′The above expression can be written asXY′Z′ (1+W) +XZ′=XY′Z′+XZ′ as 1+W=1=XZ′ (Y′+1)=XZ′ as Y′+1=1

2. Simplify the Boolean expressionX+X′Y+Y′+(X+Y′) X′YThe above expression can be written asX+X′Y+Y′+XX′Y+Y′X′Y=X+X′Y+Y′ as XX′=0, and YY′=0=X+Y+Y′ as X+X′Y=X+Y=X+1 as Y+Y′=1=1 as X + 1=1

3. Simplify the Boolean expressionZ(Y+Z) (X+Y+Z)The above expression can be written as(ZY+ZZ)(X+Y+Z)= (ZY+Z) (X+Y+Z) as ZZ=Z=Z(X+Y+Z) as Z+ZY=Z=ZX+ZY+ZZ=ZX+ZY+Z as ZZ=Z,=ZX+Z as Z+ZY=Z=Z as Z+ZX=Z

DE MORGAN’S THEOREMS De Morgan’s First Theorem: Statement: It states that for any two elements A and B in Boolean Algebra, the complement of a sum is equal to the product of complements.

A + B = A . B

Logic circuit:

AA

Y Y

B B

De Morgan’s Second Theorem:

Statement:

It states that for any two elements A and B in a Boolean algebra, the complement of a product is equal to the sum of complements

A . B = A + B

Logic circuit:

A A

B Y B Y

2.2.2 BASIC IDENTITIES

Boolean algebra equations can be manipulated by following a few basic rules.

Manipulation Rules  A + B = B + A  A * B = B * A  (A + B) + C = A + (B + C)  (A * B) * C = A * (B * C)  A * (B + C) = (A * B) + (A * C) 

A B Y=A . B0 0 00 1 01 0 01 1 1

A B Y= A + B

0 0 1

0 1 1

1 0 1

1 1 0

 A + (B * C) = (A + B) * (A + C)Equivalence Rules  =  A = A        (double negative)  A + A = A  A * A = A      _  A * A = 0      _  A + A = 1

Rules with Logical Constants  0 + A = A  1 + A = 1  0 * A = 0  1 * A = A

2.2.3 DE MORGAN’S THEOREMS Example 1:

Prove mathematically De Morgan’s Theorems: for any two elements A and B in Boolean algebra

A+B = A . B

A.B = A + B

Theorem 1: A+B = A . B Proof:

We know that a + a = 1 and a. a = 0i.e (A+B) + A + B = 1 and (A + B ). (A + B ) = 0

To Prove:(A+B) + A . B = 1 and (A + B ). (A. B ) = 0

Solution:(A+B) + A . B = {(A + B ) +A} . {(A + B ) + B}

= {B+(A + A )} . { A + (B + B)} = (B+1) . ( A+1) = 1 . 1 = 1

And (A + B ) . (A . B) = {A . ( A . B )} + {B . (A . B)} = { (A. A) . B } + { (B . B) . A } = ( 0 . B ) + ( 0 . A )

= 0 + 0 = 0

Theorem 2: A . B = A + B

Proof:

We know that a + a = 1 and a. a = 0

i.e., A . B + A . B = 1 and A . B . (AB ) = 0

To Prove:

A.B + ( A + B ) = 1 and A . B . ( A + B ) = 0

Solution:

A . B + (A + B ) = ( A + B ) + A . B ={ ( A + B ) + A} . {(A + B ) +B } = (A + A + B ) . ( B + B + A ) = ( 1 + B ) . ( 1 + A ) = 1

And A . B . (A + B ) = { ( A . B ) . A} + { (A . B ) . B } = { (A . A ) . B ) } + { ( B . B ) . A ) = ( 0 . B ) + ( 0 .+ A ) = 0

Example: prove the identities using Boolean algebra(a) A . B + C . D = ( A + C )( A + D)( B + C )( B + D ) To Prove : AB + CD = ( A + C )( A + D)( B + C )( B + D )

Solution :

L.H.S = AB + CD = (AB) + C . D= (AB+C) . (AB + D)= ( C + A . B) . ( D + A . B)= (C + A ) ( C+ B ) ( D + A) ( D+ B)= ( A + C) ( A + D) ( B + C ) ( B + D)= R.H.S

(b) (A + BC + C ) C = ABC + ABC + ABCTo Prove :(A + BC + C) C = ABC + ABC + ABCSolution : L.H.S = (A + BC + C) C

= AC + BCC + CC= AC + BC + 0

= A(B+B) . C + (A+A) BC

= ABC + ABC + ABC + ABC= ABC + ABC + ABC + ABC= ABC + ABC + ABC = R.H.S

(c) A (A + C ) (AB + C ) = 0To Prove :A (A + C ) (AB + C ) = 0Solution :

L.H.S = A(A+C) . ( AB + C)= (AA + AC) . ( AB + C)= 0 + AC . ( AB + C)= ACAB + ACC= AABC + A . CC= 0 . BC + A . 0= 0 + 0= 0 = R.H.S

2.2.4 MAP SIMPLIFICATION:

KARNAUGH’S MAP

The map method was proposed by E.W.Veitch and later modified by M.Karnaugh. This provides a simple set procedure for minimizing the switching function. This map method /pictorial representation of the truth table is called as Veitch-Karnaugh (V-K) map or

Karnaugh map. Made up of squares – each square represents one term. Each n variable map contains of 2n cells. (If n=3 then map contains 8 cells)

A three- variable Karnaugh Map A four – variable Karnaugh Map

Take 3-variable Karnaugh map : AB=01 C=0 so ABC = 010 whose decimal value = 2

AB

CD

00 01 11 10

00 0 4 12 8

01 1 5 13 9

11 3 7 15 11

10 2 6 14 10

AB – top values (00,01,11,10) C - down values (0,1)Take 4-variable Karnaugh map : AB=01 CD=01 so ABCD=0101 whose decimal value= 5AB – top values CD - down values (00,01,11,10)

CANONICAL FORM 1

Decimal

Value

A B C Minterm Maxterm

0 0 0 0 A’ B’ C’ A+B+C

1 0 0 1 A’ B’ C A+B+C’

2 0 1 0 A’ B C’ A+B’+C

3 0 1 1 A’ B C A+B’+C’

4 1 0 0 A B’ C’ A’+B+C

5 1 0 1 A B’ C A’+B+C’

6 1 1 0 A B C’ A’+B’+C

7 1 1 1 A B C A’+B’+C’

2.2.5 MINTERMS AND MAXTERMS FOR THREE VARIABLES

Minterms :

A product term which has each of the variables as factors in either complemented or uncomplemented form is known as minterm.

A function with n variables has 2n minterms A three-variable function, such as f(x,y,z), has 23 = 8 minterms. Any variable should be taken in uncomplemented form if it has the value ‘1’ and should be taken in

complemented form if it has the value ‘0’. For example 001 should be written as C

Maxterms : A sum term which has each of the variables in either complemented or uncomplemented form is

known as maxterm. A function with n variables has 2n maxterms A three-variable function, such as f(x,y,z), has 23 = 8 maxterms. Any variable should be taken in uncomplemented form if it has the value ‘0’ and should be taken in

complemented form if it has the value ‘1’. For example 001 should be written as A+B+ .

SUM OF PRODUCTS (SOP) :

The switching function expressed as the sum of all the minterms for which the function attains the value ‘1’ is called the Canonical Sum of Products (SOP) or disjunctive normal expression.

Σ denotes sum of product.Consider the following truth table. The function attains the value in ‘1’ in 4 cases.

Therefore, SOP = (1, 2, 4, 7) // 1,2,4,7 have the output 1

= 001+010+100+111 f(A,B,C) = C + B + A +ABC

Product of Sum (POS):

The expression expressed as product of all the maxterms for which the function attains the value ‘0’ is known as the canonical product of sums (POS) or conjunctive normal expression.

π denotes product of sum.

POS = (0, 3, 5, 6) // 0,3,5,6 have the output 0 = 0, 3, 5, 6 = (000) (011) (101) (110) = (A+B+C)(A+ + )( +B+ )( + +C)

FINDING THE CANONICAL SUM OF PRODUCTS (SOP) FORM FOR AN EXPRESSION:

Step 1 : When any switching expression is to be expressed in canonical SOP forms, then each term of the expression should be examined and if it is a minterm , then it should be kept as it is.

Eg : AB - all the 3 variables are present – so it is a minterm and hence kept as it is.

Step 2 : If any particular variable does not occur in any term, then for each variable A,B or C which does not occur, multiply that term by (A+ ),(B+ ) or (C+ ) as the case may be.

Decimal Value

A B C f

0 0 0 0 01 0 0 1 12 0 1 0 13 0 1 1 04 1 0 0 15 1 0 1 06 1 1 0 07 1 1 1 1

Eg : A – here C is missing so multiply this term by (C+ ). A (C+ ) = A C + A

Step 3 : Eliminate the repeated terms.

Example: Find the canonical SOP and POS for the given expression.

f(A,B,C) = AB + +AC +

f(A,B,C) = AB + +AC + = AB(C+ ) + (C+ ) +AC(B+ ) + (B+ ) (step 2) = AB C+ AB + C+ +AC B +AC + B +

Eliminating the repeated terms, we get (step 3) f(A,B,C) = AB C+ AB + C+ ++A C+ B = 111 + 110 + 001+000+101+010

= (7,6,1,0,5,2)

SOP = (0,1,2,5,6,7)

POS = Complement of SOP = (3,4) = (011,100) = (A + + )( +B+C)

FINDING THE CANONICAL PRODUCT OF SUM (POS) FORM FOR AN EXPRESSION:

Step 1 : When any switching expression is to be expressed in canonical POS forms, then each term of the expression should be examined and if it is a maxterm , then it should be kept as it is. Eg : A+B+ - all the 3 variables are present – so it is a maxterm and hence kept as it is.

Step 2 : If any particular variable does not occur in any sum term, then for each variable A,B or C which does not occur, add that term by A , B or C as the case may be.Eg : A+ – here C is missing so add this term by (C ). (A+ +C ) = (A+ +C) ( A+ + )

Step 3 : Convert the sum terms into product of sums.

Step 4 : Eliminate the repeated terms.

Example : Find the canonical POS and SOP for the given switching functions.

f(A,B,C) = ( ).(B+ ) = ( +B + C ).(B+ + A ) (step 2) = (( +B)( + )+ C ).(A+B+ ).( +B+ ) (Step 3) = [(( +B)( + )+ C).( ( +B)( + )+ )] . [(A+B+ ).( +B+ )] = ( +B+C)( + +C) ( +B+ )( + + )(A+B+ ).( +B+ )

Eliminating the repeated terms, we get (step 4) POS = ( +B+C)( + +C) ( +B+ )( + + )(A+B+ ) = (100) (110) (101) (111) (001) = (4,6,5,7,1) = (1,4,5,6,7)

To get SOP , multiply each variable by the absent variable.

f(A,B,C) = ( ).(B+ ) = B+ = B(C+ )+ (B+ ) = BC+ B + B + = BC+ B + (deleted B as it has repeated twice) = 011+010+000

= (3,2,0)

SOP = (0,2,3)

Example : From the truth table given below , express the function f in sum of minterms and product of maxterms . Obtain the switching function f(A,B,C) in canonical SOP and POS from and prove that they both minimize to same value.

Decimal value

A B C f

0 0 0 0 11 0 0 1 12 0 1 0 03 0 1 1 04 1 0 0 15 1 0 1 16 1 1 0 07 1 1 1 0

Solution:The decimal value for which the function f assumes value ‘1’ are 0,1,4,5

= (0,1,4,5)

f=000+001+100+101 = Sum Of Minterms

f(A,B,C) = + C+A +A C = SOP form

The above form can be minimized to = ( +C)+ A (C+ ) (Since (C+ ) = 1) = + A

= (A+ ) = .1 =

The decimal value for which the function f assumes value ‘0’ are 2,3,6,7 = (2,3,6,7)

=(010)(011)(110)(111) = Product Of Maxterms

f(A,B,C) = (A+ +C)(A+ + )( + +C)( ) = POS form

The above form can be minimized to = [(A+ )(C+ )][( + )( C+ )]

= (A+ )( + ) = A +A + +

= 0+ (A+ )+ = + =

Hence the minimization of both canonical SOP and POS gave the same value ( ).

KARNAUGH’S MAP – CONSTRUCTION AND PROPERTIES

The Karnaugh map is a modified from of Venn diagram of a switching function with 4 or less variables in the canonical SOP form.

When a venn diagram is redrawn using rectangles and squares and complemented and uncomplemented variables are represented by 0’s and 1’s, in the columns or rows which it represents, then the diagram is called Karnaugh Map.

Each square of K map is denoted by a binary number or its decimal number. If the function has n variables then there must be 2n squares. For example if there are 4 variables then

the map has 24=16 squares. To construct a Karnaugh map of a switching function, first the function is represented in the sum of

products form. Example : f(A,B,C) = + C+ B + BC+ ABC

= 000+001+010+011+111

= (0,1,2,3,7)

The above function is represented on Karnaugh Map by marking the squares by ‘1’

The decimal numbers are usually written in small numerals at the bottom right corner of the squares

representing a decimal number. Example : f(A,B,C,D) = (0,1,3,7,11,15)

The simplification of the switching function can be done by combining the ‘1’ cells into pairs, quartets and octets as the case may be.

Minterms of adjacent squares in the map are identical except for one variable, which appears complemented in one square and uncomplemented in the adjacent square.

Eg : In the above K map take the first row - first two cells having the decimal value 0,4 i.e 0000 ()and 1000(A ) here only one variable ‘A’ appears complemented in one square and

uncomplemented in another square. According to this definition of adjacency

The square of the extreme ends of the same horizontal row are adjacent. Eg : 0(0000), 8(1000)The square of the top and bottom squares of a column are adjacent. Eg : 0(0000), 2(0010)The four corner squares of a map are adjacent. Eg : 0000,1000 ,0010,1010 - i.e [0000,1000] [0000,0010] [1000, 1010] [0010,1010]

Examples :

1. Simply the Boolean function f(A,B,C) = ( 3,4,6,7)

Solution

Pairs are (6,4) and (3,7) Before minimization the function is written as BC+A +AB +ABC After minimization the function is written as BC+A . 6 is written as AB and the adjacent square 4 is written as A . The common term is A

. 3 is written as BC and the adjacent square 7 is written as ABC. The common term is BC. Hence BC+A .

To check :

f = ( 3,4,6,7)

f = BC+A +AB +ABC = BC+ABC+A +AB (rearranged) = BC( +A)+A ( +B) = BC+A .

2. Simplify the switching function f(A,B,C,D) = (0,1,2,3,8,9,10,11)

Solution

a. Simplification Using K Map :

‘1’ is marked in the respective squares. See the common variable in all these squares. In 0(0000), 1(0001), 2(0010), 3(0011) – the common variable

is In 8(1000), 9(1001), 10(1010), 11 (1011) – the common

variable is A So + A

= ( +A) = The function in minimized form is

b.Simplification using Boolean Algebra :

f = + D+ C + C D+A +A D+A C +A CD= ( +D)+ C( +D)+ A ( +D)+ A C( +D) = ( +C)+ A ( +C)= ( + A) = .

IMPLICANTS :

When a switching function of four or less than four variables is represented on a K map, then the set of adjacent minterms or the simplified product term obtained by combining the minterms of set are called implicants of the switching function

Prime-Implicant : An implicant is called a prime-implicant of the switching function if it is not a subset of any other implicant of the switching function.

Essential Prime-Implicant : A prime-implicant which includes a ‘1’ cell , which is not included in any other prime-implicant , on the K map, is known as an essential prime-implicant of the switching function.

MINIMIZATION IN SOP FORM USING KARNAUGH MAP :

1. Minimize the Boolean function f (A,B,C)= + B + BC using K map.Solution :

f (A,B,C)= + B + B C = 000+010+011 = (0,2,3)

Mark ‘1‘is made in 3 cells.

Take first row (0,2) , the two cells are adjacent. The value is 000 and 010, only variable B appears complemented in 0(000) and uncomplemented in 2(010). Hence this can be written as (common terms).

Take second column (2,3), the two cells are adjacent as only one variable (C) appears complemented in one and uncomplemented in another. Hence this can be written as B (common terms).

Thus the Boolean function + B + B C is minimized to + B.

2. Minimize the Boolean function f (A,B,C)= + B + A +AB using K map.

Solution :

f (A,B,C)= + B + A +AB = 000 + 010 +100+110

= (0,2,4,6)

‘1’ is marked in the first row. The cells are adjacent . The common term is and the terms that appears complemented and

uncomplemented forms are A and B.

Thus the Boolean function + B + A +AB is minimized to .

3. Minimize the Boolean function f (A,B,C,D)= (1,3,6,7,9,13,14,15)

Solution :

Adjacent minterms are combined to form the following sub- cubes.

(1,3) (13,9) (6,7,14,15) (1,3) can be represented as D (common terms in representing 0,3) (13,9) can be represented as A D (6,7,14,15) can be represented as BC

Thus the Boolean function f (A,B,C,D) is minimized to D + A D + BC.

MINIMIZATION IN POS FORM USING KARNAUGH MAP :

1. Obtain the minimal POS expression for the switching function given below using K map . f (A,B,C,D)= (1,2,4,5,6,7,8,9,10,11,13,14)

Solution :

First form the sub-cubes by combining the adjacent max terms .(4,5,7,6) (8,9,10,11) (1,5,9,13) (2,6,14,10)

Consider (4,5,6,7) – the common terms are A+ Here the value of variable C and D changes.

( 8,9,10,11) indicates +B (1,5,9,13) indicates C + (2,6,14,10) indicates +D

Thus the minimal POS expression for the switching function is given by the product of above four sum terms as

f (A,B,C,D)= (A+ )( +B)( C + )( +D)

2.2.6 DON’T CARE COMBINATIONS:

When the variables are not mutually independent, the function may assign ‘1’ for some combinations and ‘0’ for other combinations.

The combinations for which the value of the function is not specified with certainity is called don’t care combinations.

These values are denoted by or D on K map. Example : Consider the following Boolean function together with the don’t-care minterms :

f (A,B,C) = (0,2,6)

d (A,B,C) = (4,5)

The 1’s and ’s are combined to enclose the maximum number of adjacent squares. The simplified expression is If the don’t care minterms are not included the simplified expression will be + AB

Thus the expression represents the Boolean function f (A,B,C) = (0,2,4,6)

Example : Minimize the multiple – output switching function given below, using a four- variable K map.

f(A,B,C,D)= (1,2,6,7,8,13,14,15) + (3,5,12)

Solution :

Sometimes certain designs require only some minterms to be defined and few other can be either ‘0’s or ‘1’s.

The terms represented are called unspecified states.

QUESTIONS:

1) __________ computer work as physical magnitude.a)Digital computer b) Analog computer c) Hybrid computer d) None

2) Bar code is a type of_________.a)Input device b) Output Device c) Printer d) Memory

3) LCD stands for________________a) Liquid Crystal Display b) Light Crystal Display c) Liquid Clear Display d) None

4) ________ has only one input and only one output.a) AND b) OR c) NOT d) NAND

5) In Boolean Algebra a.1=_________.1 b) a c) 0 d) None

6) Proof that (A.B)+(A+C)a) AC+AB b) AC c) C d) AB

7) ________ provide simple set of procedures for minimizing the switching functions.a) Karnaugh map b) Boolean Algebra c) DeMorgans Law d) Gates 8) In K-Map for 3 variables we need ___________Squares.

a) 16 b) 8c) 12 d) 3 9) A product term which has each of all variables as factors in either complemented or un complemented

form is called as_______________.a) Minterm b) Maxterm c) Both d) None

10) The combinations for which the value of the function is not specified with certainly called_____.a) Implicants b) Don’t care combination c) Product of Sum d) SOP

11) ________ are digital circuits because input and output have only two states.a) Gates b) K-Map c) Boolean Algebra d) Digital Computer

12) ________ called as universal Gates.a) AND, OR & NOT b) NOR &NAND c) NOT d) XOR

13) ________ called as Fundamental Gates.a) AND, OR & NOT b) NOR &NAND c) NOT d) XOR

14) ________ transmits input as serious of electronic pulse.a) Input device b) Output Device c) Printer d) Memory

15) ________ called as brain of computerCPU b) Monitor c) Printer d) Memory

UNIT III 3.1 COMBINATIONAL & SEQUENTIAL CIRCUITS

Digital logical circiuts are basically categorized into two types1. Combinational circuits2. Sequential circuits

A combinational circiuts transforms binay information from the given input data to required output data

It is represent by truth table with n inputs and m outputs. The design of combinational circuits starts from the verbal outline of the problem and ends in a

logic circuit diagram1.The procedure involves the following steps2.The problem is stated3.The input and output variables are assigned letter symbols4.The truth table that defines the relationship between inputs and outputs is derived.5.The simplified boolean functions for each output are obtained.6.The logic diagram is drawn

3.1.1 BLOCK DIAGRAM OF A COMBINATIONAL CIRCUITS

3.1.2 HALF   ADDER

A basic module used in binary arithmetic elements is the half-adder. The function of the half-adder is to add two binary digits, producing a sum according to the binary addition rules shown in the table.

INPUT SUM OF BITS

0+0 00+1 11+0 11+1 0 With a carry of 1

Addition Table

Two inputs are designated as X and Y and two outputs, designated as S and C.   The half-adder perform binary addition operation for two binary inputs as shown in table.  This is arithmetic addition, not logical or Boolean algebra addition.

 Half Adder – Block Diagram

 Truth Table

In the half-adder diagram there are two inputs to the half-adder and two outputs.  If either of the inputs is a 1 but not both, then the output on the S line will be a 1.  If both inputs are 1s, the output on the C line will be a 1.  For all other states, there be a 0 output on the carry line. These relationships may be written 

in Boolean form as follows.S = XY’ + X’Y C = XY

3.1.3  FULL   ADDER

The adder circuit is capable of adding the content of two registers. It must include provision for handling carries as well as an addend and augends bits. So there must be three inputs to each stage of a multi digit adder, except the stage for the least significant bits.  One for

each input from the numbers being added, one for any carry that might have been generated or propagated by the previous stage.

There are three inputs to the full-adder X and Y inputs from the respective digits of the

registers to be added, the Ci input, which is for any carry generated by the previous stage.   The two outputs are S, which is the output value for that stage of the addition, and C0, which produces the carry to be added into the next stage. The Boolean expressions for the input output

relationships for each of the 2 outputs are as follows:

Block diagram

Logic Diagram Truth Table

3.1.4 BINARY CODED DECIMAL ADDER

Arithmetic units which perform operations on numbers stored in BCD form must have the ability to add 4-bit representations of decimal digits.   To do this BCD adder is used.  A block diagram symbol for an adder is shown. 

BCD Adder

The adder has an augends digit input consisting of four lines, an addend digit input forfour lines, a carry- in and a carryout, and a sum digit with four output lines.  

The augend digit, addend digit and sum digit with four-output line.   The augend digit, addend digit and sum digit are each represented 8, 4, 2, 1 BCD form.   The purpose of the BCD adder in figure is to add

the augend and addend digits and the carry- in and produce a sum digit and carry out.

(i)8+7=15 1000+0111(ii) 9+5=14 1001

01011110

+0110Carry Generated 10100 = 14

3.1.5 PARALLEL BINARY ADDER

The purpose of this adder is to add two 4-bit binary integers.  The adder inputs are named X0 through X3 and the augend bits are represented

by Y0 through Y3.    A 4-bit parallel binary adder is illustrated in the figure.

Consider the additionFigure. following  Binary   binary numbers:0111 where X3=0, X2=1, X1=1 and X0=10011 where Y3=0, Y2=0, Y1=1 and Y0=1 Sum = 1010

The sum should therefore be S3=1, S2=0, S1=1 and S0=0.  The operation of the adder may be checked as follows.   Since X0 and Y0 are the least significant digits, they cannot receive a

carry from a previous stage.  In the problem above X0 and Y0 are both 1s, their sum therefore 0

and a carry is generated and added into the full-adder for bits X1 and Y1. Bits X1 and Y1 are also both 1s, as is the carry input to this stage. Therefore the sum output line S1 carries a 1 and the carry line to the next stage  also

carries a 1.   Since X2 is a 1, Y2 is a 0 and the carry input is 1.   The sum output line S2 will carry a 0, and the carry to the next stage will be a 1. Both inputs X3 and Y3 are equal to 0, and the carry input line to this adder stage is equal to 1.   Therefore, the sum output line S3 will represent a 1

and the carry output line designated as “overflow” will have a 0 output.

3.1.6 SUBTRACTOR  HALF SUBTRACTOR

A half subtractor subtracts a bit from another.   The subtraction table (or truth table) of a half subtractor is shown below.   The half subtractor has two input bits A and B two output bits, a difference DIFF = (A-

B) and a Borrow.

Truth table

Half Subtractor From the truth table shown in the table , it can be seen that DIFF = A-B and borrow

which has been implemented on the logic circuit for half subtractor.

FULL SUBTRACTOR

A full subtractor subtracts with three bits (A-B-C).  The third bit C is the borrow from previous stage.   The truth table of a full subtractor is given in table .

From the truth table of the full subtractor it can be seen that DIFF = (A B C) andborrow = A’B + BC + CA’.  This logic has been implemented.

Truth Table

  

FULL SUBTRACTOR

PARALLEL BINARY SUBTRACTOR

When a binary number is to be subtracted from another using 1’s complement method,the following circuit can be used. 

The number to be subtracted is first complemented using inverters. The complemented number is then added to the minuend using full adders.

The carry resulting from the addition is added to the least significant bit as shown in Figure.

Parallel Binary Subtractor

PARALLEL BINARY ADDER - SUBTRACTOR

For the 1’s complement system, if the storage register is composed of flip flops,the 1’s complement

can be formed by simply connecting the complement of each input to the adder.

PARALLEL ARITHMETIC EL EMENT

A complete logical circuit capable of adding or subtracting two signed 2’s complement

number is shown below.To add: Add line is made 1.To Subtract: Subtract line is made 1.

One number is represented by X1 X0 and the other number is represented by Y1Y0. 

There are two control signals. ADD and SUBTRACT. If the add control line is made a 1 then the sum

of the number X and Y will appear as S1 S0. If the subtract line is made a 1, then the difference

between X and Y will appear S1 S0. The AND to OR gate network connected to each input selects either Y or 

Y.

3.2 SEQUENTIAL CIRCUITS

Two types of circuits - Combinational circuit and Sequential circuit. Combinational circuit doesn’t has any memory elements and its

output depends only on the combined set of input applied to it simultaneously at that instant of time.

Sequential circuit must contain atleast one memory element and its output depends on both the present input and previous history of inputs.

Two types of sequential circuits – i) clocked or synchronous ii) unclocked or asynchronous

Clocked or synchronous sequential circuits:

A master oscillator provides the regular timing pulses. Events are allowed to occur during the timing pulses. Has a propagation delay. Example : Magnetic tape reader – reading takes place only when the

portion of tape to be read is under the read head.

Unclocked or asynchronous sequential circuits:

Don’t wait for the timing pulses. Event takes place or occurs after the completion of a previous event.

InputsCombinational circuit

Outputs

Inputs Sequential circuit

Outputs

Past input history or memory

Has internal logic circuit delay. Example : Telephone dial system – user dials the next number as

soon as the dialing of the previous number is completed.

3.2.1 INTRODUCTION

FLIP-FLOPS

Synchronous sequential circuits employ signals that affect the storage elements onl at a discrete instants of time.

Synchronization is achieved by a timing device called a clock pulse generator that produces a periodic train of clock pulse.

The storage element employed in clocked sequential circuits are called flip-flops.

A flip-flop is a basic memory element used to store one bit of information.

This is abbreviated as FF or F/F. It has 2 output signals, one for the normal value and one for the

complement value of the bit stored.

SR FLIP FLOP

The RS (SR) flip flop has three inputs, labeled S (for Set), R(for Reset) and C(for Clock).

It has an output Q. The complemented output is indicated with a small circle at the other

output terminal.

Graphic Symbol Characteristic Table

S R Q(t+1)

0 0 Q(t) No change

0 1 0 Clear to 0

1 0 1 Set to 1

1 1 ? Indeterminate

The arrowhead-shaped symbol in front of the letter C to designate a dynamic input.

The dynamic indicator symbol denotes that the flip-flop responds to a positive transition (from 0 to 1) of the input clock signal.

If there is no clock input C, the output of the circuit cannot change. Only when the clock signal changes from 0 to 1 the output can be

affected according to the values of S and R. S and R columns gives the binary value of the two inputs. Q(t) is the binary state of the Q output at a given time (present time). Q(t+1) is the binary state of the Q output after the occurrence of a

clock transition (next state).

3.2.2 D FLIP FLOP

The D(data) flip-flop is a modification of RS (SR) flip-flop. An SR flip-flop is converted to a D flip-flop by inserting an inverter

between S and R and assigning the symbol D to the single input.

Characteristic Table

If D = 0 and when C changes from 0 to 1, output Q is cleared to 0. If D = 1 and when C changes from 0 to 1, output Q is set to 1. The output state Q(t+1) is determined by the input D. The relationship can be expressed using the characteristic equation

Q(t+1) = D No input condition will leave the state of D flip-flop unchanged. The advantage of D flip-flop is it has only one input(excluding C).

The disadvantage of D flip-flop is it do not have “no change” condition.

Q(t+1)=Q(t) This can be done by feeding the output back to the input or by

disabling the clock.

3.2.3 JK FLIP FLOP

This is a refinement of SR flip-flop. The indeterminate state of SR flip-flop is defined in JK flip-flop. The inputs J and K are used to set and clear the flip-flop. (just like S

and R). If J = 1 and K = 1 and when C changes from 0 to 1, then a

complemented output is obtained. Q(t+1)=Q’(t)

Graphic Symbol Characteristic Table

3.2.4 T FLIP FLOP

The T (toggle) flip-flop is obtained from a JK flip-flop when inputs J and K are connected to provide a single input designated by T.

J K Q(t+1)

0 0 Q(t) No change

0 1 0 Clear to 0

1 0 1 Set to 1

1 1 Q’(t) Complement

When T =0 (J = K = 0) and when C changes from 0 to 1, there is no change in the output.

When T =1 (J = K = 1) and when C changes from 0 to 1, the complemented state of the output is obtained.

The conditions can be expressed by a characteristic equation

Graphic Symbol Characteristic Table

3.2.5 EDGE TRIGGERED FLIP-FLOP

Another type of flip-flop that synchronizes the state changes during a clock pulse transition is the edge-triggered flip-flop.

When the clock pulse input exceeds a specific threshold level, the inputs are locked out and the flip-flop is not affected by further changes in the inputs until the clock pulse returns to 0 and another pulse occurs.

Some edge-triggered flip-flops cause a transition on the positive edge of the clock pulse (positive-edge-triggered), and others on the negative edge of the pulse (negative-edge-triggered).

The logic diagram of a D-type positive-edge-triggered flip-flop is shown.

T Q(t+1)

0 Q(t) No change

1 Q’(t) Complement

D-type positive-edge triggered flip-flop

When using different types of flip-flops in the same circuit, one must ensure that all flip-flop outputs make their transitions at the same time, ie., during either the negative edge or the positive edge of the clock pulse.

3.2.6 MASTER-SLAVE FLIP-FLOP

A master-slave flip-flop is constructed from two separate flip-flops. One circuit serves as a master and the other as a slave. The logic diagram of an SR flip-flop is shown. The master flip-flop is enabled on the positive edge of the clock pulse

CP and the slave flip-flop is disabled by the inverter. The information at the external R and S inputs is transmitted to the

master flip-flop. When the pulse returns to 0, the master flip-flop is disabled and the

slave flip-flop is enabled. The slave flip-flop then goes to the same state as the master flip-flop.

Logic diagram of a master-slave flip-flop

The timing relationship is shown and is assumed that the flip-flop is in the clear state prior to the occurrence of the clock pulse.

The output state of the master-slave flip-flop occurs on the negative transition of the clock pulse.

Some master-slave flip-flops change output state on the positive transition of the clock pulse by having an additional inverter between the CP terminal and the input of the master.

Timing relationship in a master slave flip-flop

QUESTIONS:

1. __________ computer work as physical magnitude.a. a)Digital computer b) Analog computer c) Hybrid computer d)

None 2. Bar code is a type of_________.

a. a)Input device b) Output Device c) Printer d) Memory 3. LCD stands for________________

a)Liquid Crystal Display b) Light Crystal Display c) Liquid Clear Display

b. d) None 4. ________ has only one input and only one output.

a) AND b) OR c) NOT d) NAND 5. In Boolean Algebra a.1=_________.

a. 1 b) a c) 0 d) None 6. Proof that (A.B)+(A+C)

a) AC+AB b) AC c) C d) AB 7. ________ provide simple set of procedures for minimizing the switching

functions.a) Karnaugh map b) Boolean Algebra c) DeMorgans Law d)

Gates 8. In K-Map for 3 variables we need ___________Squares.

a) 16 b) 8c) 12 d) 3 9. A product term which has each of all variables as factors in either

complemented or un complemented form is called as_______________.a) Minterm b) Maxterm c) Both d) None

10. The combinations for which the value of the function is not specified with certainly called_____.

a) Implicants b) Don’t care combination c) Product of Sum d) SOP

11. ________ are digital circuits because input and output have only two states.a) Gates b) K-Map c) Boolean Algebra d) Digital Computer

12. ________ called as universal Gates.a) AND, OR & NOT b) NOR &NAND c) NOT d) XOR

13. ________ called as Fundamental Gates.a) AND, OR & NOT b) NOR &NAND c) NOT d) XOR

14. ________ transmits input as serious of electronic pulse.a) Input device b) Output Device c) Printer d) Memory

15. ________ called as brain of computera)CPU b) Monitor c) Printer d) Memory

UNIT IV

4.1 DIGITAL COMPONENTS: INTEGRATED CIRCUITS

Integrated circuit(IC) is a small silicon semiconductor crystal is called a chip

The various gates are interconnected inside the chip to form the required circuit.

Each IC has a numeric designation printed on the surface of the package for identification.

Small Scale Integration (SSI) devices contain several independent gates in a single package.

The inputs and outputs of the gates are connected directly to the pins in the package.

Medium Scale Integration (MSI) devices have a complexity of approximately 10 to 200 gates in a single package.

Large Scale Integration (LSI) devices contain between 200 and few thousand gate in a single package

Very Large Scale Integration (VLSI) devices contain thousands of gate in a single package

4.1.1 DECODERS

A decoder is a combinational circuit that converts binary information from ‘n’ input lines to a maximum of 2n unique output lines.

It is used to decode the binary information to some other number system (decimal or hexadecimal).

A 2 to 4 line Decoder

Inputs Outputs

A B C D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

Truth Table for 3 to 8 line decoder

Here, a 3 bit binary information is decoded into eight outputs. The three NOT gates or invertors on the input side give the

complement of the inputs. The eight AND gates are used to active the outputs ‘High’. It is also called as binary to octal decoder. The applications of decoder is binary to octal conversion. It is also used to display the letters of the alphabet. Light Emitting Diodes (LEDs) are used as light source for the

read-out display.

4.1.2 ENCODERS

It is just reverse process of decoding. This changes decimal signals into equivalent binary signals. It is also called as coder. It has 2n or less input lines and n output lines. The octal to binary encoder has 8 inputs and three outputs. It is constructed using three OR gates.

Octal to binary encoder

Inputs Outputs

D7 D6 D5 D4 D3 D2 D1 D0 A B C

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

Truth Table for Octal to binary encoder

Decimal to BCD encoder can be constructed using four OR gates. This encoder has 10 input lines and four output lines. The switches S0 to S9 are push buttons. When push-button S2 corresponding to decimal number 2 is pressed,

the OR gate for output B has a high input, therefore the output BCD word is given by

o D C B A = 0 0 1 0.

Decimal to BCD encoder

4.1.3 MULTIPLEXERS

It is also known as data selector and abbreviated as MUX.

It is a combinational logic circuit. It accepts several data inputs and selects only one at a time and

directs it to a single output line.

4-to-1 line Multiplexer

In 4 –to-1 line multiplexer, there are four inputs I0, I1 , I2 and I3 which is applied to one input of an AND gate.

The two select inputs S1 and S2 are decoded to select a particular AND gate.

The outputs of the AND gates are applied to the single OR gate to provide the single output.

When S1 S0 = 11, the AND gate associated with I3 has two of its input equal to 1. The third input is connected to I3 . The other three AND gates have atleast one input equal to zero. So the OR gate output is now equal to the value of I3, thus providing a path from select input to output.

The size of the multiplexer is given by 2n to 1 line, where 2n stands for the number of the input lines and n stands for the number of select inputs.

4.1.4 DEMULTIPLEXERS

It is also known as data distributor and abbreviated as DEMUX. It does the reverse process of the multiplexer. It takes in single input and distributes several outputs. It receives single line information and transmits it to one of 2n

possible output lines. The select input will determine or decide to which output the data

input will be transmitted.

DEMULTIPLEXERS

There is a single input line I which is connected to all the AND gates. Three select inputs are used , so n=3. There must be 2n output lines (23=8). The select inputs enable one of the eight AND gates. Demultiplexers are useful when information from one source is to be

fed to several places.

Inputs Outputs

Data Input

Select Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

S2 S1 S0

I 0 0 0 0 0 0 0 0 0 0 I

I 0 0 1 0 0 0 0 0 0 I 0

I 0 1 0 0 0 0 0 0 I 0 0

I 0 1 1 0 0 0 0 I 0 0 0

I 1 0 0 0 0 0 I 0 0 0 0

I 1 0 1 0 0 I 0 0 0 0 0

I 1 1 0 0 I 0 0 0 0 0 0

I 1 1 1 I 0 0 0 0 0 0 0

Truth Table for 1 to 8 line Demultiplexer

4.2 REGISTERS

Register is a group of cascaded flip-flops for storing binary information momentarily.

They are used in microprocessors and digital computers. They are used for transfer of binary information and for storage

of binary data which is being decoded in digital systems.4.2.1 SHIFT REGISTERS

Shift register is a register, which is used to assemble and store the information arriving from a serial source.

A shift register can shift binary word either to the left or to the right.

It consists of cascaded flip-flops, with the output of each flip-flop connected to the input of the next flip-flop.

A common clock pulse is applied to all the flip-flops, clocking them synchronously and causing the shift from one stage to the next stage.

The shift register is a synchronous sequential circuit. When a shift register is used to move the stored bits to the left, it

is called shift-left register.

When a shift register is used to move the stored bits to the right, it is called shift-right register.

SHIFT-LEFT REGISTER

Shift-left register using D flip-flop

In shift-left register,the data input Din is applied to flip flop A. A common edge triggered clock pulse is applied to all the four flip flops. The data input Din sets up the first flip-flop A, whose output Q0 sets the

second flip-flop, whose output Q1 sets the third flip-flop C and so on. On arrival of the next positive clock edge, the stored bits move one

position to the left. Initially Q = D C B A = 0 0 0 0 and Din = 1 The first rising clock edge will set the right flip-flop A and stored word

becomes Q = D C B A = 0 0 0 1 Now the input to the D1 to the flip-flop B is equal to ‘1’. On arrival of the

next positive clock edge, flip-flop B sets and the contents of the register becomes Q = D C B A = 0 0 1 1

The third positive clock edge gives the output Q = D C B A = 0 1 1 1

Shift-left register using JK flip-flop

The data input X is connected to J input and obtained after inversion is connected to K input.

The clock pulse is applied at the T inputs of all the flip-flops simultaneously.

When the first clock pulse arrives, the data inputs X and are shifted to the output of the flip-flop A.

Thus on arrivals of each clock pulse, the data are shifted to the output of the next flip-flop.

SHIFT-RIGHT REGISTER

Shift-right register using D flip-flop

The connection is similar to shift-left register with only difference that the data input is connected to D flip-flop and output is taken from A flip-flop.

A common edge triggered clock pulse is applied to all the four flip flops. The output Q3 of flip-flop D, sets the input for the prededing flip-flop C. When the positive clock edge arrives, the stored bit move one position to

the right. Initially Q = D C B A = 0 0 0 0 and Din = 1 The first rising clock edge will set the left flip-flop D and stored word

becomes Q = D C B A = 1 0 0 0. The second positive clock edge gives the output Q = D C B A = 1 1 0 0 The third positive clock edge gives the output Q = D C B A = 1 1 1 0 The fourth positive clock edge gives the output Q = D C B A = 1 1 1 1 The word is stored and remains unchanged till Din = ‘1’.

Shift-right register using JK flip-flop

The data input X is connected to J input and obtained after inversion is connected to K input.

The clock pulse is applied at the T inputs of all the flip-flops simultaneously.

When the first clock pulse arrives, the data inputs X and are shifted to the output of the flip-flop D.

Thus on arrival of each clock pulse, the data are shifted to the output of the next flip-flop.

Four types of shift registers are1. Serial in serial out shift registers2. Parallel in serial out shift registers

3. Serial in parallel out shift registers4. Parallel in parallel out shift registers5. Parallel in parallel out bi-directional shift registers

4.3 COUNTERS

The counter has the ability to count. It is an important and useful subsystem of a digital system. A counter is a group of cascaded flip-flops to store more binary

information. A counter is a register, which is capable of counting the number of

clock pulses, which has arrived at its clock input. It is used in control systems, computers, electronic and scientific

instruments. The application of counters includes counting the occurrence of

events, frequency division, time sequence of operation of equipments and digital systems.

Two types of counters are i) asynchronous or ripple counter

ii) synchronous counter.

ASYNCHRONOUS COUNTER It is an asynchronous sequential circuit. All the flip-flops in an asynchronous counter are not under the

control of same clock pulse. An n-bit binary ripple counter can count upto a maximum of 2n states. A ripple counter is a basic and simple counter. It has limitation on speed of operation.

3 bit binary ripple counter

In 3 bit binary ripple counter, three JK flip-flops are connected in cascade.

It can count upto 23 states i.e 8 states. Initially all the four flip-flops A,B and C are in logic ‘0’ state. A clock pulse is applied to flip-flop A only, which makes QA to

change from logic 0 to logic 1 state. Other flip-flops B and C do not change their state. After the application of the clock pulse to the clock input, the counter reads.

Q = QC QB QA = 0 0 1 When second clock pulse is applied to flip-flop A, output QA changes

state from logic 1 to logic 0. Due to this state change, a negative going pulse created at QA , which is connected to clock input of the flip-flop B. This pulse triggers the flip-flop B and changes the state of QB from 0 to 1. Flip flop C do not change its state. Now the counter reads

Q = QC QB QA = 0 1 0 The counter will continue to count the input clock pulses in the

binary form upto the state till QC , QB and QA all become high. That is the counter reads Q = QC QB QA = 1 1 1, which in decimal means that it will count upto 7 clock pulses.

On the arrival of the 8th clock pulse, all the three flip-flops will go to ‘0’ and the counter will once again repeat its counting from 000 to 111 (from 0 to 7).

SYNCHRONOUS COUNTER It is an synchronous sequential circuit. All the flip-flops in an asynchronous counter are under the control of

same clock pulse. It is used to eliminate the cumulative flip-flop delays. Two methods are used to control the flip-flop in synchronous counter.

one with ripple carry one with parallel carry All the flip-flops in synchronous counter change their state

simultaneously and thus They are capable of operating at higher frequencies and speed.

They are more complicated and require more components.

(i) Four-bit synchronous counter with serial or ripple carry

Four-bit synchronous counter used positive edge triggered JK flip-flop with serial or ripple carry.

It requires two input logic gates. On the arrival of clock pulse, all the flip-flops changes their state

simultaneously. Inputs of flip-flops are

JA = KA = 1JB = KB = QA

JC = KC = QA * QB

JD = KD = QB * QC

(ii) Four-bit synchronous counters with parallel carry or look-ahead carry

Here, the state of the flip-flop is fed parallel to all succeeding flip-flops.

The input clock pulse drive all the flip-flops in parallel. The flip-flop A has its J-K inputs to a high voltage level ‘1’ and it

responds to each positive clock pulse. The remaining flip-flops respond to the next positive clock edge only

if all the lower bits are ‘1’s. Inputs of flip-flops are

JA = KA = 1JB = KB = QA

JC = KC = QA * QB

JD = KD = QA *QB * QC

4.4 MEMORY UNIT

Memory stores such binary information as instructions and data, and provides thatinformation to the microprocessor whenever necessary.

To execute programs the microprocessor reads instructions and data from memory and

performs the computing operations in its ALU section. Results are either transferred to the output section for displayer stored in

memory forlater use. The memory block has two sections

Read only memory (ROM) Read/Write memory (R/WM), popularly known as Random- Access

memory (RAM). The ROM is used to store programs that do not need alterations. The mon

itor program ofa single board microcomputer is generally stored in the ROM.

This program interprets the information entered through a keyboard and provides equivalent binary digits of the microprocessor.

MAIN MEMORY

The main memory is the central storage unit in a computer system. It is a relatively large

and fast memory used to store programs and data during the computer operation.

The principal technology used for the main memory is based on semiconductor integrated circuits.

Integrated circuit RAM chips are available in two possible operating modes, static and dynamic.

The static RAM consists essentially of internal flip- flops that store the binary information.

The stored information remains valid as long as power is applied to the unit.

The dynamic RAM stores the binary information in the form of electric charges that are applied to capacitors.

The capacitors are provided inside the chip by MOS transistors.

The stored charges on the capacitors tend todischarge with time and the capacitors

must be periodically recharged by refreshing the dynamic memory. Refreshing is done by

cycling through the words every few milliseconds to restore the decaying charge.

The dynamic RAM offers reduced power consumption and larger storage capacity in a single memory chip.it is necessary to combine a number of chips to form the required memory size.

To demonstrate the chip interconnection, we will show an example of a 1024 * 8 memory constructed with 128 * 8 RAM chips and 512 * 8 ROM chips.

QUESTIONS:

1) _____________ is a small silicon semiconductor crystal containing electronic components for digital gates. a) Integrated Code b) Interface circuit c) Internal circuit d) Integrated circuit 2) _____________devices contain between 200 and a few thousand gates in a single package. a) VLSI b) LSI c) SI d) MSI 3) _____________ is a combinational circuit that converts binary information from n coded inputs to maximum of 2 n unique outputs. a) Decoder b) Encoder c) Counter d) Register 4) _____________has 2 n input lines & n output lines. a) Decoder b) Encoder c) Counter d) Register 5) _____is a combinational circuit that receives binary information from one of 2 n input lines & directs to a single output line . a) Encoder b) Decoder c) Multiplexer d) Demultiplexer 6) Multiplexer is also called as __________ a) Data pin b) Data selector c) Database d) none 7) The transfer of new information into a register is referred to as __________. a) Load register b) Create register c) Allocate register d) none 8) A counter that follows the binary number sequence is called as __________ a) Unary b) Binary c) Serial d) Unidirectional 9) The memory stores binary information in groups of bits called__________. a) Byte b) Pair c) Quad d) Word 10) A group of ________ bits called a byte a) 4 b) 2 c) 8 d) 16 11) _____________ is a permanent memory. a) RAM b) ROM c) Cache d) none 12) Flash memory is a form of_______________ a) PROM b) EPROM c) EEPROM d) ROM 13) _________ is a collection of storage cells together which associated circuits needed for transfer information in & out of storage. a) Memory unit b) Control unit c) ALU d) Processor 14) A register that can shift in both directions is called ________. a) Unidirectional b) Bidirectional c) Semi directional d) None 15) CMOS stands for____________ a) Common metal oxide semiconductor b) Complementary metal oxide semiconductor

c) Computer metal oxide semiconductor d) Common memory oxide system

UNIT V

5.1 INPUT-OUTPUT ORGANIZATION

PERIPHERAL DEVICES

A microprocessor is a multipurpose, programmable logic device that reads binaryinstructions from a storage device called memory accepts binary data as input and processes dataaccording to those instructions and provides results as output.

A typical programmable machine can be represented with three components: microprocessor, memory and I/O as shown

I/O

A Programmable devices

Microprocessor, memory and I/O Components are work together or interact with each otherto perform a given task; thus they compromise a system.

The physical components of this system are called hardware. A set of instructions written for the microprocessor to perform a ta

sk is called a program. A group pf programs is called software. The machine (system) represented in figure can be

programmed to turn traffic lights on and off,

MICROPROCESSOR

Memory

compute mathematical functions or keep track of a guidance system.

The microprocessor applications are classified primarily in two categories:

1. Reprogrammable systems2. Embedded systems

Reprogrammable Systems In reprogrammable systems, such as microcomputers, the micropr

ocessor is used for computing and data processing. These systems include general – purpose microprocessors capable

of handling large data, mass storage devices and peripherals.

Embedded Systems In embedded systems, the microprocessor is a part of a final produ

ct and is available for reprogramming to the end user. A copying machine is a typical example of an embedded system.

BINARY DIGITS The microprocessor operates in binary digits 0 and 1, also known a

s bits. Bit is an abbreviation for term binary digit. These digits are represented in terms of electrical voltages in

the machine 0 represents low voltage level and 1 represents high voltage level.

A MICROPROCESSOR AS A PROGRAMMABLE DEVICE The microprocessor is programmable that can be instructed to perf

orm given tasks within its capacity. The engineers designing a microprocessor determine a set of t

asks the microprocessor should perform and design the necessary logic circuits and provide the user with

a list of instructions the processor will understand. For example, an instruction for adding two numbers may look like

a group of eight binary digits such as 1000 0000.

These instructions are simply a pattern of 0s and 1s. The user

(programmer) selects instructions from the list and determines the sequence of execution for a

given task. These instructions are entered or stored in storage, called memory,

which can be read by the microprocessor.

MEMORY

Memory is like the pages of a notebook with space for a fixed number of binary numbers

on each line. However, these pages are generally made of semiconductor materi

al. Typically, each line is an 8-

bit register that can store 8 binary bits, and several of these registers are

arranged in a sequence called memory. These registers are always grouped together in powers of two.

INPUT/OUTPUT

The user can enter instructions and data into memory through devices such as keyboardor simple switches.

These devices are called input devices. The microprocessor reads the

instruction from the memory and processes the data according to those instructions.

The results can be displayed by a device such as seven segment LEDS or printed by a printer.

These devices are called output devices.

MICROPROCESSOR AS A CPU

We can also view the microprocessor as a primary component of a

computer.

The CPU

is the primary and central player in communicating with devices s

uch as

memory, input and output.

The timing of the communicating process is controlled by the grou

p of circuits called thecontrol unit.

The CPU contains various registers to store data. The arithmetic logic unit (ALU)

to perform arithmetic and logical operations, instruction decoders, counters and control lines.

The CPU reads instruction from memory and performs the task specified.

It communicates with input/output devices either to accept or to send data.

With the advent of the integrated circuit technology it became possible to built the CPU on a single chip; this came to be known as microprocessor.

ORGANIZATION OF A MICROPROCESSOR-BASED SYSTEM

MICROPROCESSOR

I/OALUREGISTER

ARRAYCONTROL

INPUT/OUTPUT

SYSTEM BUS

MEMORYRO

M R/WM

Microprocessor-Based Systems with Bus Architecture

MICROPROCESSOR

The microprocessor is a semiconductor device consisting of electronic logic circuits

manufactured by using either a large-scale integration (LSI) or very- large-scale integration

(VCLSI) technique. The microprocessor is capable of performing various computing f

unctions and making decisions to change the sequence of program execution,

in large computers, a CPU implemented on one or more circuit boards performs

these computing functions. The microprocessor is in many ways similar to the CPU.

The microprocessor can be divided into three segments for the sake clarity.

Arithmetic/logic unit (ALU)

Register array Control unit.

Arithmetic/Logic Unit

This is the area of the microprocessor where various computing functions are performed

on data. The ALU unit performs arithmetic operations as addition and subt

raction, and such logic operations as AND, OR and exclusive OR. Results are stored either in register or in memory.

Register Array This area of the microprocessor consists of various registers. Thes

e registers are primarilyused to store data temporarily during his execution of a program. 

Some of the registers are accessible to the user through instructions.

Control Unit The control unit provides the necessary timing and control signals 

to all the operations inthe microcomputers. 

It controls the flow of data between the microprocessor and memory and peripherals.

5.1.1 INPUT – OUTPUT INTERFACE

This provides a method for transferring information between internal storage and external I/O devices.

Communication links are used to interface between peripherals and CPU. They resolve the differences between computer and peripheral.

The differences are

Peripherals are electromechanical and electromagnetic devices where CPU and memory are electronic devices.

Data transfer rate of peripherals are slower than transfer rate of CPU. So synchronization is necessary.

Data codes and formats in peripherals are differ from word format in CPU and memory.

Operating modes of peripherals are different from each other and it should be controlled so that it will not disturb operations of other peripherals.

To resolve these differences, a special hardware component is included in computer system between CPU and peripherals to supervise and synchronize all input and output transfers. This component are called interface units.

5.1.2 I/O BUS AND INTERFACE MODULES The I/O bus consists of data lines, address lines and control lines. Each peripheral devices are associated with its interface units. Each peripheral has its own controller.

Connection of I/O bus to input-output devices The interface Decodes the address and control received from the

I/O bus Interprets it and provides signal for peripheral controller Synchronize the data flow and supervises the transfer between

CPU and peripherals. The I/O bus from the processor is attached to all the peripheral

devices. To communicate with a particular device, Processor will place a device address on the address line. The address decoder in the interface, monitors the address line. When the interface detects its own address, it activates the path

between the bus line and the device. Other interfaces will disable their path. Processor will place a function code in the control lines. The interface selected responds to the function code and executes

it. The function code is called as I/O command.

Four types of I/O Commands :-

1. Control Command : Activates the peripheral and inform it what to

do. This depends on the peripheral and each of it receives its own

distinguished sequence of control commands based on its mode of

operation.

2. Status Command: Test various status conditions in the interface

and the peripherals. During transfer, errors may occur which are

detected by the interface. These errors are designated by setting

bits in status register which is read by the processor at certain

intervals.

3. Data Output Command: Makes the interface to respond by

transferring data from the bus into one of its register. The

processor issues data output command. The interface responds to

the address and command and transfers the information from the

data lines in the bus to its buffer register. The interface then

communicates with the peripheral devices and sends the data to it.

4. Data Input Command: This is opposite to data output command.

The interface receives an item of data from the peripheral device

and places it in its buffer register. The processor checks if data are

available by means of a status command and issues a data input

command. The interface places the data on the data lines for the

processor.

5.1.3 I/O VERSUS MEMORY BUS

Memory bus is used for communication between processor and

the memory unit.

It contains data, address and read/write control lines.

Three ways that computer bus can be used to communicate with memory and I/O :

Use two separate buses – one for memory and other for I/O.

Use one common bus for both memory and I/O but have

separate control lines for each.

Use one common bus for memory and I/O with common control

lines.

In the first method, the computer has independent sets of data,

address and control buses, one for accessing memory and the

other for I/O. This is done in computers that provide a separate

I/O processor (IOP) in addition to the CPU.

The purpose of IOP is to provide an independent pathway for

the transfer of information between external devices and internal

memory. The I/O processor is sometimes called a data channel.

5.1.4 ISOLATED VERSUS MEMORY-MAPPED I/O

Many computers use one common bus to transfer information

between memory or I/O and the CPU.The CPU specifies whether

the address on the address lines is for a memory word or for an

interface register by enabling one of two possible read or write

lines.

The I/O read and I/O write control lines are enabled during an I/O

transfer.The memory read and memory write control lines are

enables during memory transfer.

This configuration isolates all I/O interface addresses from the

memory addresses and referred as isolated I/O method for

assigning addresses in a common bus.

Certain computers employ only one set of read and write signals

and do not distinguish between memory and I/O addresses.

This configuaration is referred to as memory-mapped I/O.

There are no specific inputs or output instructions. The CPU can

manipulate I/O data residing in interface registers with the same

instruction that are used to manipulate memory words.

Computer with memory-mapped I/O uses memory-type

instructions to access I/O data.

It allows computer to use the same instruction for either I/O

transfer or memory transfer.

The advantage is that the load and store instructions used for

reading and writing from memory and can be used to input and

output data from I/O registers.

5.1.5 EXAMPLE OF I/O INTERFACE

It consists of

1. Two data registers called ports - The I/O data to and from the

device can be transferred into either port A or port B.

2. A Control register – receives control information from CPU. By

loading appropriate bits into control register, the interface and

the I/O device attached to it can be placed in a variety of

operating modes.

3. A Status register – The bits in status register are used for

status conditions and for recording errors that may occur during

the data transfer.

4. Bus buffers

5. Timing and control circuits

The interface communicates with the CPU through the data bus.

The Chip select and register select inputs determine the address

assigned to the interface

The I/O read and write are two control lines that specify an input

or output respectively.

The four registers communicate directly with the I/O device

attached to the interface.

The interface operates with an output device or with an input

device.

A circuit is provided to detect the address assigned to the

interface registers.

This circuit enables the chip select (CS) input when the interface

is selected by the address bus.

The two register select inputs RS1 and RS2 are connected to two

least significant lines of the address bus.

These two inputs select one of the four registers in the interface.

The data transfer between the selected registers and CPU is done

via data bus when an I/O read or write signal is enabled.

Example of I/O Interface units

5.1.6 ASYNCHRONOUS DATA TRANSFER

The internal operations in a digital system are synchronized by means of clock pulses supplied by a common pulse generator. Clock pulses are applied to all registers within a unit and all data transfers among internal registers occur simultaneously during the occurrence of a clock pulse. Two units, such as a CPU and an I/O interface, are designed independently of each other. If the registers in the interface share a common clock with the CPU registers, the transfer between the two units is said to be synchronous. In most cases, the internal timing in each unit is independent from the other in that each uses its own private clock for internal registers. In that case, the two units are said to be asynchronous to each other. Asynchronous data transfer between two independent units requires that control signals be transmitted between the communicating units to indicate the time at which data is being transmitted. One way of achieving this is by means of a strobe pulse supplied by one of the units to indicate to the other unit when the transfer has to occur. Another method commonly used is to accompany each data item being transferred with a control signal that indicates the presence of data in the bus. The unit receiving the data item responds with another control signal to acknowledge receipt of the data. This type of agreement between two independent units is referred to as handshaking. We have to specify the asynchronous transfer between two independent units by means of a timing diagram that shows the timing relationship that must exist between the control signals and the data in the buses. The sequence of control during an asynchronous transfer depends on whether the transfer is initiated by the source (transmitting) unit or by the destination (receiving) unit.

5.1.7 STROBE CONTROL

A Strobe Control employs a single control line to time each transfer

The strobe may be activated by either the source or the destination

unit

Block Diagram

Timing Diagram

Source-Initiated Strobe for Data Transfer

The data bus carries the binary information from source to destination.

The strobe is a single line that informs the destination unit when a valid data word is available in the bus.

The source unit places data on the bus and after a short delay, it activates the strobe pulse.

The information on the data bus and strobe signal remain active to allow destination unit to receive the data.

The source removes data from the bus a brief period after it disables its strobe pulse.

Once the strobe pulse is disabled , the data bus does not contain valid data.

Block Diagram

Timing Diagram

Destination-Initiated Strobe for Data Transfer

Here the destination unit initiated the data transfer and it activates the strobe pulse, informing source unit to provide data.

Now the source unit places the information in data bus. The falling edge of the strobe pulse is used to trigger the destination

register. Then the destination unit disables the strobe and the source removes the

data after a predefined time interval.

5.1.8 HANDSHAKING

DISADVANTAGES OF STROBE CONTROL

a. The source unit that initiates the transfer has no way of knowing whether the destination unit has actually received data

b. The destination unit that initiates the transfer no way of knowing whether the source has actually placed the data on the bus

To solve this problem, the HANDSHAKE method introduces a second control signal to provide a Replay to the unit that initiates the transfer

One control line from source to destination is used by the source unit to inform the destination unit whether the valid data in the bus.

Another control line from destination to source is used by the destination unit to inform the source unit whether it can accept data.

Source-Initiated transfer using Handshaking

(a) Block Diagram

(b) Timing Diagram

(c) Sequence of Events

Two handshaking lines are

Data valid : generated by the source unit

Data accepted : generated by the destination unit

The timing diagram shows the exchange of signals between

the two units.

The sequence of events shows four possible states in the

system.

The source unit initiates the transfer by placing the data on the

bus and enables its data valid signal.

The data accepted signal is activated by the destination unit

after it accepts the data.

The source unit then disables its data valid signal which

invalidates the data on the bus.

The destination unit disables its data accepted signal and the

system goes to initial state.

Destination-Initiated transfer using Handshaking

(a) Block Diagram

(b) Timing Diagram

(c) Sequence of Events

The signal generated by the destination unit is “ready for data”. The source unit does not place any data on the bus until it

receives the ready for data signal from the destination. The only difference between source-initiated and destination-

initiated transfer is in their choice of initial state.Timeout mechanism

Handshaking scheme provides high degree of flexibility and reliability.

If one unit is faulty, the data transfer is not completed which can be detected by means of timeout mechanism – this produces an alarm if the data transfer is not completed within in a predetermined time.

This is implemented by means of an internal clock that starts counting time when the unit enables one of its handshaking control signal. If there is no response within a predetermined time then the unit assumes there is an error and produces an alarms.

PRIORITY INTERRUPT

A priority interrupt establishes a priority to decide which condition is to be serviced first when two or more requests arrive simultaneously.

The system determines which conditions are permitted to interrupt the computer while another interrupt is being serviced.

Higher-priority interrupt levels are assigned to requests, which if delayed or interrupted, could have serious consequences.

Devices with high- speed transfers are given high priority, and slow devices receive low priority.

Establishing the priority of simultaneous interrupts can be done by software or hardware.

A polling procedure is used to identify the highest-priority.  There is one common branch address for all interrupts. The program that takes care of interrupts begins at the branch

address and polls the interrupt sources in sequence.  The order in which they are tested determines the priority of each

interrupt. The highest-priority source is tested first and if its interrupt signal

is on, then control branches to a service routine for this source. Otherwise, the next-lower-priority source is tested, and so on.

Thus the initial service routine interrupts consists of a program that tests the interrupt sources in sequence and branches to one of many possible service routines. 

Disadvantage of software method: If there are many interrupts, the time required to poll them exceeds the time available to service the I/O device. So to speed up the operation, a hardware priority-interrupt is used.

A hardware priority-interrupt unit functions as an overall manager in an interrupt system environment.

It accepts interrupt request from many sources and determines which has the highest priority and then issues an interrupt request to the computer based on the determination.

No polling is required because all decisions are established by the hardware priority-interrupt unit.

The hardware priority function can be established by either a serial or a parallel connection of interrupt lines.

Daisy-Chaining Priority

The daisy-chaining method has a serial connection of all devices that request an interrupt.

The device with the highest priority is kept in the first position, followed by lower-priority devices and so on.

The interrupt request line is common to all devices.

Daisy-Chain Priority Interrupt

If any device has its interrupt signal in the low-level state, the interrupt line goes to the low-level state and enables the interrupt input in the CPU.

When no interrupts are pending, the interrupt line stays in the high-level state and CPU does not recognize any interrupt. This is equivalent to a negative logic OR operation.

The CPU responds to an interrupt request by enabling the interrupt acknowledge line.

This signal is received by device 1 at its PI (priority in) input. The acknowledge signal passes on to the next device through the PO (priority out) output only if device 1 is not requesting an interrupt.

If device I has a pending interrupt, it blocks the acknowledge signal from the next device by placing a 0 in the PO output. It then proceeds to insert its own interrupt vector address (VAD) into the data bus for the CPU to use during the interrupt cycle.

A device with PI=0 input generates a 0 in its PO output to inform the next-lower-priority device that the acknowledge signal has been blocked.

A device that makes a request for an interrupt and has a I in its Pi input will intercept the acknowledge signal by placing a 0 in its PO output. If the device does not have pending interrupts, it transmits the acknowledge signal to the next device by placing a 1 in its PO output. Thus the devicewith PI = 1 and PO = 0 is the one with the highest priority that is requesting ani nterrupt, and this device places its VAD on the data bus.

The daisy chain arrangement gives the highest priority to the device that receives the interrupt acknowledge signal from the CPU.

The internal logic as shown in the figure must be included within each device when connected in the daisy-chaining scheme.

One stage of the daisy chain priority arrangements

The device sets its RF flip-flop when it wants to interrupt the CPU. The output of the RF flip-flop goes through an open-collector inverter (a circuit that provides the wired logic for the common interrupt line).

If PI = 0,both PO and the enable line to VAD are equal to 0, irrespective of the value of RF.

If PI =1 and RF= 0, then PO = 1 and the vector address is disabled. This condition passes the acknowledge signal to the next device through PO. The device is active when PI = 1 and RF = 1. This condition places a 0 in PO and enables the vector address for the data bus.

It is assumed that each device has its own distinct vector address. The RF flip-flop is reset after a sufficient delay to ensure that the

CPU has received the vector addressParallel Priority Interrupt

The method uses a register whose bits are set separately by the interrupt signal from each device.

Establish the priority according to the position of the bits in the register.

A circuit may include a mask register to control the status of each interrupt request.

The mask register is programmed to disable lower-priority interrupts while a higher-priority device is

being serviced. It can also provide a facility that allows a high-priority device to

interrupt while a lower-priority device is being serviced.

Priority Interrupt Hardware

The above figure is the priority logic for a system of four interrupt sources.

It has an interrupt register. The bits of this register are external conditions and cleared by program instructions.

The magnetic disk is given the highest priority. The printer has the next priority, followed by a character reader and a keyboard.

The mask register has the same number of bits as the interrupt register.

Using program instructions, we can set or reset any bit in the mask register.

Each interrupt bit and its corresponding mask bit are applied to an AND gate to produce the four inputs to a priority encoder.

An interrupt is recognized only if its corresponding mask bit is set to 1 by the program.

The priority encoder generates two bits of the vector address, which is transferred to the CPU.

Another output from the encoder sets an interrupt status flip-flop IST when an interrupt that is not masked occurs.

The interrupt enable flip-flop IEN can be set or cleared by the program to provide an overall control over the interrupt system.

The outputs of 1ST AND with IEN provide a common interrupt signal for the CPU.

The interrupt acknowledge INTACK signal form the CPU enables the bus buffers in the output register and a vector address VAD is placed into the data bus.

Priority Encoder

Circuit that implements the priority function. Logic – if two or more inputs arrive at the same time, the input

having the highest priority will take precedence.

Boolean functions

X = I’0I’1 Y = I’0I1 + I’0I’2 IST = I0 + I1 + I2 + I3

Interrupt Cycle

The Interrupt enable flip-flop (IEN) can be set or cleared by program instructions.

A programmer can therefore allow interrupts (clear IEN) or disallow interrupts (set IEN)

At the end of each instruction cycle the CPU checks IEN and IST. If either is equal to zero, control continues with the next instruction. If both = 1, the interrupt is handled.

Interrupt micro-operations:SPßSP – 1 (Decrement stack pointer)M[SP] ß PC Push PC onto stack

INTACK ß 1 Enable interrupt acknowledgePC ßVAD Transfer vector address to PCIEN ß0 Disable further interruptsGo to fetch next instruction

Software Routines for handling Interrupts

Software routines used to service interrupt requests .Each device has its own service program reached through a jump instruction stored at the assigned vector address.

Example: Keyboard sets interrupt bit while CPU is executing

instruction at location 749. At the end of the instruction, 750 is

pushed onto the stack, the VAD for the keyboard is taken off the bus

and placed into the PC. Control is passed to the keyboard routine.

Once completed, PC is replaced with original address of next

instruction (750)

Initial and Final Operations

The initial sequence of each interrupt service routine must have

instructions to control the interrupt hardware in the following manner :

Clear lower-level mask register bits Clear interrupt status bit IST Save contents of Processor registers Set interrupt enable bit IEN Proceed with service routine

The final sequence of each interrupt service routine must have

instructions to control the interrupt hardware in the following manner:

Clear interrupt enable bit IEN Restore contents of Processor registers

Clear the bit in the interrupt register belonging to the source that has been serviced.

Set lower priority bits in the mask register Restore return addresses into PC and set IEN

These initial and final operations are referred as overhead operations

or housekeeping chores.

Questions:

1) _____________ devices attached to computer are also called peripherals.

a) Input Device b) Output Device c) I/O Device d) None

2) _____________is a special hardware component between the CPU & peripherals

a) Interface Unit b) Memory Unit c) Bus d) Control Unit

3) _____________is used to activate the peripheral & to inform it what to do.

a) Status command b) I/O command c) Control command d) None

4) _____________is used to test various status conditions in the interface & the

peripheral.

a) Status command b) I/O command c) Control command d) None

5) _____data transfer clock pulses supplied by a common pulse generator.

a) Asynchronous b) Synchronous c) Both d) None

6) __________ indicate the time at which data is being transmitted.

a) Clock b) Handshaking c) Strobe d) Peripherals

7) Strobe control is the example for __________.

a) Asynchronous b) Synchronous c) Both d) None

8) Data valid generated by __________ unit.

a) Destination Unit b) Source Unit c) Data Unit d) Memory Unit

9) ASCII uses__________ bits.

a) 8 b) 9 c) 2 d) 7

10) ________ used for bulk storage

a) CD b) Magnetic Disk c) Magnetic Tape d) Floppy Disk

11) CRT stands for__________

a) Code Ray Tube b) Cathode Ray Tube c) Cache RAM Transfer d) none

12) ASCII allows_______________

a) % b) * c) $ d) All of these

13) _________ used for routing data and arranging the printed text into prescribed

format.

a) Clock Control b) Control unit c) Control Character d) Printer

14) ________transfer the data from bus into register.

a) Data O/P Command b) Data I/P Command c) Signals d) None

15) Agreement between 2 independent units is referred to as __________

a) Clock b) Handshaking c) Strobe d) Peripherals

Possible Questions:

SECTION-B

1. Explain about Half adder with neat diagram.

2. Explain about D flip flop.

3. Difference between Sequential circuit and Combinational circuit.

4. Explain about Edge Triggered flip flop.

5. Discuss about Encoders in detail.

6. Write in short about the De multiplexer.

7. Explain about shift registers.

8. Discuss about the memory unit.

9. Write about the Conversion Process of Decimal to Binary with Examples

10. Write Short notes on Gray code representation.

11. Simplify the following Boolean functions using K-Map.

a. F(A,B,C,D)=∑(0,1,2,4,5,7,11,15)

12. Discuss about Digital computers with the neat diagram.

13. Explain the operation of Half Adder with logic diagram, truth table and

a. Boolean Functions

14. Draw & Explain the circuit of T-Flip-flop

15. What is a Multiplexer? Draw Explain the circuit diagram of 4 of 1 line

a. Multiplexer

16. Explain about Binary counters.

17. Explain the source-imitated strobe for data transfer

18. Explain about I/O versus Memory Bus.

19. Write short note on sequential circuits.

20. Write about radix numbers.

21. Explain about ASCII Number system

22. Explain about BCD numbers.

23. Explain Excess – 3 code with an example

24. Explain about Minterm.

25. Explain about Don’t care combination

26. Explain about XOR and X NOR gates.

27. Write short note on Boolean algebra.

28. Write about EBCIDIC code with an example.

29. Explain about basic identities

30. Explain about Demorgans theorem

31. Write short note on combinational circuits.

32. Convert 10111011 to 2s complement

33. Convert 1996 to binary number.

34. Explain about the types of ROM.

35. Explain about the universal gates.

SECTION-C 1. Draw and explain the circuit diagram of full adder with truth table 2. Explain in detail about parallel binary adder

3. Explain in detail about parallel binary subtractor.

4. What is Multiplexer? Draw and explain the circuit diagram of 4 of 1 line

multiplexer.

5. Explain about general register organization.

6. Explain about Binary counters in detail

7. Write in detail about RAM .

8. Discuss the number system with examples

9. Perform the subtraction using 2’s complement & 1’s complement. Check

the answer by straight subtraction 110101 – 11011.

10. Explain about Gates with Logic diagram & Truth table

11. Simplify the following expression in sum of product form & Product sum

form AC’+B’D+A’CD+ABCD

12. Draw and explain the circuit diagram of RS Flip-flop with truth table.

13. Explain in detail about Parallel binary adder & parallel binary sub tractor

14. Draw and explain the circuit diagram of JK Flip-flop with truth table.

15. Explain about Decoder & Encoder

16. Explain about ROM.

17. Explain in detail about I/O bus & Interface Module.

18. Explain in detail about Handshaking method.

19. Explain in detail about Strobe control.

20. Explain about Master Slave flip flop.

Answer for Section A: UNIT : I

1. C 6. A11. B

2. A 7. B12. B

3. A 8. C13. D

4. A 9. A14. A

5. A 10. A15. B

UNIT : II

1. B 6. A11. A

2. A 7. A12. B

3. A 8. B13. A

4. C 9. A14. A

5. B 10. B15. A

UNIT : III

1. B 6. C11. C

2. A 7. A12. B

3. B 8. B13. C

4. C 9. B14. A

5. A 10. D15. B

UNIT : IV

1. D 6. B11. B

2. B 7. A12. C

3. A 8. B13. A

4. B 9. D14. B

5. C 10. C15. B

UNIT : V

1. C 6. C11. B

2. A 7. A12. D

3. C 8. B13. A

4. A 9. D14. A

5. B 10. C15. B

Reference Books & Websites:1. M.Morris Mano,”Computer System Architecture”- Prentice Hall of India ,20002. V.K. Puri, “DIGITAL ELECTRONICS CIRCUITS AND SYSTEMS” - TMH. 3. William Stallings, “Computer Organization and Architecture, Designing for Performance”-PHI/Pearson Education Asia,   2004.4.http://www.tutorialspoint.com/5.http://www.electrical4u.com/6.http://homepage.cs.uiowa.edu/