Waveform based MOSFET dynamic large-signalparameter estimation

B. Toner and V.F. Fusco

Abstract: A multifunctional time domain modelling large-signal data acquisition system is used toacquire and to extract the intrinsic parameters of a MOSFET using only one waveformmeasurement. The measurement is performed at the operating frequency of 2.4 GHz, selected forthe Bluetooth wireless networking protocol. Details of the non-linear measurement system areprovided and its application in the new extraction procedure described. Validation of the extractedparameters is referenced to traditional S-parameter extraction methods and measured large-signalmeasurements.

1 Introduction

The area of CMOS modelling for RF applications hasundergone intensive research over the last few years. Inparticular, the use of MOS technology as a device for thetelecommunications sector has received attention because ofthe low cost and RF potential [1]. To model these devices,industry has tended towards the application of physicalmodels for the intrinsic device behaviour, such as thebipolar simulation (BSIM) 3v3 model [2], suitably calibratedfor the relevant foundry process. Where available, physicalmodels are normally preferred owing to the accuracy of themodel and its scalability over varying device sizes. However,for practical RF modelling, it is necessary to incorporateextrinsic parasitic elements in the model, and oftenoptimisation of the model parameters is required to fitmeasured data [3, 4]. Therefore, the issue of parameterextraction and the fitting of measurement data is stillevident even when physical models are available. Tradi-tional measurement-based equivalent circuit modelling isstill widely used as this approach often yields the mostaccurate method to characterise a device, especially if a lackof foundry process information makes the use of a physicalmodel impractical. In particular, the use of large-signalcircuit models based on measurement is invaluable. This isso, for example, for power devices since such devices arehighly non-linear and suffer from thermal effects, hence aredifficult to model. Other large-signal characterisationtechniques such as load–pull allows optimisation of theoperating regions for the device in areas where models areoften lacking in accuracy, such as high compression andintermodulation [5]. With the advent of large-signalvectorial measurement-based systems [6–8], it has becomepossible to characterise and model the transistor under realoperating conditions [9, 10]. Wei [11] and Wertof [12]illustrated the use of such systems in the analysis and

modelling of bipolar transistors and MESFET devices,respectively. They provided insight into the operation of thedevice under high power operation, and thus were able tohighlight the problems with traditional approaches. How-ever, these methods were still dependent on linear extractionof some of the components, which approximates the chargein the device when operated dynamically [13]. The workpresented in this paper describes a method whereby weestimate the parameters of an equivalent circuit dynamicallywithout the need for multibias S-parameter measurement.This paper illustrates a comparison between dynamicextraction and multibias S-parameter extraction methods.Thereby we attempt to demonstrate the physicality of theextracted values. In addition, dynamically extracted para-meters are entered into a non-linear equivalent circuit modelto provide verification of the model against actual timedomain measured waveforms.

2 Measurement system

The measurement system developed [14] to measure thetime domain waveforms on-chip at the RF CMOS devicemanifold is shown in Fig. 1. Electronically controlledcoaxial switches allow different instruments access to theon-wafer probe station to permit different measurements tobe completed, such as on-wafer noise or S-parameters. Herewe will concentrate on the use of the microwave transitionanalyser (MTA) portion as it enables time domainmeasurements, which are necessary for parameter estima-tion. Passive source and load tuners allow arbitraryimpedances to be presented to the device under test. TheMTA accesses the travelling waves going to and from thedevice via the couplers on either side of the device. Tocorrect the waves to the DUT plane, a large-signalcalibration procedure is used. From the corrected travellingwaves, the voltage and current waveforms presented to thewafer probe tips can be compiled.

3 System calibration

With reference to Fig. 1, using on-wafer standards, astandard 12-term calibration is performed at the DUTplane B, as in the case of a network analyser [15]. How-ever, the non-reciprocal nature of the directional couplersimpose the requirement for a further coaxial calibration to

The authors are with the High Frequency Electronics Laboratories, theDepartment of Electrical and Electronic Engineering, The Queens University ofBelfast, Ashby Building, Stranmillis Road, Belfast BT9 5AH, UK

r IEE, 2003

IEE Proceedings online no. 20031012

doi:10.1049/ip-map:20031012

Paper first received 1st February 2002. Online publishing date: 26 November2003

IEE Proc.-Microw. Antennas Propag., Vol. 150, No. 6, December 2003 451

Plane C in order to separate the reflection tracking errorcoefficients (e10e01,e32e23). Therefore, a one-port calibrationis performed whereby open, short and load standards areplaced at port C, and the first small-signal calibration isused to provide corrected S-parameter measurements of theoutput network between planes B and C. Transmissionmeasurements are then performed between the MTA input(plane A) and plane C. Since the output S-parameter blockis known, the input error coefficients at (e10e01) can beseparated. A similar procedure is repeated at the input toprovide a full two-port calibration. Both the on-wafer andcoaxial calibrations are performed using an interchangeableSOLT scheme. This correction provides data to the probetips using (1)–(4).

a1 ¼ a0e10 þ b1e11 ð1Þ

b2 ¼b3ð1 e33GT2Þ

e32ð2Þ

b1 ¼b0 a0e00

e01ð3Þ

a2 ¼ b2GL ð4ÞHowever, this data is not exactly at the DUT intrinsicdevice plane (Fig. 2), owing to on-wafer pads and connec-tions to the device. To correct for this, a further calibrationstep is required and the signal flow diagram is extended asshown in Fig. 2. The additional S-parameter boxesrepresent the accumulation of device RF pads, the parasiticgate and drain resistances of the device. These S-parametersare obtained by simulating the pad equivalent circuit, Fig. 3.The values for the interconnect equivalent circuit are foundusing a two-step procedure using on-wafer CMOS openand thru standards.

a4 ¼ a1eba þ b4ebb ð5Þ

b4 ¼b1 a1eaa

eabð6Þ

b5 ¼b2ð1 eddGLÞ

edcð7Þ

a5 ¼ a2ecd þ b5ecc ð8ÞThus, from the extra error terms of Fig. 2, additionalequations (5)–(8) can be formulated to give the intrinsicwaveforms at the DUT plane. From these travelling waves,the voltages and currents can be calculated at eachharmonic using

V ¼ffiffiffiffiffiZ0

pðaþ bÞ ð9Þ

I ¼ ða bÞffiffiffiffiffiZ0

p ð10Þ

Finally, the overall waveforms can be computed in the timedomain by summing the harmonic voltage and currentcomponents

V ðtÞ ¼Xn¼h

n¼1

vn cosð2pfnt þ fnÞ ð11Þ

IðtÞ ¼Xn¼h

n¼1

in cosð2pfnt þ fnÞ ð12Þ

where in,vn¼magnitude of harmonic; fn¼ phase of har-monic, and h¼ number of harmonics.

To validate the calibration, the magnitudes and phases ofthe corrected travelling waves referenced to the DUTintrinsic device plane (Fig. 2) are compared when a CMOSthru line is measured. The thru line is assumed to havenegligible electrical length at the operating frequency and itshould be the case that the following conditions areconfirmed.

a4 ¼ b5 ð13Þ

a5 ¼ b4 ð14Þ

On - Wafer probe station

8510A Network analyser

Source tuner

Coaxswitch

Load tuner

Noise meter

Coaxswitch

Coaxswitch

Coaxswitch

Synthesisedsources

Couplers CouplersCoaxswitch

Noisesource

Powersplitter

Isolator

Isolator

Coaxswitch

Microwave transition analyser

ProgrammableDC source

Plane B

Plane A

Plane C

Fig. 1 Measurement system configuration

452 IEE Proc.-Microw. Antennas Propag., Vol. 150, No. 6, December 2003

When measured, the values for these power waves were asfollows at the fundamental frequency of 2.4GHz,

a4¼ 0.03832+69.21 b5¼ 0.03825+70.81

a5¼ 0.01549+23.91 b4¼ 0.01411+25.21

From these values, the voltages and currents are calculatedusing (9) and (10) as

Port 1 voltage¼ 0.354+58.81 Port 2 voltage¼ 0.354+57.81

Port 1 current¼ 0.00422+88.21 Port 2 current¼0.00422+87.21

Here, the port 1 and 2 voltages and currents are identical.Having verified the calibration, the device waveforms can

be measured. Addition of DC bias voltages and currentsallows reconstitution of time domain waveforms as seen atthe intrinsic device terminals at the input and output of thedevice (Fig. 4). Self-biasing was evident, which increased thebias point of the drain current from its quiescent value of11mA to 18mA under 0.5dBm available input power.

4 Parameter estimation

The large-signal equivalent circuit that was chosen torepresent the device is shown in Fig. 5 [16]. The intrinsicmodel consists of only four components, which makes theprocess of parameter fitting straightforward and lesssusceptible to errors in the extraction procedure. In addition

to these components, three extrinsic resistors have beenadded to each terminal of the device. These parasiticcomponents will be measured using traditional methods [4]with optimisation to fit measured S-parameters. The effectof the gate and drain resistances has already been accountedfor as they were lumped with the pad equivalent circuit ofFig. 3 and de-embedded to give the intrinsic waveforms.The voltage drop across the source resistance is accountedfor in the MATLAB based program that extracts theparameters. The intrinsic device the terminal currents can bedescribed in the time domain using

Ig ¼ CgsdVgdt

þ CgddðVg VdÞ

dtð15Þ

Id ¼ Irf þ CdsdVddt

þ CgddðVd VgÞ

dtð16Þ

The intrinsic waveform values for the instantaneousvoltages and currents and their derivatives can be enteredinto the equations and, using an optimisation-basedapproach, the values for the model components can befitted. This approach takes advantage of the incrementalchange in the instantaneous voltages across the device toconstrain the optimisation process. Since the change involtage will be small, it can be assumed that the change incomponent parameters will also be small, thereby enablingan adaptive optimisation strategy to be used, which is nowdescribed. Taking an arbitrary starting point on thewaveforms at time t¼ 0, initial capacitor values are

Pad Pad

DUT intrinsicdevice

probe plane

Cpad 0.28 pF

Cpad0.28 pF

Rpad 175 Ohm Rpad

175 Ohm

Rdrain0.57 Ohm

Rgate3.2 Ohm

L 0.05 nH

L 0.05 nH

Fig. 3 On-wafer interconnect topology

e10

e01

e00 e00 eaa

eab S12

S11 ebb

eba

S22

S 21 edc

ecd

ecc edd

e32

e23

e33 ΓT 2 ΓT1

Γ in

ΓS

Γ in int ΓL intΓL

ΓOUT

b0

a0

a1 a4 b5 b2

b1 a5 b4 a2

b3

a3

output pad DUTinput pad

MTA port

MTA port MTA port

MTA port

Fig. 2 Flow diagram for intrinsic power waves

IEE Proc.-Microw. Antennas Propag., Vol. 150, No. 6, December 2003 453

obtained using S-parameters at the same DC value as theinstantaneous voltage applied at the gate and drain of thedevice. From measured device DC characteristics, an initialguess value was also entered for the current source, Irf(Fig. 5). The optimisation program developed in-housetakes these guess values, along with data from the wave-forms, and varies the component values of Fig. 5 to fit (15)and (16). The next data point on the waveform is thentaken, and the initial guess for this point is taken from theprevious result. A tight constraint on the range of valuesallowable for the components of 73 fF for the capacitorsand 78mA for the current source is used. Again, theprogram optimises to fit the component values to theequations. As the program progresses along the waveform,the moving constraint ensures a continuous solution withchanging bias. The issue of the time delay between theapplication of a change in the gate voltage and itsconsequential effect on the drain current was alsoinvestigated, but for the devices under test it was found tohave no effect.

5 Extraction results

The procedure outlined was implemented on a 300mm/0.25mm CMOS device. The available power to the devicewas set at 0.5dBm, which is about 5dBm above themeasured 1dB compression point. The waveforms wereobtained for a 50O load and entered into the optimisation

0

0.5

1.5

1.0

2.5

2.0

0 5E−11 1E−10 1.5E−10 2E−10 2.5E−10 3E−10 3.5E−10 4E−10 4.5E−10time, s

volta

ge, V

−0.01

0

0.01

0.02

0.03

0.04

0.05

curr

ent,

A

Id

Ig

Vg

Vd

0.25um/300um, Vg =0.85 Vd =1.5, 0.5dBm Int Av. Power, f0_Γl=0.05∠112°, 2f0_Γl=0.139∠97°, 3f0_Γl=0.24∠30°, 4f0_Γl=0.16∠-66°

Fig. 4 Measured voltage and current waveforms

Rg Cgd

Cgs Irf

Rs

Rd

Cds

Vg Vd

Ig Id

intrinsic model

3.2 Ω 0.51 Ω

0.17 Ω

Fig. 5 Large-signal model topology

0

0.6

0.5

0.4

0.3

0.2

0.1

0 0.2 0.4 0.6 0.8 1.21.0 1.4Vg, V

capa

cita

nce,

pF

optimised S-parameter

Fig. 6 Extracted Cgs

0

0.1

0.2

0.3

0.4

0 2.00.5 1.0 1.5 2.5

Vd, V

capa

cita

nce,

pF

optimised S-parameter

Fig. 7 Extracted Cgd

454 IEE Proc.-Microw. Antennas Propag., Vol. 150, No. 6, December 2003

program. 300 uniformly time sampled points were used foreach waveform. The results of the extraction are shown inFigs. 6–9, and are compared with extracted results usingstandard multibias S-parameters. From Figs. 6–8, it can beseen that the optimised capacitance values approximate thevalues extracted using S-parameters methods. However, agreater dependence on the other bias variable is shown,which gives the looping characteristics. The value of thedynamic RF current is also higher than that predicted underDC conditions. This is possibly a result of low frequencydispersion effects [17], an effect also evident in MESFETmeasurements [12]. Small-signal modelling of these devicesreveals that the output resistance varies considerably withfrequency [18] (Fig. 10). The extracted results cover oneloadline in the DCIV plane. To provide a full multibiasmodel, the drain voltage is swept from 0.1V to 2V and thewaveforms measured at each point. This results in coverageof the DC curves as shown in the graph of Fig. 11. At thispoint, the extracted results are collated and surface fittedagainst the gate and drain voltages [19]. For the capacitors,polynomial equations are used and, for the current source,four common models were fitted to the DC curves ofFig. 11 to assess their accuracy. These were the Curtice

Square and Cubic models [20], the Taki model [21] and theStatz model [22]. Table 1 illustrates the standard error [23]associated with each of the models.

As can be seen, the Curtice Cubic model gives the bestaccuracy overall. However, it was found that in the regionof interest in the DCIV plane the Curtice model fails,particularly in the linear region of operation. Analysing theDC curves for each of these models reveals that none of themodels display good accuracy over all regions of interest. Itwas decided to implement the Taki model as it illustratesgood accuracy at lower gate voltages, where the device wasultimately to be biased. In addition, it also follows the DCcurves into the linear region better than the other models,an important consideration under large-signal conditionswhere gain compression may occur.

6 Modelling

To ascertain the accuracy of the full non-linear model, itwas compiled in HP-ADS using symbolically defined device(SDD) components. Equations for the components aregiven in Table 2. Comparison between the measured andmodelled S-parameters display reasonable agreement(Fig. 12). The S22 result gives the worst fit; this hastraditionally been a difficult parameter to fit [24]. These S-parameter fits illustrate well that the extracted parametersare similar to those extracted using direct multibias small-signal S-parameter extraction techniques. Therefore, thevalidity of the optimisation technique in producing physicalvalues for the model components is confirmed. Figure 13illustrates a comparison between measured and simulatedharmonics of the device. For the second and thirdharmonics, a maximum error of 4dB occurs at very highinput power levels. It was noticed that the choice of theequation to model the current source had an effect on theharmonic content of the simulations. In addition, smallchanges in the drain–source capacitor can have a dramaticeffect on the harmonic content at the output [25]. Acomparison of the measured time domain waveforms andthe SDD model simulation results are shown as Figs. 14

0

0.1

0.2

0.3

0 1.0 2.00.5 1.5 2.5

Vd, V

capa

cita

nce,

pF

optimised S-parameter

Fig. 8 Extracted Cds

−0.0050

0.045

0.035

0.025

0.015

0.005

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Vg, V

curr

ent,

mA

Irf DC Guess value

Fig. 9 Extracted Irf

1 2 3 4 5 6 7 8 9 10

0

100

200

300

400

500

600

frequency, GHz

Rds

Fig. 10 Extracted output resistance

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

00 1.00.5 1.5 2.0 3.02.5

Vd, V

I d, m

A

DC curves - Vg=0.5V→1.5 V, 0.1 V step Vd=0V→2.6 V, 0.2 V step

loadlines - Vg =0.85, Vd =0.1 V→2 V, 0.1V step source/load at 50Ω

available power = 0.5 dBm

Fig. 11 Measured loadlines

Table 1 Current model errors

Model type Number of fittingparameters

Standard error

Taki 3 0.0027

Curtice Cubic 5 0.0018

Curtice Square 4 0.0036

Statz 6 0.0019

IEE Proc.-Microw. Antennas Propag., Vol. 150, No. 6, December 2003 455

and 15. Reasonable agreement is obtained for the drainvoltage with an error of 0.1V. For the drain current, agreater degree of error was found as a result of the DCoffset from the quiescent bias point. There are two reasonsfor this: first, at the quiescent point, the Taki model gives anerror of some 1–2mA. Second, the current source value,calculated at 2.4GHz, is higher than that measured at DCowing to dispersion effects [12].

7 Conclusions

In this paper, a procedure for the direct dynamic extractionof the parameters for a large-signal equivalent circuit hasbeen developed. The validity of the procedure has beenshown through comparison with traditional S-parametermethods, and with the compilation of a full non-linearmodel and its small/large-signal simulations. Comparisonswith results obtained from the time domain measurementsystem developed are in agreement. Therefore the method

Table 2 SDD equations

Component Equation Coefficients

a¼3.68096006558E-13

b¼3.12996536367E-13

Cgs Cgs ¼ a þ bVg þ cV 2g þ dV 3

g þ eVd

c¼ 6.65259199461E-13

d¼2.83539533541E-13

e¼1.82794628724E-15

a¼9.65598054995E-13

b¼6.49114147229E-12

c¼ 1.87663950140E-11

d¼2.44914824214E-11

e¼1.49697065305E-11

Cgd Cgd ¼ a þ bVg þ cV 2g þ dV 3

g þ eV 4g þ fV 5

g þ gVd þ hV 2d þ iV 3

d þ jV 4d þ kV 5

d

f¼3.48405269330E-12

g¼1.93250528005E-13

h¼ 9.10353432974E-14

i¼1.111553957849E-14

j¼1.64725443405E-14

k¼ 2.77217575608E-15

a¼0.008605654216427

Irf Irf ¼ a 1 Vg

b

2 tanh c Vd

bVg

b¼ 0.3816147531945

c¼ 2.104493573009

a¼4.62459249028E-13

b¼8.429285251E-13

c¼ 1.775132080E-12

Cds Cds ¼ a þ bVg þ cVg2g þ dV 3

g þ eV 4g þ fVd þ gV 2

d þ hV 3d

d¼1.48929282636E-12

e¼4.1131136996E-13

f¼1.02684329673E-13

g¼ 1.11873439134E-13

h¼2.54855386307E-14

frequency (100.0MHz to 10.10GHz)

measured

SDD circuitS21/6

S12*5

S11

S22

Fig. 12 Measured and simulated S-parameters

−10

−20

−30

−40

−50

−60

−70

0

20

10

−16 −14 −12 −10 −8 −6 −4 −2 0 2 4

available power, dBm

outp

ut p

ower

, dB

m

III

II

I

measuredSDD circuit

Vg =0.85 Vd =1.5 Id =11mA, source/load=50Ω, power= −13.7dBm→2.37dBm, 4dBm step

Fig. 13 Measured and simulated harmonic power

456 IEE Proc.-Microw. Antennas Propag., Vol. 150, No. 6, December 2003

described allows the quick and easy establishment of amodel for non-linear RF simulation without the need formultibias quasistatic measurements.

8 Acknowledgments

The authors would like to thank Parthus Technologies forprovision of the CMOS devices and their sponsorship ofthis research.

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0

2.5

2.0

1.5

1.0

0.5

3.0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

time, ns

volta

ge

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measured

SDD circuit

Fig. 14 Drain voltage

0

0.04

0.03

0.02

0.01

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0time, ns

curr

ent,

A

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measured

SDD circuit

Fig. 15 Drain current

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