Warning: 1.8V Levels - Technologic Systems · 2016-10-06 · Technologic Systems Date Title: Rev: Designer Sheet of TS-7680 MX286 CPU 3 LCD JTAG, I2C NAND, PWM MX286 ARM9 CPU 18 April

Te chnologic Sys t e ms Da te

Tit le :

Re v: De s igne r She e t of

TS-7680 Docume nta t ion

1P1

April 21, 2014

18

Boa rd ca n be powe re d from USB

Cort e x M0 is powe re d up firs t , t he n it cont rols MX286 s t a rt up

- USB De vice t o Cons ole conve rs ion

Cort e x M0 doe s t he s e funct ions :

- Cont rols Blue LED

- Ca n re a d Pus h Swit ch

- Cont rols MX286 powe r up s e que nce

- Me a s ure s Ana log Vin va lue

- Re a ds SD_BOOT Jumpe r

- Boa rd ID

Che ck Ethe rne t LEDs

Note s :

Comme nt s :

- Cont rols MX286 Boot St ra pping

1)

2)

UART0 = RS-232

UART1 = RS-232

UART2 = Modbus

UART3 = STC RS-485

UART4 = Blue or DC

De bug = Cons ole /DC

STC = Scre w Te rm. Conn.

Se ria l Port Us a ge

DC = Da ughte r Ca rd

3) BOM Wa rning:

Se ria l Port RX DMA on MX286 s a ys "mus t be mult iple s of 4 byt e s "

Pa ge 1944TX DMA doe s not s a y re s t rict e d t o 4 byt e mult iple s

For Modbus 1042K ba ud ope ra t ion - us e DMA ?

128MB a nd 256MB RAM s ize s

CAN Opt ionU25, U26 a nd TVS16

or by 8-28VDC, or by 24VAC

JP1 thru JP5 is 5x2 he a de r = 15-3070-7

CAN port s a re opt ions

UART0_RTS --> E2_I2C_CLK

UART0_CTS --> E2_I2C_DAT

DC_DIO_8 = FPGA_SPARE_2 (1.8V)

DC_DIO_9 --> DISABLE_TXEN2#

I/O Diff from TS-7670

GPS_PPS_OUT --> FPGA_DONE

U3.R3 = FPGA_RESET#

U3.U4 = FPGA_SPI_CS#

U3.T4 = FPGA_IRQ

UART1_CTS --> WIFI_IRQ (1.8V)

EN_ETH_3.3V# = No Conne ct

EN_232_TRANS = No Conne ct

- SD2 s igna ls

Wa rning: 1.8V Le ve ls

- WIFI_IRQ

UART2 a nd UART3 cha nge d to SPI

whe n progra mming FPGA

- FPGA_SPARE_0

- FPGA_SPARE_1

UART1_RTS = FPGA_SPARE_0 (1.8V)

U3.U5 = FPGA_SPARE_1 (1.8V)

R33, R34 a nd HD3 not pop

- FPGA_SPARE_2

Cha nge d VIN A/D s ca ling !

Re v.P1 Proble ms :

RAM_1.8V ra il t urns on la t e r t ha n TS-7670

Te s t 24VAC powe r


Tit le :

Re v: De s igne r She e t of2

TS-7680 Cort e x M0 Cont rolle r

April 21, 2014

P1 18

USB De vice Port a nd Cort e x M0

USB De vice PortCort e x M0

SPI

UART

I2C

Progra m

USB

3.3V Re g. for M0

3.3V_A

Blue LED

Pus h Swit ch

MX286

Cont rols

Boot Jumpe r

Pins 2 a nd 3 mus t be high a t PU

3.8V Trip

Brown out De te ct

Sca le = 12.53

20PIO0_22/AD6/CT16B1_MAT1/MISO1

19SWCLK/PIO0_10/SCK0/CT16B0_MAT2

22TMS/PIO0_12/AD1/CT32B1_CAP0

7PIO0_20/CT16B1_CAP0

8PIO0_2/SSEL0/CT16B0_CAP0

1PIO1_19/DTR/SSEL1

2RESET# /PIO0_0

9PIO0_3/USB_VBUS

10PIO0_4/SCL

11PIO0_5/SDA

12PIO0_21/CT16B1_MAT0/MOSI1

13USB_DM

14USB_DP

15PIO0_6/USB_CONNECT/SCK0

16PIO0_7/CTS

17PIO0_8/MISO0/CT16B0_MAT0

27PIO0_23/AD7

4XTAL_IN

6VDD

18PIO0_9/MOSI0/CT16B0_MAT1

23TDO/PIO0_13/AD2/CT32B1_MAT0

24TRST# /PIO0_14/AD3/CT32B1_MAT1

29VDD

30PIO0_17/CT32B0_CAP0/SCLK

31PIO0_18/RXD/CT32B0_MAT0

32PIO0_19/TXD/CT32B0_MAT1

28PIO1_15/DCD/CT16B0_MAT2/SCK1

25SWDIO/PIO0_15/AD4/CT32B1_MAT2

26PIO0_16/AD5/CT32B1_MAT3/WAKEUP

3PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE

5XTAL_OUT

21TDI/PIO0_11/AD0/CT32B0_MAT3

33VSS

U13

LPC11U12_QFN32

R26

30

R28

30

C179

.1 uF

2

1

3

Q14

2

7

RN3-B3.3K

1

8

RN3-A3.3K

Y2

12 MHzC25

22 pF

C26

22 pF

R44

140

USBSingle

4GND

15V

2D-

3D+

5FRAME

6FRAME

P2

CONN_USB_B_RA_BLACK

FB23

600 ohm

2

3

1

4TVS4

BGX50A_SOT143

C180

.1 uF

FB24

600 ohm

C107

.1 uF

C105

.1 uF

R7241.2K

2%2.2-6.0V 3.3V

8VIN

5EN

1VOUT

4GND

7NC

9PAD

6NC

3NC

2NC

U16

REG_AP7361-3.3V_DFN8

C75 C76

1

2 LED6

Blue

1

234

SW1

SW_PUSH_RT_TH

G

S

D

2

6

1

Q5-A

3

6

RN3-C3.3K

4

5

RN10-D1.5K

2

7

RN12-B1.5K

3

6

RN12-C1.5K

4

5

RN12-D1.5K

G

S

D

5

3

4

Q5-B

2VCC

3GND

1RESET#

U12

STM1001S-2.9V_SOT23

1

8

RN4-A3.3K

C47

22 nF

R11620.5K

R1186.04K

R86

0.10 ohms

R87

0.10 ohms

4

5

RN17-D47K

R138

475K

C96

1 uF

USB_DATA_M

USB_DATA_P

M0_SPI_MISO

USB_5V

M0_SPI_CLK

M0_SPI_MOSI

USB_DATA_M

USB_DATA_P

3.3V_A

I2C_CLK

I2C_DAT

DEBUG_TXD

VIN

CPU_RESET#

5V_A

M0_SW_CLK

M0_SW_DIO

PUSH_SW#

DEBUG_RXD

USB_5V

EN_PWR_RAILS#

3.3V_A

3.3V_A

PUSH_SW#

EN_BLUE_LED

EN_BLUE_LED

BOOT_STRAP_0_3

BOOT_STRAP_2

M0_SPI_CS#

JP_SD_BOOT#

3.3V_A

5V_A

3.3V_A

MX286_BLUE_LED

CPU_PSWITCH

PWR_FAIL#

3.3V_A5V_A

PWR_FAIL#

BOARD_ID_PIN24


Tit le :


TS-7680 MX286 CPU

3

LCD

JTAG, I2C

NAND, PWM

MX286 ARM9 CPU

18

April 21, 2014

P1

UARTs , ADC

NC on

MX283

SD Ca rd

SPI Boot

NC on

MX283

NC on

MX283

Audio

SD0

SD2

LCD_00 thru LCD_04

Cont rol Boot Source

LCD_05 a nd 06 bia s low

LCD_RS bia s e d high

LCD_RS low = us e OTP

Se e : EVK s che ma t ic, Pa ge 15

All JTAG ha ve 47K int e rna l PU e xce pt RTCK

NAND Int e rfa ce

PWM output s ca n be 24 MHz

divide d by 16-bit int e ge r

Allows clock 12MHz a nd lowe r

E9 is SD0 PWR_EN on both

EVK a nd Gre e n s che ma t ics

K8 is EVK LCD PWM

J5 is EVK USB_0_ID

K7 a nd L7 a re EVK cons ole

E10 is EVK SD1_PWR_EN

C7 a nd D8 = EVK I2C

E1 is EVK Eth_PWR_EN

F5, F6 a re EVK USB_PWR_EN

F3 is EVK ETH_RESET#

SCK = CLK

CMD = MOSI

D0 = MISO

D3 = CS#

SPI

NC

RESET#

4 CAN s igna ls

a nd ba ll D7

MX286 a dds

on MX283

a nd 286

a nd 286

a nd 286

FPGA

SPI

B14ADC0_HS

C14ADC6

D15ADC5

D13ADC4

D9ADC3

C8ADC2

C9ADC1

C15ADC0

J6AUART0_CTS/DEBUG_RXD

J7AUART0_RTS/DEBUG_TXD

G5AUART0_RX

H5AUART0_TX

K5 AUART1_CTSJ5 AUART1_RTS

L4AUART1_RX

K4AUART1_TX

H6 AUART2_CTSH7 AUART2_RTS

F6 AUART2_RXF5 AUART2_TX

L6 AUART3_CTSK6 AUART3_RTSM5 AUART3_RXL5 AUART3_TX

U3-A

MX286_CPU_IND

U7GPMI_D03/SSP1_D3R8GPMI_D02/SSP1_D2T8GPMI_D01/SSP1_D1U8GPMI_D00/SSP1_D0

R6GPMI_RDN

L8 CAN_RX0

M8 CAN_TX0

N8GPMI_RDY1/SSP1_CMD

N6GPMI_RDY0/USB0_ID

L9GPMI_RESETN

P8GPMI_WRN/SSP1_SCK

C7I2C0_SCL

D8I2C0_SDA

E14JTAG_RTCK

E11JTAG_TCK

E12JTAG_TDI

E13JTAG_TDO

D12JTAG_TMS

D14JTAG_TRST

T6GPMI_D07U6GPMI_D06R7GPMI_D05T7GPMI_D04

P6GPMI_ALE

N7GPMI_CE0N

N9GPMI_CE1N

M7 CAN_TX1

M9 CAN_RX1

P7GPMI_CLE

E10PWM4

E9PWM3

K8PWM2/USB0_ID

L7PWM1/DEBUG_TXD

K7PWM0/DEBUG_RXD

U3-C

MX286_CPU_IND

R5LCD_D23T5LCD_D22U5LCD_D21R4LCD_D20T4LCD_D19U4LCD_D18R3LCD_D17T3LCD_D16

U3LCD_D15U2LCD_D14T2LCD_D13T1LCD_D12R2LCD_D11R1LCD_D10P3LCD_D09P2LCD_D08

P1LCD_D07N2LCD_D06M3LCD_D05M2LCD_D04L3LCD_D03L2LCD_D02K3LCD_D01K2LCD_D00

P5LCD_CS/ENABLE

N1 LCD_DOTCLKN5 LCD_ENABLEM1 LCD_HSYNC

P4LCD_RD_E/VSYNCH

M6LCD_RESET/VSYNCH

M4LCD_RS/DOTCLK

L1 LCD_VSYNC

K1LCD_WR_RWN/HSYNCH

U3-D

MX286_CPU_IND

Boot

SPI

F7SAIF0_BITCLK/UART4_RXD/PWM5

G6SAIF0_LRCLK/PWM4

G7SAIF0_MCLK/PWM3

E7SAIF0_SDATA0/UART4_TXD/PWM6

E8SAIF1_SDATA0/PWM7

D7SPDIF

A4SSP0_CMD

B4SSP0_DATA7/SSP2_SCK

D5SSP0_DATA6/SSP2_CMD

C5SSP0_DATA5/SSP2_D3

B5SSP0_DATA4/SSP2_D0

A5SSP0_DATA3

D6SSP0_DATA2

C6SSP0_DATA1

B6SSP0_DATA0

D10SSP0_DETECT

A6SSP0_SCK

C1 SSP1_CMDE1 SSP1_DATA3D1 SSP1_DATA0B1 SSP1_SCK

B3SSP2_MISO/UART3_RXD

C3SSP2_MOSI/UART2_TXD

A3SSP2_SCK/UART2_RXD

D4SSP2_SS2/SSP2_D2

D3SSP2_SS1/SSP2_D1

C4SSP2_SS0/UART3_TXD

B2 SSP3_MISOC2 SSP3_MOSIA2 SSP3_SCKD2 SSP3_SS0

U3-F

MX286_CPU_IND

1 8RN21-A

10K

3 6RN18-C

47K

LCD_D[00:23]

LCD_D00

LCD_D01

LCD_D02

LCD_D03

UART0_TXD

UART0_RXD

UART2_RXD

UART2_TXD

UART3_RXD

UART3_TXD

EN_SD_3.3V#

I2C_CLK

I2C_DAT

CPU_3.3V

SD0_CLK

SD0_CMD

SD0_D0

SD0_D1

SD0_D2

SD0_D3

YEL_LED#

SD2_D0

SD2_CLK

SD2_CMD

SD2_D1

SD2_D2

SD2_D3

DEBUG_TXD

E2_I2C_CLK

E2_I2C_DAT

ETH_RESET#

DEBUG_RXD

NAND_ALE

NAND_CLE

NAND_CS#

NAND_D0

NAND_D1

NAND_D2

NAND_D3

NAND_D4

NAND_D5

NAND_D6

NAND_D7

NAND_RD#

NAND_WR#

UART1_TXD

UART1_RXD

M0_SPI_MOSI

NAND_RDY

M0_SPI_MISO

M0_SPI_CLK

UART4_TXD

RED_LED#

GREEN_LED#TXD_CAN0

RXD_CAN0

TXD_CAN1

RXD_CAN1

WIFI_IRQ

EN_HOST_USB_5V

FPGA_DONE

EN_MODBUS_3V#

M0_SPI_CS#

DC_DIO_5

DC_DIO_7

DC_DIO_6

MODBUS_FAULT

EN_MODBUS_24V

DC_DIO_4

MX286_BLUE_LED

PUSH_SW#

EN_CAN#

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

DISABLE_TXEN2#

FPGA_SPI_CS#

FPGA_RESET#

UART4_RXD

FPGA_CLK

FPGA_IRQ

LCD_D04

LCD_D05

LCD_D06

FPGA_SPARE_0

FPGA_SPARE_1

FPGA_SPARE_2

ofShe e tDe s igne rRe v:

Tit le :

Da teTe chnologic Sys t e ms

TS-7680 MX286 CPU Powe r

4P1

April 21, 2014

18

Ba t t e ry pin s upplie s curre nt t o cha rge ba t t e y

DCDC_BAT pin is powe r input for DCDC

PSWITCH ca n be drive n t o 3.3V if a s e rie s 10K re s is us e d

Re g VDD1P5 goe s t o nothing

only fe e ds two 1.2K re s is tors

conve rt e rs -- conne ct dire ct t o ba t t e ry

USB

10K PU

to 3.3V

1V

VDD4P2 is a n output --

D16VDD1P5

A13VDD4P2_DCDC

E17VDD5V

C13 VDDA1

F12 VDDD7G12 VDDD6K12 VDDD4G11 VDDD3G10 VDDD2F11 VDDD1F10 VDDD0

G13 VDDIO_EMI10G17 VDDIO_EMI9G15 VDDIO_EMI8L13 VDDIO_EMI7N15 VDDIO_EMI6N13 VDDIO_EMI5M12 VDDIO_EMI4M11 VDDIO_EMI3R13 VDDIO_EMI2P11 VDDIO_EMI1M10 VDDIO_EMI0

J13 VDDIO_EMIQ2K15 VDDIO_EMIQ1R15 VDDIO_EMIQ0

F9 VDDIO18_3G9 VDDIO18_2G8 VDDIO18_1F8 VDDIO18_0

A7 VDDIO33_8E16 VDDIO33_7J10 VDDIO33_6

J9 VDDIO33_5N3 VDDIO33_4J8 VDDIO33_3

H8 VDDIO33_2G3 VDDIO33_1E6 VDDIO33_0

N17 VDDIO33_EMIA9VSS_USBB11VSSA2_AB13VSSA1C16VSSD6L11VSSD5L10VSSD4U1VSSD3J12VSSD2H12VSSD1A1VSSD0F14VSSIO_EMI10F16VSSIO_EMI9H14VSSIO_EMI8L12VSSIO_EMI7M16VSSIO_EMI6P16VSSIO_EMI5P14VSSIO_EMI4T14VSSIO_EMI3U17VSSIO_EMI2R12VSSIO_EMI1R10VSSIO_EMI0J15VSSIO_EMIQ2M14VSSIO_EMIQ1H16VSSIO_EMIQ0H10VSSIO18_2H9VSSIO18_1H11VSSIO18_0B7VSSIO33_8E15VSSIO33_7K11VSSIO33_6K10VSSIO33_5N4VSSIO33_4K9VSSIO33_3J11VSSIO33_2H3VSSIO33_1E5VSSIO33_0

U3-G

MX286_CPU_IND

C41

15 pF

C42

15 pF

1.2V

1.8V

3.3V

0 = Bounda ry

1 = ETM

A15BATTERY

B15DCDC_BATTA17 DCDC_GND

B17 DCDC_LN

A16 DCDC_LP

B16DCDC_VDDA

D17DCDC_VDDD

C17DCDC_VDDIO

B9 DEBUG_JTAG

A11 PSWITCH

A14 RESETN

C10 TESTMODE

A10USB0DMB10USB0DP

B8USB1DMA8USB1DP

C12 XTAL_VDD

D11XTALI_RTC

A12XTALI

C11XTALO_RTC

B12XTALO

U3-H

MX286_CPU_IND

L5 15 uH

C165

.1 uF

C63C153

.1 uF

C154

.1 uF

C68C152

.1 uF

C151

.1 uF

C150

.1 uF

C149

.1 uF

C148

.1 uF

C147

.1 uF

C146

.1 uF

C145

.1 uF

C144

.1 uF

C143

.1 uF

C142

.1 uF

C141

.1 uF

C140

.1 uF

C139

.1 uF

C138

.1 uF

C137

.1 uF

C136

.1 uF

C135

.1 uF

C134

.1 uF

C133

.1 uF

C132

.1 uF

C131

.1 uF

C130

.1 uF

C129

.1 uF

C128

.1 uF

C125

.1 uF

C123

.1 uF

C119

.1 uF

C118

.1 uF

C117

.1 uF

C115

.1 uF

C114

.1 uFC61 C157

.1 uF

C62C156

.1 uF

C65C155

.1 uF

R880.10 ohms

CORE

CP-1.8

CP-3.3

C54

22 uF

R890.10 ohms

C55

22 uF

C56

22 uF

C57

22 uF

C58

22 uFC185

.1 uF

D21

Y1

24 MHz

C186

.1 uF

C161

.1 uF

2 7RN10-B

1.5K

1

8

RN18-A47K

4 5RN18-D

47K2

7

RN18-B47K

CPU_1.8V

CPU_3.3V

CPU_CORE

CPU_3.3V

CPU_1.8V

CPU_CORE

USB_HOST_P

USB_HOST_M

USB_OTG_M

USB_OTG_P

VDD_4P2

VDD_4P2

CPU_RESET#

CPU_3.3V

CPU_1.8V

CPU_PSWITCH

CPU_3.7V


Tit le :


TS-7680 DDR2 RAM

5

DDR2 SDRAM

MX286

64M x 16

128 MB

(128 or 256 MByte )

Le ngth of t his t ra ce is

e qua l t o [CLK + Da ta ] le ngths

18P1

April 21, 2014

NC

NC

256 MB

128M x 16

OR

Da ta = Ave ra ge le ngth of a ll da t a t ra ce s

C176

.1 uF

C175

.1 uF

C174

.1 uF

C173

.1 uF

C172

.1 uF

C171

.1 uF

C170

.1 uF

M8 A0M3 A1M7 A2N2 A3N8 A4N3 A5N7 A6P2 A7P8 A8P3 A9M2 A10P7 A11R2 A12R8 A13

L2 BA0L3 BA1L1 BA2

J8 CKK8 CK#

K2 CKEL8 CS#F3 LDMB3 UDMK7 RAS#L7 CAS#K3 WE#

A1

VD

D0

E1

VD

D1

J9V

DD

2

M9

VD

D3

R1

VD

D4

J1V

DD

L

J2 VREF

R3 A14R7 A15

A2NC0K9 ODT

F1DQ6G2DQ1H7DQ2G8DQ0H1DQ4H9DQ5H3DQ3F9DQ7D1DQ12C2DQ9D7DQ10D3DQ11C8DQ8D9DQ13B9DQ15B1DQ14

F7LDQSE8LDQS#

B7UDQSA8UDQS#

A9VDDQ0C1VDDQ1C3VDDQ2C7VDDQ3C9VDDQ4E9VDDQ5G1VDDQ6G3VDDQ7G7VDDQ8G9VDDQ9

H8

VS

SQ

9

H2

VS

SQ

8

F8V

SS

Q7

F2V

SS

Q6

E7

VS

SQ

5

D8

VS

SQ

4

D2

VS

SQ

3

B8

VS

SQ

2

B2

VS

SQ

1

A7

VS

SQ

0

J7V

SS

DL

P9

VS

S4

N1

VS

S3

J3V

SS

2

E3

VS

S1

A3

VS

S0

E2NC1

U19

DDR2_128MB_X16

C160

.1 uF

R517.87K

R527.87K

N10EMI_A14T9EMI_A13U11EMI_A12T10EMI_A11U13EMI_A10P10EMI_A09U9EMI_A08N11EMI_A07R9EMI_A06R11EMI_A05U10EMI_A04T11EMI_A03U14EMI_A02U12EMI_A01U15EMI_A00

N12EMI_BA2T12EMI_BA1T16EMI_BA0

U16EMI_CASN

P12EMI_CE0N

P9EMI_CE1N

T13EMI_CKE

L17EMI_CLK

L16EMI_CLKN

F17 EMI_D15

F13 EMI_D14

H17 EMI_D13

H13 EMI_D12

J14 EMI_D11

G14 EMI_D10

H15 EMI_D09

G16 EMI_D08

M17 EMI_D07

L14 EMI_D06

P17 EMI_D05

P13 EMI_D04

N14 EMI_D03

P15 EMI_D02

M13 EMI_D01

N16 EMI_D00

L15 EMI_DDR_OPEN_FB

K14 EMI_DDR_OPEN

F15 EMI_DQM1

M15 EMI_DQM0

K16 EMI_DQS0N

J16 EMI_DQS1N

J17 EMI_DQS1

K17 EMI_DQS0

T17 EMI_ODT1

R17 EMI_ODT0

R16EMI_RASN

K13EMI_VREF1

R14EMI_VREF0

T15EMI_WEN

U3-B

MX286_CPU_IND

C158

.1 uF

C177

.1 uF

C178

.1 uF

C103

.1 uF

C106

.1 uF

C104

.1 uF

R547.87K

R537.87K

RAM_1.8V

RAM_A[00:15]

RAM_A00

RAM_A01

RAM_A02

RAM_A03

RAM_A04

RAM_A05

RAM_A06

RAM_A07

RAM_A08

RAM_A09

RAM_A10

RAM_A11

RAM_A12

RAM_A13

RAM_BA0

RAM_BA1

RAM_BA2

RAM_CLK_P

RAM_CLK_M

RAM_CKE

RAM_CS#

RAM_DQM0

RAM_DQM1

RAM_RAS#

RAM_CAS#

RAM_WE#

RAM_1.8V

RAM_DQS0_P

RAM_DQS1_P

RAM_1.8V

RAM_ODT

RAM_D[00:15]

RAM_A14

CPU_1.8V

RAM_DQS0_M

RAM_DQS1_M

RAM_D07

RAM_D03

RAM_D06

RAM_D11

RAM_D14

RAM_D15

RAM_A00

RAM_A01

RAM_A02

RAM_A03

RAM_A04

RAM_A05

RAM_A06

RAM_A07

RAM_A08

RAM_A09

RAM_A10

RAM_A11

RAM_A12

RAM_A13

RAM_A14

RAM_D14

RAM_D15

RAM_BA2

RAM_BA1

RAM_BA0

RAM_CAS#

RAM_RAS#

RAM_WE#

RAM_CKE

RAM_CLK_P

RAM_CLK_M

RAM_ODT

RAM_DQM1

RAM_DQM0

RAM_DQS1_P

RAM_DQS0_P

RAM_DQS1_M

RAM_DQS0_M

RAM_CS#

RAM_D00

RAM_D01

RAM_D02

RAM_D03

RAM_D04

RAM_D05

RAM_D06

RAM_D07

RAM_D08

RAM_D09

RAM_D10

RAM_D11

RAM_D12

RAM_D13RAM_D00

RAM_D02

RAM_D01

RAM_D05

RAM_D04

RAM_D13

RAM_D08

RAM_D12

RAM_D10

RAM_D09

RAM_1.8V


Tit le :


5V Powe r Supply (2000 mA)

C81 mus t be ve ry ne a r U17

Powe r Input

8-28 VDC

.063 hole

6

TS-7680 5V a nd Swit che d Powe r

April 21, 2014

P1 18

Swit che d Powe r

Ris e t ime of both output s

me a s ure d a t ~ 1V/ms

USB a nd MX286

D11 a llows USB to powe r MX286

This will only work if 3.7V

Re g (U7) is powe ring MX286

For 24VAC powe r

C99 mus t be ins t a lle d

JMP mus t not be pop.

Te s t on MAC104

470uF = 4Vpp ripple

with 1A loa d on 5V

1.225V

DC Jumpe r

C98

10 uF

50V

VIN

C80

.1 uF

C81

.1 uFTVS18

43V

FB12

220 ohm

1

2

CN5

CONN_OSTOQ025501_BLACK

GND

C95

1 uF

FB16

220 ohm

6VDD

3EN_FET1

2EN_FET2

7GND

4DRAIN_1

5SOURCE_1

8SOURCE_2

1DRAIN_2

U22

SLG_DUAL_FET_SW_SMT8

C168

.1 uF

SW_5V

1 8RN17-A

47K

2 7RN17-B

47K

G

S

D

5

3

4

Q3-B

D11

D22

-

+

3

4

1

2

FW1

RECT_FW1A_DF10S_1000V

C99470 uF63V

FB15

220 ohm

3VIN

4VIN

1VCC

2SHUTDN#

11SS

8RT

5SYNCH

9RAMP

17SW

18SW

19PRE

15IS

16IS

12OUT

7FB

6COMP

20BOOST

14

PG

ND

13

PG

ND

10AGND 21

PAD

U17

LM5005_SMT20

C49

22 nF

C48

22 nF

C44

330 pF

C43

330 pF

R115

20.5K

R78

41.2K

R1121.58K

D3

C46

22 nF

C45

22 nF

R694.99K

C51

22 uF

C52

22 uF

C53

22 uF

L7

33 uH

R64

5.1 ohm

R65

5.1 ohm

5V_A

5V_A

VIN

HOST_USB_5V

SW_5V

EN_PWR_RAILS#

5V_A

3.3V_A

EN_HOST_USB_5V

USB_5V


Tit le :


TS-7680 AUX Powe r Re g, Boot St ra p

18P1

April 21, 2014

7

Boot

3.3V

ETM off

TEST off

Boot St ra pBia s Re s .

Source

LCD_3 LCD_0

0 0 1 0

1 0 0 1

SPI

SD Ca rd

0 0 0 0 USB

Aux. 3.3V Re g

RC = 4 x e -6

De fa ult st o NAND

0 1 0 0 NAND

RAM 1.8V Re g

RC = 4 x e -6

3.31V typ

1.81V typ

Se le ct Boot

CPU BATT 3.7V

RC = 4 x e -6

3.74V typ

This Re g only re quire d for

e xt ra low powe r mode

FB7 not ins t a lle d whe n

this re g. is us e d

Re quire s a pos it ive puls e on PSWITCH

0.4V = L

1.5V = H

600 mV

3VIN

1GND

2EN

4SW

5GND

6FB

7PAD

U6

REG_1A_RT8016_DFN6

L2

2.2uH

3.3V

C64

FB13

220 ohm

R1119.1K

R8241.2K

C31

100 pF

1 2

3D6

DIODE_BAV99-2_SOT23

C66

4 5RN19-D

10K

3 6RN19-C

10K

2 7RN19-B

10K

1 8RN19-A

10K

1 8RN23-A

10K

2 7RN23-B

10K

3 6RN23-C

10K

4 5RN23-D

10K

0.4V = L

1.5V = H

600 mV

3VIN

1GND

2EN

4SW

5GND

6FB

7PAD

U5

REG_1A_RT8016_DFN6

L1

2.2uH

1.8V

C71

FB25

600 ohm

R8141.2K

C30

100 pF

C72

R11420.5K

2

7

RN21-B10K

3

6

RN21-C10K

0.4V = L

1.5V = H

600 mV

3VIN

1GND

2EN

4SW

5GND

6FB

7PAD

U7

REG_1A_RT8016_DFN6

L3

2.2uH

3.7V

C74

FB22

600 ohm

R7141.2K

C29

100 pF

C73

R557.87K

R90

0.10 ohms

LCD_D[00:23]

AUX_3.3V YEL_LED#

AUX_3.3V

CPU_3.3V

SW_5V

LCD_D01

RAM_1.8VSW_5V

LCD_D00

LCD_D03

LCD_D02BOOT_STRAP_2

BOOT_STRAP_0_3

CPU_3.7VSW_5V

LCD_D04

LCD_D05

LCD_D06

EN_1.8V_RAIL

EN_1.8V_RAIL


Tit le :


TS-7680 Ethe rne t Swit ch

April 21, 2014

P1 18

Auto MDIX is s upport e d

Pola rit y Corre ct ion a ls o s upport e d

2 Port s with Ma g CT

3.3V Ra il = 20 mA

Curre nt Dra in include s

1.8V Ra il = 80 mA

1.2V Ra il = 62 mA

Tota l 88E6020 100 Mbit

1.2V

10/100 Ethe rne t 4-Port Swit ch

St ra ppe d for

RMII MAC mode

with 3.3V Le ve ls

MDI a ddre s s A4 de fa ult s t o "1"

Port 1 LEDs

Port 0 LED

All Port 6 pins

ha ve PU or PD bia s

Pull-downs de fa ult P6

to port dis a ble d mode

Re quire s Re s e t# a s s e rt e d

for 10 ms a ft e r powe r

MX283

"0111" = RMII MAC mode

Powe r Down mode

42 mA on 1.2V ra il

0 mA on othe r ra ils

NC on

MX283

proble m ?

R12051

R12151

R12251

R12351

C206

.1 uF

8 MHz ma x.

PHY 1

PHY 0

Input

a nd OD Output

We a k PU

40MDIO

39MDC

58ROW_0_LED/SMI_ADD4

59ROW_1_LED/NO_CPU

60ROW_2_LED

61COL_0_LED

63COL_1_LED

64COL_2_LED

1COL_3_LED

5AVDD_PLL

50P5_OUT_EN/PWR2.5V

53P5_IN_D2/GPIO2

52P5_IN_D3/GPIO3

44P5_OUT_D3/MODE3

45P5_OUT_D2/MODE2

46P5_OUT_D1/MODE1

47P5_OUT_D0/MODE0

49P5_OUT_CLK

51P5_IN_CLK

54P5_IN_D1

55P5_IN_D0

56P5_IN_DV

34VDD18_OUT

35VDD18_IN

33VDD_33

48P5_VDDO

2VDD_CORE_0

17P6_COL/GPIO5

57VDD_CORE_2

41INT#

43P5_CRS/GPIO0

42P5_COL/GPIO1/FIBER

62EE_VDDO

36VDD_CORE_IN_OUT

37RESET#

38VSS

30P6_IN_D0

4XTAL_OUT

3XTAL_IN

7P0_RX_P

8P0_RX_M

10P0_TX_P

11P0_TX_M

16P1_RX_P

15P1_RX_M

13P1_TX_P

12P1_TX_M

18P6_CRS/GPIO4

19P6_OUT_D3/MODE3

21P6_OUT_D1/MODE1

22P6_OUT_D0/MODE0

27P6_IN_D3/GPIO7

26P6_IN_CLK

24P6_OUT_CLK

23P6_VDDO

28P6_IN_D2/GPIO6

29P6_IN_D1

31P6_IN_DV

32VDD_CORE_1

6I_REF

9P0_AVDD

14P1_AVDD

20P6_OUT_D2/MODE2

25P6_OUT_EN/PWR2.5V

65GND_PAD

U20

88E6020_QFN64

R684.99K

C202

.1 uF

C201

.1 uF

C200

.1 uF

C199

.1 uF

C209

.1 uF

C208

.1 uF

C207

.1 uF

C205

.1 uF

C204

.1 uF

C203

.1 uF

R12651

R12751

C198

.1 uF

R12451

R12551

C197

.1 uF

C194

.1 uF

C193

.1 uF

1 8RN6-A

3.3K

2 7RN6-B

3.3K

3 6RN6-C

3.3K

4 5RN6-D

3.3K

1

8

RN5-A3.3K

2

7

RN5-B3.3K

3

6

RN5-C3.3K

4

5

RN5-D3.3K

E2ENET_CLK

J4 ENET0_COL

J3 ENET0_CRS

G4ENET0_MDC

H4ENET0_MDIO

F3 ENET0_RX_CLK

E4ENET0_RX_ENJ2 ENET0_RXD3

J1 ENET0_RXD2

H2ENET0_RXD1

H1ENET0_RXD0

E3 ENET0_TX_CLK

F4ENET0_TX_EN

G2 ENET0_TXD3

G1 ENET0_TXD2

F2ENET0_TXD1

F1ENET0_TXD0

U3-E

MX286_CPU_IND

1 8RN14-A

1.5K

2 7RN14-B

1.5K

AUX_3.3V

RAM_1.8V

RXD0

RXD1

RXD2

RXD3 MDIO

MDC

PORT1_ACT_LED

PORT0_ACT_LED

PORT1_RX_P

PORT1_RX_M

PORT1_TX_P

PORT1_TX_M

ETH_RESET#

PORT0_RX_P

PORT0_RX_M

PORT0_TX_P

PORT0_TX_M

RXD0

RXD1

RXD2

RXD3

ENET_CLK

RX_DV

TXD0

TXD1

TX_EN

PORT1_TX_P

PORT1_TX_M

PORT1_RX_P

PORT1_RX_M

PORT1_SPEED_LED

MDIO

MDC

RXD0

RXD1

RX_DV

TXD0

TXD1

TX_EN

ENET_CLK

1.2V

AUX_3.3V

AUX_3.3V

LED_ROW_0

PORT0_SPEED_LED

25MHZ_1.8V


Tit le :


TS-7680 Ma gJa cks

April 21, 2014

P1 18

Gre e n

Ye llow

Port # 1

10/100 Ma gJa ck

Gre e n

Ye llow

Port # 0

10/100 Ma gJa ck

Te s t LEDs on Prototype

POE

Boa rd IDPin 22 Pin 23 Pin 24

TS-7670

TS-7680

1

0

1

11

x

M0 Boa rd ID

Pin 16 de le t e d from GND

for la yout purpos e s

As s ume s we a k PU on the s e 3 pins

4RX+

5RX-

6RX_CT

3TX_CT

1TX+

2TX-

7POE_RX

9POE_45

11LLED+

12LLED-

13RLED+

14RLED-

17ALIGN

18ALIGN

15SHD

16SHD

8POE_TX

10POE_78

T2

MAGJACK_POE_10_100

C163

.1 uF

R47

140

R46

140

4RX+

5RX-

6RX_CT

3TX_CT

1TX+

2TX-

7POE_RX

9POE_45

11LLED+

12LLED-

13RLED+

14RLED-

17ALIGN

18ALIGN

15SHD

16SHD

8POE_TX

10POE_78

T1

MAGJACK_POE_10_100

C101

.1 uF

R41

140

R40

140

13

24

HD3

HD_4X1_2.54MM

4

5

RN3-D3.3K

RAM_1.8V

PORT1_TX_P

PORT1_TX_M

PORT1_RX_P

PORT1_RX_M

PORT1_SPEED_LED

PORT1_ACT_LED

RAM_1.8V

PORT0_RX_P

PORT0_RX_M

PORT0_TX_P

PORT0_TX_M

PORT0_SPEED_LED

PORT0_ACT_LED

LED_ROW_0 LED_ROW_0

BOARD_ID_PIN24


Tit le :


10

TS-7680 NAND a nd SD Ca rd

Micro SD Ca rd Socke t

April 21, 2014

P1 18

NAND Fla s h

Fla s h Me mory

Da ughte r Ca rdInt e rfa ceSD Boot Jumpe r

M0 Progra m He a de r

C122

.1 uF

7DATA_0

8DATA_1

1DATA_2

2DATA_3

5CLK

3COMMAND

4VDD

6GND

10FRM2

9FRM1

11FRM3

12FRM4

CN3

CONN_MICRO_SD

C112

.1 uF

9CS#

8RD#

18WR#

17ALE

16CLE

19WP#

12VCC1

37VCC2

29D0

30D1

31D2

32D3

41D4

42D5

43D6

44D7

13GND

36GND

7RDY

6RDY2

10CS2#

U9

FLASH_NAND_16GBIT_TSOP48

C108

.1 uF

1 8RN28-A

10K

2

7

RN28-B10K

3 6RN28-C

10K

4

5

RN21-D10K

14

12

10

8

6

4

2

11USB-

9

7

5GND

3GND

1

13USB+

165V

155V

HD1

HD_2X8_DC_2.54MM_TH

1

MT7

MT125 1

MT8

MT125 1

MT9

MT125

FB11

220 ohm

1 8RN12-A

1.5K

G

S D

1

2 3

Q19

2 7RN27-B

10K

R11320.5K

SD0_CMD

SD0_D3

SD0_CMD

SD0_CLK

SD0_D0

SD0_D1

SD0_D2

NAND_RD#

NAND_WR#

NAND_CS#

NAND_CLE

NAND_ALE

NAND_RDY

AUX_3.3V

NAND_D[0:7]

NAND_D0

NAND_D1

NAND_D2

NAND_D3

NAND_D4

NAND_D5

NAND_D6

NAND_D7

AUX_3.3V

SD2_CMD

RXD_DC_5V

DC_DIO_6

SW_5V

UART4_TXD

M0_SPI_MISO

M0_SPI_CLK

M0_SPI_MOSI

M0_SPI_CS#

USB_OTG_P

USB_OTG_M

DC_DIO_4

DC_DIO_5

DC_DIO_7

JP_SD_BOOT#

AUX_3.3V

EN_SD_3.3V#

M0_SW_CLK

M0_SW_DIO


Tit le :


TS-7680 RTC a nd Hos t USB

11P1

April 21, 2014

18

RTC a nd Hos t USB

RTC a nd Te mp. Se ns orGND gua rd ba nd

SMT RA LEDs

Exte rna l Hos t USB Port

EEPROM 1 Kbyte

For Ca libra t ion Va lue s

The re is a I2C a ddre s s conflict

be twe e n the RTC RAM a nd the EEPROM

EEPROM mus t us e s e pa ra t e I2C bus

Wa rning

X1X2

12SCL

11SDA

9NC

15NC

14VCC

13FREQ_OUT 7

BAT

8GND

10NC

6NC

1

2

3

4

5

20

19

18

17

16

U15

ISL12020_DFN20

C102

.1 uF

C69

2

7

RN4-B3.3K

3

6

RN4-C3.3K

K1

R63649

D20

R25

30

R45140

R42140

R43140

1

2 LED2

Ye llow1

2 LED3

Gre e n 1

2 LED4

Re d

PF1PTC_1100MA_1812

C109

.1 uF

2

3

1

4TVS3

BGX50A_SOT143

Ve rt ica l

Single

USB

4GND

15V

2D-

3D+

5FRAME1

6FRAME2

8FRAME4

7FRAME3

CN1

CONN_USB_A_RA_VERT_SINGLE

FB14

220 ohm

FB17

220 ohm

E2

4VCC

2GND

1I2_CLK

5WP

3I2_DAT

U11

C110

.1 uF

18RN29-A

10K

4

5

RN20-D10K

3

6

RN20-C10K

4

5

RN4-D3.3K

AUX_3.3V

I2C_CLK

I2C_DAT

AUX_3.3V

AUX_3.3V

GREEN_LED#

RED_LED#

YEL_LED#

HOST_USB_5V

SW_5V

USB_HOST_M

USB_HOST_P

E2_I2C_DAT

E2_I2C_CLK

AUX_3.3V

RAM_1.8V

WIFI_32KHZ_1.8V

AUX_3.3V


Tit le :


12

TS-7680 RS-232 Port s

April 21, 2014

P1 18

RS-232 Port s a nd Da ughte r Ca rd He a de rs

RS-232 Tra ns ce ive r

Le ve l s hift e r

3.3V < -- 5V

RS-232/CAN

STC RS-485 Drive r

Dig. Input

Do not us e

19 OE

1 DIR

2 A1

3 A2

4 A3

5 A4

18B1

17B2

16B3

15B4

6 A5

7 A6

8 A7

9A8

14B5

13B6

12B7

11B8

20VCC

10GND

U27

74LVC245_TSSOP20

(CAN_H)

(CAN_L)

(CAN_GND)

8RTS

7CTS

6TXD

5RXD

4GND

2DCD

3DTR

1DSR/RI

9SHLD

10SHLD

J4

RJ45_RA_SHIELD_PJ031_EIA561_CAN

C162

.1 uF

4TXD

1RXD

3TXEN

2 RXEN#

8VCC

6X+

7X-

5GND

U29

SP485EEN_SOIC8

R2260.4

R2360.4

4 5RN29-D

10K

T1

T2

R1

R2

C1+

C1-

C2+

C2-

GND

Vcc

V+

V-

1

2

3

4

5

6

7

89

10

11

12 13

14

15

16

U14

SP202_SOIC16

C159

.1 uF

C126

.1 uFC121

.1 uF

C116

.1 uF

C120

.1 uF

2

7

RN29-B10K

3

6

RN29-C10K

1 2

3D8

DIODE_BAV99-2_SOT23

1

8

RN24-A10K

2 7RN24-B

10K

36RN24-C

10K

4

5

RN24-D10K

AUX_3.3V

RXD_CAN1_5V

RXD2_485_5V

RXD_DC_5V

RXD_CAN0_5V

UART1_TXD

UART0_TXD

UART0_RXD

RXD_CAN1

DC_RXD_3V

RXD_CAN0

CAN1_H

CAN1_L

RS-485_TXEN3

SW_5V

UART3_TXD

RXD3_485_5V

485_PLUS

485_MINUS

RXD3_485_5V

SW_5V

UART1_RXD

SW_5V

SW_5V

DIG_IN

DIG_IN_5VDIG_IN_3V

RXD3_485_3V

DIG_IN_5V

RXD2_485_3V


Tit le :


Mod Bus RS-485 a nd CAN Port s

RS-485 Drive r

RJ45

Modbus

13

TS-7680 Modbus a nd CAN

April 21, 2014

P1 18

Powe r Swit ch

Modbus

CAN_0 Tra nce ive r

24V

CAN_1 Tra nce ive r

24VTJA1040 a llows low

powe r 15 uA mode

Do Not Us e

C167

.1 uF

4TXD

1RXD

3TXEN

2 RXEN#

8VCC

6X+

7X-

5GND

U28

SP485EEN_SOIC8

R1560.4

R1660.4 RS-485

8GND

712V-24V

612V-24V

5DATA-

4DATA+

2GND

3MODE

1GND

9SHLD

10SHLD

J6

RJ45_RA_SHIELD_PJ031

R61649

R62649

FB26

600 ohm

FB27

600 ohm

FB19

220 ohm

FB18

220 ohm

TVS9

30V

R18

60.4

R17

60.4

2

1

3

Q16

2

1

3

Q18

D12

PF3

1500 mA

3

6

RN13-C1.5K

4

5

RN13-D1.5K

G

S

D

2

6

1

Q3-A

3

6

RN17-C47K

1 8RN13-A

1.5K

2 7RN13-B

1.5K

4RXD

1TXD

5VREF

8EN#

3VCC

7CANH

6CANL

2GND

U25

TJA1040_SOIC8

C164.1 uF

21

3

TVS15

NUP2105L_SOT23

C127

.1 uF

R20

60.4

R19

60.4

1 8RN11-A

1.5K

2 7RN11-B

1.5K

3

6

RN11-C1.5K

4

5

RN11-D1.5K

4RXD

1TXD

5VREF

8EN#

3VCC

7CANH

6CANL

2GND

U26

TJA1040_SOIC8

C166.1 uF

21

3

TVS16

NUP2105L_SOT23

C124

.1 uF

R14

60.4

R24

60.4

4 5RN28-D

10K

3

2

1

4Q9

30V

1 2

3 D70

2

1

3 Q10

2

1

3

Q12

R67

4.99K

R103100K

R104100K

2

7

RN16-B47K

1

8

RN16-A47K

3

6

RN16-C47K

4

5

RN16-D47K

SW_5V

MODBUS_24V

RXD2_485_5V

VIN

MODBUS_24VAUX_3.3V

MODBUS_FAULT

EN_MODBUS_3V#

EN_MODBUS_24V

SW_5V

RXD_CAN0_5V

TXD_CAN0SW_5V

RXD_CAN1_5V

CAN1_H

CAN1_L

TXD_CAN1

RS-485_TXEN2

EN_CAN#

EN_CAN#

AN5_CAN_H

AN4_CAN_L

UART2_TXD

DISABLE_TXEN2#


Tit le :


NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NCNC

NC

NC

VBAT mus t powe r up firs t

1.8V Le ve ls

WiFi Ra dio

Silicon

14

TS-7680 WIFI a nd DIO

April 21, 2014

P1 18

All I/O mus t be 1.8V le ve ls 14V Supply

DAC

DIO_2

Sinks 500 mA

Ma x. Input = 30V

DIO_0

Sinks 500 mA

Ma x. Input = 30V

DIO_1

Sinks 500 mA

Ma x. Input = 30V

NC

1VBAT

2BT_FUNC5

3WL_UART_DBG

4WLAN_IRQ

5BT_EN

6FM_EN

7WL_RS232_RX

8WL_RS232_TX

9FM_I2S_FSYNC

10WL_EN

11VIO

12GND1

13SDIO_D3

14SDIO_D2

15SDIO_D1

16SDIO_D0

17SDIO_CMD

18SDIO_CLK

19SLOW_CLK

20FM_IRQ

21FM_SDA

22FM_SCL

23FM_I2S_CLK

24FM_I2S_DI

25FM_I2S_DO

26FM_AUD_RIN

27FM_AUD_LIN

28FMRFOUT

29FMRFIN

30GND2

31FM_AUD_ROUT

32FM_AUD_LOUT

33AUD_FSYNC

34HCI_RX

35HCI_RTS

36HCI_TX

37AUD_CLK

38AUD_OUT

39HCI_CTS

40AUD_IN

41BT_FUNC2

42BT_FUNC4

43VDD_LDO_CLASS_1P5

44GND3

45GND4

46GND5

47GND6

48ANT

49GND7

50GND8

51GND9

52GND10

53GND11

54GND12

55GND13

56GND14

K5

WIFI_MODULE_LSR

C219.1 uF

C220.1 uF

L6COIL_2.7NH_0402

D5

3

2

1

4Q8

15V

1 2

3

D52

ZENER_15V_SOT23

C77.1 uF

G

S

DQ22

TVS8

30V

D19

40V

1

8

RN9-A1.5K

2

7

RN9-B1.5K

G

S

DQ21

TVS6

30V

D13

40V

1

8

RN20-A10K

2

7

RN20-B10K

G

S

DQ20

TVS7

30V

D18

40V

R97

0.10 ohms

R95

0.10 ohms

R99

0.10 ohms

3

6

RN10-C1.5K

WIFI_32KHZ_1.8V

RAM_1.8V

SD2_D0

SD2_D1

SD2_D2

SD2_D3

SD2_CMD

SD2_CLKWIFI_IRQ

SW_5VVIN

14V

DIO_2

AUX_3.3V

DIO_2_IN

DIO_0

AUX_3.3V

DIO_0_IN

DIO_1

AUX_3.3V

DIO_1_IN

BT_CTS

BT_EN

BT_RTS

BT_RXD

BT_TXD

WL_EN

EN_LS_OUT_0

EN_LS_OUT_1EN_LS_OUT_2


Tit le :


TS-7680 FPGA

April 21, 2014

P1 18

If SPI_CS# is high a t POR

FPGA configure s from NVCM

unle s s it is bla nk, t he n it

t rie s t o loa d from SPI Fla s h

If SPI_CS# is low a t POR

FPGA wa it s for e xt e rna l SPI

configura t ion.

Als o us e d t o writ e t o NVCM

FPGA re quire d for:

- Auto-485 for two UARTs

- PWMs for DACs

iCE40 FPGA

Schmit t Trig. on a ll Input s

10 MHz min clock for PLL

No Int e rna l clock

All pins ha ve prog. PU re s is tor

- providing s e ria l port MUXing

1.8V

Ba nk 0

PLL_1 ca n not be us e d

Ba nk 0

- Blue Tooth Le ve l Shift ing

- Addit iona l I/O

1.2V Re gula tor

- Da ughte r Ca rd Funct ions

1.8V

50MHz

12MHz

Ba nk 0 = 1.8V le ve ls

All othe r Ba nks = 3.3V

NC

Config

D12IO_B1

J6VCC_B3

J12IO_B1

L14IO_B1

P4IO_B2

M7IO_B2

L1IO_B3

C9IO_B0

D10IO_B0

J8

GND

M9IO_B2

K11IO_B1

P9IO_B2

L3

GND

C4IO_B0

P11SPI_SI

K4IO_B3

G9

GND

G4IO_B3

E1IO_B3

J4VCC_CORE

C8PLL_VCC_1

M5VCC_B2A3

IO_B0

F7

GND

D7IO_B0

J14

GND

N14IO_B1

A9

GND

A12IO_B0

L8IO_B2

E3VCC_B3

A1IO_B0

C14IO_B1

L5IO_B2

C10IO_B0

D14IO_B1

B14IO_B1

E4IO_B3

F8VCC_CORE

F3IO_B3

E11IO_B1

A2IO_B0

G6VCC_CORE

D5IO_B0

J9VCC_B2

A4IO_B0

F12IO_B1

P10IO_B2

P1IO_B3

H7

GND

M1IO_B3

L12IO_B1

F6VCC_B0

G11IO_B1

D1IO_B3

J3IO_B3

M3IO_B2

N1IO_B3

K14IO_B1

M14NC

H9VCC_CORE

H1IO_B3/GB

L4IO_B2

H3IO_B3

J11IO_B1

F4IO_B3

P5IO_B2

J1IO_B3

A8VCC_B0

K3IO_B3

P8IO_B2/GB

P2IO_B2

M6IO_B2

K12IO_B1

M4IO_B2

M12IO_B1

A13VPP_FAST

A14VPP_2V5

A5IO_B0

A10IO_B0

A6IO_B0/GB

L7PLL_GND_0

M8PLL_VCC_0

H6

GND

H4IO_B3

J7VCC_CORE

B1IO_B3

F9VCC_B1

C11IO_B0

C5IO_B0

E12IO_B1

C12IO_B0

C3IO_B3

P3IO_B2

G7

GND

C6IO_B0

F14IO_B1/GB

D11IO_B0

D6IO_B0

M10C_DONE

L10C_RESET#

D8PLL_GND_1

P7IO_B2/GB

G8

GND

P12SPI_CLK

P13SPI_SS#

L11SPI_VCC

L6IO_B2

L9IO_B2

E14IO_B1

H14VCC_B1

D3IO_B3

P6

GND

A11IO_B0

A7IO_B0/GB

C7IO_B0

G14IO_B1/GB

F1

GND

D9IO_B0

H8

GND

M11SPI_SO

K1VCC_B3

P14IO_B1

D4IO_B3

F11IO_B1

G1IO_B3/GB

H12IO_B1

H11IO_B1

C1IO_B3

G12IO_B1

G3IO_B3

U21

LATTICE_ICE40_8KLUT_CS132

1

8

RN27-A10K

3

6

RN27-C10K

C196.1 uF

C67

10 uF

R2160.4

4

5

RN27-D10K

C187.1 uF

C184.1 uF

C192.1 uF

C190.1 uF

C189.1 uF

C191.1 uF

C183.1 uF

C181.1 uF

C169.1 uF

C182.1 uF

C188.1 uF

C111.1 uF

C195.1 uF

1 2

3D7

DIODE_BAV99-2_SOT23

2% FT1.20V1.5-6.0V

3% LPLow = LP

0.3V = L1.0V = H

1VIN

3EN

5VOUT

2GND

4ECO

U24

REG_NCP585D_1.2V_SOT23

C70

10 uF

3 6RN14-C

1.5K

1 8RN10-A

1.5K

4 5RN14-D

1.5K

UART2_RXD

UART2_TXD

UART3_RXD

FPGA_SPI_CS#

AUX_3.3V

1.2V

FPGA_DONE

FPGA_RESET#

AUX_3.3V

1.2V

1.2V

AUX_3.3V

RS-485_TXEN3

250KHZ_PH0

E2_I2C_CLK

RAM_1.8V

UART2_TXD

AUX_3.3V

RAM_1.8V 1.2V

DC_RXD_3V

UART3_RXD

25MHZ_1.8V

BT_CTS

BT_EN

BT_RTS

BT_RXD

BT_TXDUART4_RXD

WL_EN

FPGA_25

FPGA_27

FPGA_28

FPGA_29

FPGA_30

FPGA_31

FPGA_32

FPGA_33

FPGA_34

FPGA_35

FPGA_36

FPGA_37

250KHZ_PH1

DAC_PWM_1

DAC_PWM_2

DAC_PWM_3

DIG_IN_3V

DIO_0_IN

DIO_2_IN

EN_LS_OUT_0

EN_PU_AD0

EN_PU_AD1

EN_PU_AD2

EN_PU_AD3

EN_RELAY_1

FPGA_CLK

FPGA_IRQ

E2_I2C_DAT

RS-485_TXEN2

RXD3_485_3V

UART3_TXD

UART4_TXD

UART2_RXD

RXD2_485_3V

DAC_PWM_0

DIO_1_IN

EN_LS_OUT_1

EN_LS_OUT_2

EN_RELAY_2

FPGA_SPARE_0

FPGA_SPARE_1

FPGA_SPARE_2

ENET_CLK


Tit le :


Re la ys

16

TS-7680 DACs a nd Re la ys

April 21, 2014

P1 18

Ga in = 3.3

0-10V Out

150 Hz low pa s s filt e r

Ga in = 3.3

0-10V Out


Ga in = 3.3

0-10V Out


Ga in = 3.3

0-10V Out


10-bit DACs1

2

3

5

4

K2

RELAY_SPDT_5V_5A_TH

1

2

3

D4

DIODE_BAT54-CC_SOT23

G

S

D

2

6

1

Q4-A G

S

D

5

3

4

Q4-B

+

-2

31

11

4

U4-A

R75

41.2K

C82

.1 uF

R107

100K

C215.1 uF

C214.1 uF

R27

30

C33

3.3 nF

R32

30

1

2

3

5

4

K3

RELAY_SPDT_5V_5A_TH

G

S

D

2

6

1

Q6-A G

S

D

5

3

4

Q6-B

R74

41.2K

R105

100K

C213.1 uF

C212.1 uF

C34

3.3 nF

R31

30+

-6

57U4-B

+

-9

108U4-C

+

-13

1214U4-D

R76

41.2K

R106

100K

C211.1 uF

C210.1 uF

C35

3.3 nF

R30

30

R77

41.2K

R108

100K

C217.1 uF

C218.1 uF

C36

3.3 nF

R29

30

DAC3

DAC2

3

6

RN9-C1.5K

4

5

RN9-D1.5K

R92

0.10 ohms

R91

0.10 ohms

4 5RN25-D

10K

36RN25-C

10K

2 7RN25-B

10K

18RN25-A

10K

3 6RN26-C

10K

45RN26-D

10K

1 8RN26-A

10K

27RN26-B

10K

SW_5V

SW_5V

14V

DAC_0

EN_RELAY_1

RELAY_1_NO

RELAY_1_NC

RELAY_1_COM

SW_5V

EN_RELAY_2

RELAY_2_NO

RELAY_2_NC

RELAY_2_COM

DAC_1

DAC_2

DAC_3

DAC_PWM_1

DAC_PWM_2

DAC_PWM_3

DAC_PWM_0


Tit le :


17

TS-7680 Ana log

April 21, 2014

P1 18

Ana log In Cha nne ls

0-10V Input

0-10V Input

0-10V Input

0-10V Input

24V

Bipola r Ana log Input s

R33 a nd R34 not popula t e d

-5V to + 5V Input Ra nge

By a djus t ing re s is t or va lue s

All A/D Input s ca n be conve rt e d

to Bipola r, but mus t re move FETs

2

1

3

Q11

4

5

RN15-D1.5K

2

7

RN15-B1.5K

3

6

RN15-C1.5K

1

8

RN15-A1.5K

1 8RN22-A

10K

3 6RN22-C

10K

2 7RN22-B

10K

4 5RN22-D

10K

D14

40V

R80

41.2K

R507.87K

C221

.1 uFR38240

G

S

DQ25

R98

0.10 ohms

2

1

3

Q13

D15

40V

R73

41.2K

R567.87K

C216

.1 uFR37240

G

S

DQ26

R96

0.10 ohms

2

1

3

Q15

D16

40V

R79

41.2K

R577.87K

C222

.1 uFR35240

G

S

DQ24

R94

0.10 ohms

2

1

3

Q17

D17

40V

R83

41.2K

R587.87K

C113

.1 uFR36240

G

S

DQ23

R93

0.10 ohms

21

3

TVS14

NUP2105L_SOT23

21

3

TVS13

NUP2105L_SOT23

R85

41.2K

R60

7.87K

C78

.1 uFR33240

R84

41.2K

R59

7.87K

C79

.1 uFR34240

R102100K

R101100K

R134

475K

R135

475K

R137

475K

R136

475K

AUX_3.3V

ADC0

EN_CL_0

AN_DIN_0

AUX_3.3V

ADC1

EN_CL_0

AN_DIN_1

AUX_3.3V

ADC2

EN_CL_0

AN_DIN_2

AUX_3.3V

ADC3

EN_CL_0

AN_DIN_3

EN_PU_AD0

EN_PU_AD1

EN_PU_AD2

EN_PU_AD3

ADC4 AN4_CAN_LADC5 AN5_CAN_H

1.2V1.2V

1.2V

1.2V

1.2V

1.2V


Tit le :


Top Row Bot tom Row

Le ft Le ft

18

TS-7680 Scre w Te rm. Conne ctors

April 21, 2014

P1 18

DC STC He a de r

Right Right

24 Scre w Te rm. Pos it ions

1

2

3

4

5

6

7

8

9

10

11

12

P1-A

13

14

15

16

17

18

19

20

21

22

23

24

P1-B

16

14

12

10

8

6

4

2

15

13

11

9

7

5

3

1

18

20

22

24

34

26

28

30

32

17

19

21

23

25

27

29

31

33

36

38

40

35

37

39

HD4

HD_20X2_2.54MM

R130

Ze ro

R131

Ze ro

R132

Ze ro

RELAY_1_NO

RELAY_1_COM

RELAY_1_NC

RELAY_2_NC

RELAY_2_COM

RELAY_2_NO

AN_DIN_0

AN_DIN_1

AN_DIN_2

AN_DIN_3

485_PLUS

485_MINUS

DIO_0

AN4_CAN_L

AN5_CAN_H

DAC_2

DAC_3

DAC_3

DAC_2

DAC_1

DAC_0

AN5_CAN_H

AN4_CAN_L

AN_DIN_1

AN_DIN_0

250KHZ_PH0

VIN

SW_5V

RELAY_1_NO

RELAY_1_NC

RELAY_1_COMAUX_3.3V

DIO_1

DIO_2

DAC_0

DAC_1

DIG_IN

TXD_CAN0

RXD_CAN0_5V

DIG_IN

DIO_1

DIO_0

AN_DIN_3

AN_DIN_2 DIO_2

485_PLUS

485_MINUS

FPGA_25

FPGA_27FPGA_28

FPGA_29FPGA_30

FPGA_31FPGA_32

FPGA_33FPGA_34

FPGA_35FPGA_36

FPGA_37

250KHZ_PH1

Documents

Warning: 1.8V Levels - Technologic Systems · 2016-10-06 · Technologic Systems Date Title: Rev: Designer Sheet of TS-7680 MX286 CPU 3 LCD JTAG, I2C NAND, PWM MX286 ARM9 CPU 18 April