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Wafer-Level Packaging Inflection
Breakout Session 2
2011 Investor & Analyst Meeting
March 23, 2011
Sesh Ramaswami
Senior Director
Silicon Systems Group
Applied Materials
External Use
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Safe Harbor Statement
This presentation contains forward-looking statements, including those
regarding Applied’s products, strategic position and growth opportunities.
These statements are subject to known and unknown risks and
uncertainties that could cause actual results to differ materially from those
expressed or implied by such statements, including but not limited to: the
level of demand for Applied’s products, which is subject to many factors,
including: uncertain global economic and industry conditions, business
and consumer spending, demand for electronic products and
semiconductors, and customers’ utilization rates and new technology and
capacity requirements; Applied’s ability to (i) develop, deliver and support
a broad range of products and expand its markets, (ii) obtain and protect
intellectual property rights in key technologies, and (iii) attract, motivate
and retain key employees; and other risks described in Applied’s SEC
filings. All forward-looking statements are based on management’s
estimates, projections and assumptions as of March 23, 2011, and
Applied undertakes no obligation to update any forward-looking
statements.
2
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Double
Patterning
22nm Line and Space
Major Inflections Adding Complexity
3
Source: Chipworks, Micron Technology
Copper
Damascene
Through-Silicon
Via (TSV)
3D Device
Interconnect Advanced
Patterning
Advanced
Packaging Transistor
External Use
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End Markets Driving Advanced Packaging
Mobility
Enhanced Multimedia
Form Factor
Longer Battery Life
4
Servers
Break Through Memory Wall
– Multi-Core CPU Support
Energy Conscious Processing
External Use
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Advanced Packaging Solves “Memory Wall” Issue
5
Logic Fast Memory Slow Logic Fast Memory Fast
Increased DRAM Density, Reduced DRAM-CPU Latency
DRAM DIMM
8X Capacity – Multi DIMM (conceptual)
8X Capacity – Single DIMM
Increase in Parallel Connections
External Use
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Mobile Devices Require Enhanced Chip Performance Stacked Chip vs. Package-on-Package Capability
6
8X Bandwidth
Improvement
50% Less
Power
Consumption
35% Smaller
Package Size
Source: ITRI, Nokia Semicon Taiwan 2010
Micron Hybrid Memory Cube, cnet 2/10,/11
External Use
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Migration to Higher Functionality 3D Technologies
Silicon Systems Group 7
Traditional
Wire Bonding
Substrate
Ve
rtic
al
Inte
gra
tio
n
Functionality RDL = Redistribution Layer
TSV = Through Silicon Via
Logic
Flip Chip
Substrate
Bump
Logic
Flip-Chip
Bump + RDL
Stacked Die w/TSV
Logic
Memory
Substrate
Flip-Chip
Bump + RDL + TSV
Chip-1 Chip-2
Substrate
Si
Memory
Processor
Memory
Memory
Memory
Substrate
Flip-Chip
Memory
Controller
Memory
Memory
Memory
Substrate
Flip-Chip
Memory
Stacked Die
Elpida, August 27 2009
Qualcomm, July 19 2010
Xilinx, Oct 26 2010
Samsung, Jan 1 2011
Micron, Feb 11 2011
External Use
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8
Source: Gartner July ‘10, wafer starts in 12” equivalents
Foundry Capacity (Millions of wafer starts)
65nm ≤32/28nm 90nm
45/40nm
Calendar Year
Bump Ramp
Begins Bump + TSV Ramp
Begins
Long Runway Ahead for Wafer-Level Packaging
External Use
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Enabling Production Ramp of Wafer-Level Packaging
9
Bump (Flip Chip) TSV Stack
Source: Gartner, March, 2011
Projected total served market
>$800M in 2012
KEY PRODUCTS
Silvia™ Etch System
Proven high aspect ratio trench etch
Raider™-S Electrochemical Deposition
Leading gap fill capability
Charger™ PVD System
Highest productivity
External Use
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Full Portfolio Solution for Bump/RDL & TSV Processes
Dry Etch
CMP
ECD
Cleans, Wet Etch, Strip
Bonding
PVD
Dielectric CVD
Thinning
Bump/RDL TSV
Applied
Core Products
Collaboration
Strong product portfolio and collaboration creates optimal
synergistic solution for customers
10
Semitool
Acquisition
External Use
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External Use
R 140
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B 0
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12
External Use
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B 0
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R 6
G 30
B 60
13
External Use
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Dual Damascene BEOL
14 Silicon Systems Group
Backside
TSV (IC Fab)
TSV Etch
CVD Oxide Liner
PVD Barrier/Seed
Copper Plating
CMP Cu
Thickness~700µm
Depth~50µm
Frontside
Silicon
Bump, RDL (1st)
PVD RDL
Plating RDL
PVD Under-bump
Plating Bump
Wet Etch PVD films
Depth~750µm
~2µm
TSV
[Packaging Fab]
Bonding, Thinning
CMP Silicon
Silicon Recess Etch
CVD Dielectric Passivation
CMP to expose Cu TSV
~5µm
~10µm
Bump
Polymer
Polymer
Cu RDL Cu UBM
Mn-1
Mn
Mn-1
M0
Bump
Polymer
Polymer PVD UBM
PVD RDL
Memory
Processor
Memory
Memory
Memory
Board
Flip-Chip
Memory
Bump, RDL (2nd)
PVD RDL
Plating RDL
PVD Under-bump
Plating Bump
Wet Etch PVD films
External Use
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Strong Portfolio in Through-Silicon Via
Dry Etch CVD Ox Liner PVD CuBS ECD Cu Cu CMP
Profile/Depth,
Productivity
Step Coverage,
Parametrics
Step Coverage,
CoO
Hi Quality, Void
Free Fill
Endpoint,
Defects
15
Producing the most integrated TSV development lots in the industry
Demonstrated
Performance
Applied
Product
Key
Requirement
External Use
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In-House, End-to-End Packaging Development
16
. . . \ s anj os e\ s heet \ kt ca0330. dgn Sep. 27, 1999 12: 22: 24
Litho
BEOL
FEOL
Thin Film
PDC
External Use
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Opportunity Growth with Packaging Inflection
Growth Complexity Inflection
New chip architecture
Many new process steps
Time-to-market value of
integration
Mobile device and
cloud computing are
demand drivers
Form factor and chip
performance require
bump at ~40nm
and TSV at ~20nm
~$800M opportunity in
2012
TSV ramp to come
17
+ =
*2012 market opportunity - Source: VLSI 2010, Gartner Mar’11 (2012 forecast)